JPH02311931A - Information processor - Google Patents

Abstract

PURPOSE:To prevent the processing delay of a CPU that is caused by the occurrence of an interruption by controlling the register holding the data processed with a program into a data store inhibiting state out of plural registers at occurrence of the interruption and at the same time outputting the data of the inhibited register for execution of a due process when the interruption is reset. CONSTITUTION:An information processor includes the register groups 1a - 1m, the selectors 3a - 3m, an interruption processing part 5, and a paging control part 7. When an interruption occurs during execution of a program, the writing operation is inhibited to the register group that holds the data processed by the program among those groups 1a - 1m. When the interruption is reset, the data on the register whose writing operation is inhibited is supplied to the selectors 3a - 3m. Based on this data, the program is carried out. Thus it is possible to prevent the delay of the CPU processing time due to the occurrence of an interruption.

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial Application Field) The present invention relates to mispage processing control, particularly in information processing 'IAn using virtual memory paging.

(Prior Art) In recent years, virtual storage systems have been used that utilize virtual storage spaces suitable for processing by users. Among the virtual storage systems mentioned above, there is a paging system in which memory is divided into blocks called pages, and users can freely use the pages.

The operation of the CPU using the conventional paging method described above can be performed using microinstructions! The execution of the microprogram 1011 will be explained using the schematic flowchart of FIG.

First, when executing process 1, the microprogram accesses the main storage device by a load instruction, and if the address to be accessed exists on the page, the microprogram accesses the address and executes process 1. When processing 1 is completed, the microprogram accesses the main storage device by a load instruction in the same manner as processing 1 to execute processing 2, and executes processing 2 up to processing n-1. When the microprogram executes process 0, if the address to access m@a by the load instruction does not exist on the page, a so-called miss page occurs. When a mispage occurs, the operation system (O8)
The relevant page is loaded from the secondary storage device, usually a magnetic disk, into the main storage device and processing is executed.

When loading a corresponding page from the above-mentioned magnetic disk device, it takes a considerable amount of time to load because the I10 (input/output device) is used, which affects the processing capacity of the CPU.

(Problems to be solved by the invention) Conventional 4! In this case, when a miss page occurs, it takes time to load the corresponding page from the magnetic disk device, which may lead to a decrease in the processing capacity of the CPLJ.

In addition, after the page is loaded from the main storage device to the magnetic disk device and the mispage interrupt is restored, the microprogram will not retain the data at the time of the interrupt occurrence.
In order to execute from process 1 again, v equipped with this MCPLJ
There was a problem in that the overall processing was degraded.

The present invention has been made in view of the above, and its purpose is to retain data when an interrupt occurs,
An object of the present invention is to provide an information processing device that prevents a reduction in CPLJ processing time by executing processing from the time when the interrupt occurs when the interrupt returns.

[Structure of the Invention] (Means for Solving the Problems) In order to achieve the above object, the present invention provides a plurality of register groups that hold data processed by a program during execution of the program, and a plurality of registers. a plurality of selectors that select an arbitrary group of registers among them and output the data held in the arbitrary register; an interrupt discrimination means that discriminates the interrupt when an interrupt occurs during execution of the program; 1IIItl1 means for prohibiting writing to a register group that holds data processed by the program among the plurality of register groups when the interrupt is determined by the determining means; The present invention further comprises a second control means for outputting, by the selector, data held in a data write inhibited register by the first iIJtl1 means.

(Operation) In the information processing device having the above configuration, when an interrupt occurs during execution of a program, a register group that holds data processed by the program among a plurality of register groups is prohibited from being written. When the interrupt returns, the data of the write-inhibited register among the plurality of registers is supplied to the selector, and the program is executed based on the data, so that delays in CPU processing time due to the occurrence of the interrupt can be prevented.

(Example) Hereinafter, the present invention will be explained in detail using the drawings.

FIG. 1 is a block diagram showing the configuration of a practical example of information processing according to the present invention.

The information processing device includes register groups 18 to 1m (registers), selectors 3a to 3- (selectors), an interrupt processing section 5 (interrupt discrimination means), and a basic control section 7 (first
1!1m means, 2111tm means).

The register groups 18 to 1m include work registers that temporarily store data during execution of a microprogram that controls the operation of the CPU using microinstructions.

Further, the register groups 1a to 1- are provided with a microprogram counter that is a counter indicating an address where an instruction to be executed by the CPU (central processing unit) is stored.

That is, the register groups 18 to 1m each include a work register and a microprogram counter, and sequentially hold data processed by the microprogram to 1a to 1m. Note that the above register groups 1a to 1
-, write permission/write prohibition is controlled by a control signal from the paging control unit 7.

The selectors 38 to 3m are switched and selected by a control signal from the paging control unit 7, which will be described later.During normal execution when no interrupt occurs, any one of the register groups 1a to 11 is selected. The data of the selected register group is output. The output data is supplied to the microprogram and used for next processing.

Here, the main memory bag @(
Virtual memory paging is used to effectively utilize memory space (not shown).

Here, it is assumed that a so-called miss page occurs, in which an address accessed by the main memory device by a load instruction or the like does not exist on the page using paging of the virtual memory. The interrupt processing section 5 outputs an interrupt signal to the paging control section 7 upon receiving a signal indicating an interrupt from the operation system (O8). On the other hand, the interrupt processing unit 5
When a signal indicating m-return of the interrupt is received from 8, a return signal is output to the paging control section 7.

When an interrupt signal is input from the interrupt processing unit 5, the paging v1t111 unit 7 prohibits writing to a write-enabled register group that holds data at the time of occurrence of a miss page among the register groups 18 to 111. For example, if register group 1■ is write-enabled when an interrupt occurs, the paging control unit 7 disables write to register group 1■, and changes the other register groups 1a to 1-1 from write-prohibited to write-enabled. .

On the other hand, when a return signal is input from the interrupt processing section 5, the paging control section 7 enables writing of the register group 1-, which is prohibited from writing, and outputs the data held in the register group 1- from the selector 1m. The output data causes the microprogram to start processing from the time the interrupt occurs. Note that the paging@control unit 7 stores the address at which the interrupt occurs and passes the address to the microprogram, thereby starting processing from the time the interrupt occurs.

Next, the operation of this embodiment will be explained using a schematic chart 70-1r in FIG.

First, after the power is turned on, the CPU starts up and the microprogram starts processing. The microprogram executes process 1, and when process 1 ends, it executes process 2 and continues up to process n-1. In the above processing 1 to processing n-1, data held in any register group from one register group is output from the selector for normal operation. When a mispage occurs after the completion of processing n-1 and a signal indicating an interrupt is received from O8, the interrupt processing section 5 outputs an interrupt signal to the paging control section 7. Basing control section 7
For example, the registers in register group 1 are prohibited from being written to in order to retain the data at the time of occurrence of the interrupt. On the other hand, the paging control unit 7 makes the other register group, which is already write-prohibited, write-enabled so that it can hold data. The paging l1w11 unit 7 outputs the data of the register group by outputting control signals to the selectors 3a to 311 in order to output the data held in the register group for which writing is enabled.

Upon receiving a signal indicating the return of the interrupt from O8, the interrupt processing section 5 outputs a return signal to the paging control section 7. When the return signal is input, the paging tIQt1 section 7 enables writing of the write-prohibited register group 1m, and outputs the data of the register group 1m from the selector 3. By outputting the data of the register group 11, the microprogram executes from process n using the data and the address at the time of occurrence of the interrupt from the paging 111tm unit 7. On the other hand, the paging control unit 7 controls the write-prohibited register group to write-enable.

As a result, since the process n in which the mispage occurred is executed after the interrupt process returns, a delay in the CPU processing time can be prevented compared to the conventional process in which the process 1 is executed at the beginning of the process.

In this embodiment, job LJO, which is the work unit of the program,
Although the case where there is one item 8) has been described, when there are multiple jobs, the use level of the register group is deepened in response to multiple miss pages. On the other hand, if the job starts execution immediately after the interrupt processing returns, the level of the register group becomes the value at the time the interrupt occurred. That is, the level at the time the interrupt occurs becomes valid, and instructions such as a load instruction are executed starting from the instruction at the time the interrupt occurs.

Further, in this embodiment, a miss page has been described as an example of an interrupt, but the present invention is applicable not only to a miss page but also to other interrupts.

As described above, the present invention can be implemented with various modifications within the scope of the invention.

[Effects of the Invention] As explained above, according to the present invention, when an interrupt occurs, the register that holds data processed by the program among the plurality of registers is prohibited from holding data v11.
On the other hand, when the interrupt returns, the data in the register that is prohibited from being held is output and processing is executed using that data. Therefore, by executing the program from the time when the interrupt occurs after the interrupt returns, the CPU processing due to the interrupt occurrence can be avoided. It is possible to prevent rifts.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram showing an embodiment of an information processing apparatus of the present invention, and FIG. 2 is a schematic flowchart showing the operation of the present invention. 18-11...Register group 38-3m...Selector group 5...Interrupt processing unit

Claims (1)

[Claims] A plurality of register groups that hold data processed by the program during execution of the program, and an arbitrary register group selected from the plurality of registers and held in the arbitrary register. a plurality of selectors for outputting data; an interrupt determining means for determining an interrupt when an interrupt occurs during execution of the program; a first control means for prohibiting writing of a group of registers holding processed data; and when the interrupt determination means determines that the interrupt has returned, the first control means causes the data held in the write-inhibited registers to be disabled; the second output by the selector;
An information processing device comprising: a control means;