JPH02309681A - Semiconductor nonvolatile memory - Google Patents

Abstract

PURPOSE:To make possible a writing by a supply voltage and to prevent a soft write at the time of readout by a method wherein an injection of hot electrons and the writing are performed between second and third channel regions and a drain region is formed into a thin drain region. CONSTITUTION:A channel region is constituted of first and third channel regions, which are respectively controlled by floating gates 9, and a second channel region which is controlled by a selective gate electrode 13. Moreover, a tunnel insulating film (a drain region) 8 is formed between a drain region 3 and the electrode 9, hot electrons are injected between the second and third channel regions to perform a writing and an erase is performed taking out the electrons form the electrode 9 to the region 3 by applying a high voltage to the drain region. Thereby, a memory is actuated by a supply voltage only and moreover, a soft write at the time of readout can be prevented.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor nonvolatile memory used in electronic equipment such as a combinator.

[Summary of the invention]

In a floating gate type electrically erasable semiconductor nonvolatile memory, the present invention performs channel hot electron injection at the channel surface remote from the junction between the substrate and the drain region, and also forms a tunnel insulating film on the drain region. Furthermore, by forming the drain region with a thin concentration, the drain region can be used as an erase terminal, thereby making possible an electrically erasable semiconductor nonvolatile memory using a single power supply.

[Conventional technology]

Conventionally, as shown in FIG.
An N-type source region 2 and a train region 3 are formed at a distance from each other on the surface of the substrate 1, and a tunnel insulating film is further formed on the channel region, which is the surface of the substrate 1, between the source region 2 and the drain region 3. Floating game through 8)'? tlE
An electrically erasable semiconductor nonvolatile memory in which an i9 and a control gate electrode 11 are formed is known. For example, V,N,KyneLt etal “An II
n-5yste Reprogrammable
32k x8 CMO5Flash Memory”
IEEE Journal of 5olid-3
tateCircuits, vol, 23. No.5.
1988 ppH57-1163.

[Problem to be solved by the invention]

However, in conventional semiconductor non-volatile memory, during writing, it is difficult to inject hot electrons at the power supply voltage due to large variations in channel length, and during erasing, a high voltage is applied to the source region 2. There is a drawback that the memory is always in an ON state after electrons are removed from the floating gate electrode 9. Also, in reading,
When the channel length is shortened, there is also the drawback that soft writes occur during readout.

Therefore, in order to solve these conventional drawbacks, the present invention enables stable writing and erasing with a power supply voltage, and furthermore, after erasing, unselected memories can be turned off.
The object of the present invention is to obtain a semiconductor non-volatile memory that can perform the following steps and is free from soft writing even during reading.

[Means to solve the problem]

In order to solve the above problems, the present invention configures a channel region with first and second channel regions controlled by a floating gate electrode, and a second channel region controlled by a selection gate electrode, and By performing hot electron injection writing between the second channel region and the third channel region, writing at a voltage of 7 JrA was made possible. Also, by making the drain region thin, soft writing during reading was prevented.

〔Example〕

Embodiments of the present invention will be described below based on the drawings.

FIG. 1 is a sectional view of a first embodiment of a semiconductor nonvolatile memory according to the present invention. On the surface of a P-type silicon substrate 1 (which may, of course, be a P-type silicon thin film), an N'-type source region 2 and drain region 3 are provided at a distance from each other. Source region 2 and drain region 3
The channel region, which is the surface of the silicon substrate 1 between the
A first channel region, a second channel region, and a third channel region are electrically connected in series in this order from the source region 2 side. Above the first channel region,
A floating gate electrode 9 is formed with the first gate insulating film 5 interposed therebetween. Furthermore, a selection gate electrode 13 is formed on the second channel region with a second gate insulating film 6 interposed therebetween.

Furthermore, a floating gate Ti FF 19 is provided on the third channel region with a third gate insulating film 7 interposed therebetween. Furthermore, a control gate 1 frame 11 is provided on the floating gate electrode 9 with a control gate insulating film 10 interposed therebetween.

The control gate electrode 11 is strongly capacitively coupled to the floating gate electrode 9, and by applying a voltage to the control gate electrode 11, it is possible to control the potential of the floating gate electrode 9. Furthermore, a tunnel insulating film through which a tunnel current flows is formed in a part of the insulating film between the drain region 3 and the floating gate electrode 9. Further, a lightly doped N-type drain region 4 is formed to surround the drain region 3 . To make the memory small, N-type source region 2 and drain region 3 . Further, the N-drain region 4 is formed in a self-aligned manner with respect to the floating gate Ti pole 9. In addition, the floating gate electrode 9 and the control gate electrode 11
In order to reduce the variation in capacitive coupling between them,
It is better to process the floating gate electrode 9 using the control gate electrode 11 as a mask. Further, as the tunnel insulating film, a silicon dioxide film of 80 to 120 people is suitable in terms of retention characteristics and programming voltage optimization.

First, the memory reading method of the present invention will be explained. i! [For the desired memory, apply a voltage (generally the power supply voltage) higher than the dark value voltage of the second channel region to the selection gate electrode 13, and apply a constant voltage (between 0 and the power supply voltage) to the control gate electrode 11. It can be read by monitoring the channel conductance between the source region 2 and the drain region 3 under the condition where a value of .

For example, when electrons are written into the floating gate electrode 9, the channel conductance is low; on the other hand, when electrons are extracted from the floating gate electrode 9 and erased, the channel conductance becomes large. This is because the first channel region and the third channel 2U region, which are controlled by the potential of the floating gate electrode 9, are electrically arranged in series in the channel region between the source region 2 and the drain region 3. . In non-selected memories, by turning off the second channel region under the selection gate electrode 13,
No unnecessary current flows. That is, unselected memory is always O.
It is an FF, and information is read out from the selected memory by changing the channel conductance depending on the potential of the floating gate electrode 9. Furthermore, since the drain region 3 is surrounded by the thin drain region 4, the hot electron generation rate during reading is extremely low. Therefore, since there are few soft writes during reading, the voltage applied to the drain region 3 during reading (read drain region voltage) can be increased to the voltage a.

Next, a method for recessing a memory according to the present invention will be explained.

The source region 2 is set to the same potential as the substrate 1, and a power supply voltage is applied to the drain region 3. Furthermore, a high voltage of about 10 V is applied to the control gate electrode 11.

A voltage is applied to the selection gate electrode 13 so that the second channel region is weakly inverted. By applying a high voltage to the control gate electrode 11, the first channel region and the third channel region are strongly inverted, and as a result, the surface potential of the first channel region becomes the same potential as the source region 2. ,
The potential of the third channel region is the same potential as the power supply voltage, which is the potential of the drain 3. Since the second channel region is weakly inverted compared to the first and third channel regions, the power supply voltage applied to the drain region 3 is applied to the intersection of the second channel region and the third channel region. Add to the pinch-off point that forms. Therefore, a large surface potential difference is formed at the intersection of the second and third channel regions, and many hot electrons are generated. Some of the generated hot electrons are absorbed by the electric field of the third gate insulating film. In the memory of the present invention, even if the channel length of the second channel region is 1 μm or more, writing can be performed with a drain voltage below the power supply voltage. FIG. 3 is a diagram showing the L dependence of the minimum drain program voltage Vdpmin required for writing.Even when the channel length is longer than 1-,
Writing can be performed with a low drain voltage. Therefore, even if the channel length has a large variation of ±0.2-0.2 mm due to processing, four-way cutting can be performed at a voltage below the power supply voltage. On the other hand, in conventional memories, the L dependence is large as shown by curve a in FIG. 3, and writing at a voltage below the power supply voltage is practically difficult.

In the memory of the present invention, the L dependence is small and the drain write voltage is low, as shown in the curve, because the electric field of the gate insulating film in the third channel region, which is the region where hot electrons are injected, easily This is because the direction is such that it can be injected.

Further, the generation rate of electrons is also very high because they are formed by pinch-off between the second channel region and the third channel region. 2nd channel dilute acid and 3rd channel
The larger the difference in the strength of inversion in the channel region, the higher the occurrence rate. In other words, the selection gate electrode 13 has a
A voltage near the dark value voltage of the channel region is applied to the control gate electrode 11, and a voltage at which the first and third channel regions are sufficiently inverted is applied to the control gate electrode 11. The fact that the injection region is farther away than the drain region 3 is also the reason why writing can be performed with a low drain voltage.

Next, a memory erasing method according to the present invention will be explained. A high voltage of about 15 V is applied to the drain region 3 with the control gate electrode 11 and the selection gate electrode 13 set to Ov. By applying OV to the control gate electrode 11, the potential of the floating gate electrode 9 is also reduced to about Ov. Therefore, the tunnel insulating film 8 between the floating gate electrode 9 and the drain region 3
A high voltage of approximately 15 V is applied to the gate electrode 2, and electrons due to a tunnel current flow from the floating gate electrode 9 to the drain region 3. By surrounding the drain region 3 with the N-type drain region 4, junction leakage between the surface of the substrate 1 and the drain region 3 can be reduced. Inside the chip that integrates memory,
By providing a booster circuit and generating a high voltage of about 15V from the power supply voltage, a single 1Iti memory chip can be made possible. By providing the N-type drain region 4, junction leakage is reduced and a single power supply memory is made possible. In the case of conventional memory, the hot electron generation region is near the drain region 3, so N-
Providing the type drain region 4 reduces the hot electron generation rate and increases the programmed drain voltage. Therefore, in conventional memories, it was not possible to provide an N-type drain region 4.

In the memory of the present invention, the hot electron generation region is
Since it is between the second channel region and the third channel region, an N-type drain region 4 can be provided.

That is, the drain region 3 can be used as an erase terminal. It goes without saying that, like the conventional memory shown in FIG. 2, by providing an N-type source region around the source region 2, the source region 2 can be used as an erase terminal. In memory of invention,
After erasing, the first channel region and the third channel region are O
Even in the N state, unselected memories can always be turned off by turning off the second channel region under the selection gate electrode 13.

FIG. 4 is a sectional view of a semiconductor nonvolatile memory according to a second embodiment of the present invention. A selection gate electrode 13 is formed in the lower layer, and a floating gate electrode 9 and a control gate electrode 11 are sequentially formed thereon. Reading, writing, and erasing methods can be performed in the same manner as in the first embodiment. In the case of the memory in Figure 4,
The channel length of the second channel region under the selection gate electrode 13 can be controlled by the selection gate electrode width. In the memory of the first embodiment shown in FIG. 1, the channel length of the second channel region is controlled by the spacing between floating gate electrodes 9. In the memories of the first and second embodiments, the channel length of the second channel region is also accurately controlled. Further, in the memory shown in FIG. 4, the capacitive coupling between the control gate electrode 11 and the floating gate electrode 9 can be increased.

〔Effect of the invention〕

As explained above, the present invention comprises a channel region consisting of first and third channel regions controlled by a floating gate electrode, a second channel region controlled by a selection gate electrode, and a drain region A tunnel insulating film is formed between the gate electrode and the floating gate electrode, and writing is performed by injecting hot electrons between the second channel region and the third channel region, and by applying a high voltage to the drain region. , by performing erasing that extracts electrons from the floating gate electrode to the drain region, only the power supply voltage (for example, 5V
This has the effect of facilitating the creation of a semiconductor nonvolatile memory that operates as a single device, has no leakage current in non-selected memories, and prevents soft writes during reading.

[Brief explanation of drawings]

FIG. 1 shows a first diagram of a semiconductor nonvolatile memory according to the present invention.
2 is a cross-sectional view of a conventional semiconductor non-volatile memory; FIG. 3 is a diagram showing the dependence of the lowest drain programming voltage Vdpmin on the second channel region length of the semiconductor non-volatile memory of the present invention; FIG. FIG. 4 is a sectional view of a second embodiment of the semiconductor nonvolatile memory of the present invention. l... Semiconductor substrate 2... Source region 3... Drain region 8... Tunnel insulating film 9... Floating gate electrode 11... Control gate electrode 13... Selection gate electrode and above Applicant Seiko Denshi Kogyo Co., Ltd. Representative Patent Attorney Keisuke Hayashi Fig. 1 Fig. 2 L (/Jm) L viability diagram of the pressure V□pm・n for the train 10 grams Fig. 3 Cow s/I Figure 4: The 111th Sanskrit is the main memory.

Claims (1)

[Claims] a source region and a drain region of a second conductivity type provided at a distance from each other on the surface of the semiconductor substrate of the first conductivity type; a channel region on the surface of the semiconductor substrate between the source region and the drain region; a first channel region that is part of the channel region and electrically connected to the source region; a third channel region that is part of the channel region and electrically connected to the drain region; A part of a channel region, and provided over a second channel region between the first channel region and the third channel region, and a first gate insulating film over the first channel region. further comprising: a floating gate electrode provided on the third channel region via a third gate insulating film; and a control gate electrode provided on the floating gate electrode via a control gate insulating film. , a selection gate electrode provided on the second channel region via a second gate insulating film, and a lightly doped drain region provided surrounding the drain region; A semiconductor nonvolatile memory consisting of a tunnel insulating film provided between