JPH02307135A - Monitoring method for instruction executing action - Google Patents

Abstract

PURPOSE:To decide an abnormal action in real time by displaying a mode corresponding the logical state of the input/output signal of a microprocessor at the coordinate position of a display in accordance with the output address value of the microprocessor or the I/O address value. CONSTITUTION:An address bus of a frame memory 6 is connected to an address bus of a microprocessor 2 containing a memory 1. At the same time, a data input bus of the memory 6 is connected to a read/write terminal of the processor 2. Then a data output bus and a control terminal of the memory 6 are connected to a display 7 and a control part 8 respectively. In such a constitution, an instruction executing action monitor device 9 is attained. Then a character, a symbol or a mark of a prescribed mode corresponding to the logical state of the input/output signal of the microprocessor 2 is displayed at the coordinate position of the display 7 in accordance with the output address value of the processor 2 or the I/O address value. Thus it is possible to decide in a short time whether a due action is normal or not.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an instruction execution operation monitoring method for detecting abnormal operation of a microprocessor.

(Prior Art) Microprocessors perform various processes according to programs, so it is necessary to monitor the instruction execution operation of the created program and check whether it operates normally. I was debugging the program.

Conventionally, when monitoring the instruction execution operation of a microprocessor 2 equipped with a memory 1, as shown in FIG. An in-circuit emulator (ICE) 5 consisting of a monitor 4 and a monitor 4 for displaying the information was connected.

If you connect ICE5 like this, microprocessor 3
The monitor 4 can stop its operation at each step time of the program, and at that time the input/output logic state values of the microprocessor 3 can be displayed.
It can be confirmed whether the microprocessor 2 is operating normally from the context of a series of input/output logic status values displayed by the CE 5.

However, in this instruction execution operation monitoring method using ICE, it is necessary to stop the operation of the microprocessor at each step time of the program, so it takes time to check whether the operation is normal or not. Since the task of reading input/output logic state values and recognizing their operating states is complicated, it has been extremely difficult to debug large-capacity programs.

(Object of the Invention) The present invention has been made in order to solve the problems of the above-mentioned instruction execution operation monitoring method. An object of the present invention is to provide a method for monitoring an instruction execution operation that can determine whether the operation is normal or not.

(Summary of the Invention) In order to achieve the above object, the present invention has the following configuration.

That is, the microprocessor's output address value or I/O
It is arranged to display a predetermined fi-like character, symbol, mark, etc. corresponding to the logical state of the input/output signal of the microprocessor at the coordinate position of the display section corresponding to the address value.

(Example) Hereinafter, the present invention will be described in detail based on an example shown in the drawings.

FIG. 1 is a block diagram showing an embodiment of an instruction execution operation monitoring device according to the present invention.

In the figure, 6 is a frame memory, which connects its address bus to the address bus of the microprocessor 2 equipped with the memory 1, and also connects the data input bus of the frame memory 6 to the read/write terminal of the microprocessor 2. A data output bus and a control terminal of the frame memory 6 are connected to a display 7 and a control unit 8, respectively, thereby forming an instruction execution operation monitoring device 9. Here, the addresses of the frame memory are sequentially made to correspond to coordinate positions in the horizontal direction from the top left of the display screen of the display 7 in order from address O to the final address.

The instruction execution operation monitoring device configured as described above operates as follows.

That is, the frame memory 6 is reset and the display 7
If the microprocessor 2 is activated after displaying white on the entire screen, the frame memory 6 will be activated according to the program.
inputs an address signal and a read/write signal, and if the read/write signal is in a data read logic state or a data write logic state, a black dot is displayed at a predetermined coordinate position on the display 7 according to the address signal. .

Here, if the normal operation is for the microprocessor to sequentially read or write data from address 0 to the last address in the memory, then the screen display of the above-mentioned instruction execution operation monitoring device should be monitored. For example, the display will display black dots in sequence horizontally from the top left of the screen, and the color of the entire screen will eventually change from white to black, so if you want to display black dots randomly on the screen of the display, Since the microprocessor randomly reads or writes data to memory addresses, it can be determined that the /O-gram is out of control. Also, if the display color stops changing from white to black at a coordinate position in the middle of the display screen, and the color of the entire screen does not change from white to black, the microprocessor registers the stopped change in the memory. It can be determined that an eternal loop is occurring between the address corresponding to the coordinate position and the O address.

Therefore, according to the above-mentioned instruction execution operation monitoring device, since it is possible to monitor the microprocessor in real time without stopping the operation of the microprocessor, the operation of the microprocessor can be monitored in a short time from the display state of the display screen. By monitoring the display, it is possible to visually determine whether the microprocessor is normal or not based on the display pattern.

Furthermore, in the present invention, part or all of the storage contents of the frame memory 6 may be reset by the control unit 8 at predetermined intervals. Can be closely monitored.

In the above-described embodiment, a black dot is displayed at a predetermined coordinate position on the display according to the logic state of the microprocessor read/write signal, but the present invention is not limited to this; Characters, symbols, marks, etc. that correspond in advance to logical states may be displayed, or aspects such as brightness, hue, or a combination thereof may be changed in accordance with the logical state of input/output signals of the microprocessor.

In this embodiment, the positional relationship between the address value of the frame memory and the coordinate position of the display screen is not limited to that described above, and
The /O address value may correspond to a predetermined coordinate position on the display screen.

Furthermore, it is obvious that various display devices may be used, not just a display, to display a mode corresponding to the logical state of an input/output signal of a microprocessor.

(Effects of the Invention) As explained above, the present invention provides a mode corresponding to the logical state of the input/output signal of the microprocessor at the coordinate position of the display section according to the output address value or I/O address value of the microprocessor. The purpose of the present invention is to develop an instruction execution operation monitoring method that can visually debug a program so that the microprocessor operates normally in a short period of time because abnormal operation can be determined in real time based on the display state. It is effective in providing

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of an instruction execution operation monitoring apparatus according to the present invention, and FIG. 2 is a block diagram showing a conventional instruction execution operation monitoring apparatus. 1...Microprocessor, 2...Memory. 6...Frame memory, 7...Display. 8...control unit. Patent applicant: Toyo Tsushinki Co., Ltd. Figure 1 Figure 2

Claims (2)

[Claims] (1) In a device equipped with a display section for displaying the execution status of a program, the microprocessor is placed at a predetermined coordinate position on the display section according to the output address value or I/O address value of the microprocessor. A method for monitoring instruction execution operations, characterized in that characters, symbols, marks, etc. that correspond in advance to the logical states of input/output signals of the microprocessor are displayed or their appearance is changed according to the logical states of the input/output signals of the microprocessor. . (2) In a device equipped with a display section for displaying the execution status of a program, a coordinate position of the display section determined in advance according to the output address value of the microprocessor is displayed relative to the memory address of the address value. An instruction execution operation monitor characterized in that characters, symbols, marks, etc. that correspond in advance to the access state are displayed or the appearance thereof is changed according to the access state to the memory address of the address value of the microprocessor. Method.