JPH02306218A - Matrix display device - Google Patents

Abstract

PURPOSE:To accomplish color display in full screen or in a state where there are few non-displayed parts even for a signal having middle number of picture elements by constituting one picture element of 3n image elements which are the monochrome display units of R, G and B and changing the number and the combination of the image elements which constitute one picture element. CONSTITUTION:In a matrix panel consisting of MXN image elements, one picture element is constituted of 3n image elements which are the monochrome display units of R, G and B. Namely, one picture element E1 consisting of 12 image elements =(horizontal 4 image elements X vertical 3 image elements), one picture element E2 consisting of 6 image elements=(horizontal 3 image elements X vertical 2 image elements) and one picture element E3 consisting of 3 image elements arranged in a hook shape on the panel respectively are combined. A signal X1 having information on the picture elements of (M/3)X(N/4), a signal X2 having information on the picture elements of (M/2)X(N/3) and a signal X3 having information of picture elements of (M/1.5)X(N/2) are outputted from a computer so as to perform the display on the panel by writing at addresses on a frame memory corresponding to the respective image elements on the panel which constitute the respective picture elements E1, E2 and E3.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a matrix display device for display of a personal computer, etc., and particularly relates to a matrix display device for a display of a personal computer, etc. The present invention relates to a matrix display device capable of displaying signals having different numbers of signals on the same panel.

[Conventional technology]

Conventionally, as a method for selectively displaying a plurality of signals having different numbers of picture elements using the same matrix display device, for example, as described in Japanese Patent Application Laid-Open No. 61-231526, the number of picture elements can be changed by changing the driving method of the panel. The ratio is 1:
One example is one that can selectively display the Ig number of Class 2, which is 4.

[Problem to be solved by the invention]

In the above-mentioned conventional technology, only two types of signals with a pixel number ratio of 1:4 can be displayed on the same panel, and no consideration is given to signals with a pixel number between the two types of signals. There is a problem with this signal that part of the information is missing or there are too many pixels left over, that is, there are blank areas and the information can only be displayed in a state where it cannot be displayed on the entire screen.

An object of the present invention is to provide a matrix display device capable of displaying a signal having an intermediate number of picture elements in color without filling the screen or lacking the amount of information and with a small number of non-display areas. There is a particular thing.

[Means to solve the problem]

The above purpose is to
One picture element is composed of 3n pixels, which are monochrome display units. This is achieved by providing means for changing the number and combination of pixels constituting one picture element so that the number of picture elements that can be displayed on the panel is greater than or equal to the number of picture elements of the input signal and is the minimum.

[Effect]

For an input signal having a certain number of picture elements, the number and combination of pixels constituting one picture element of a matrix display device are changed so that the number of picture elements is greater than or equal to the number of picture elements of the input signal and the number of displayable picture elements is the minimum. In this way, by changing the number of picture elements that can be displayed on the panel, signals having different numbers of picture elements can be displayed in color without missing information and with fewer non-displayed areas.

〔Example〕

Figure g1 is a block diagram showing a first embodiment of the present invention. 10 to 12 are computers, '100 is a data bus,
300 is DMA (direct memory access device), 2
01 is a frame memory with the same number of addresses as the number of pixels of the matrix panel, 2o2 is a 07 person converter, 204
Reference numeral 30 denotes a blanking address generation circuit that controls the cutting operation from the frame memory, and 30 a matrix display device.

FIGS. 2 and 3 are diagrams of the operating principles of the system shown in FIG. 1. In FIG. 2, 1 is a matrix panel consisting of MXN pixels, x1 to x3 are signals output from computers 10 to 12, xl is a signal with V3XN/4 picture element information, and x2 is ? A signal having pixel information of 12×N/3, x3 is a signal having pixel information of M/15XN/2, and El, E2, and E3 are each Xi.

In order to display the x2 and x3 signals in color on the matrix panel 1, it has a one-pixel configuration including the same number of pixels of each of the three primary colors R, G, and B. In FIG. 3, 5 is one address of the frame memory. The embodiment shown in FIG. 1 will be described below with reference to FIGS. 2 and 3.

The above video signals xi, x2. x3) In order to display the IJ panel 1 without excess or deficiency, each signal xi,
x2. x3 pixel information, on the panel, as shown in the circle in Figure 2, each pixel E1 consists of 4 horizontal pixels x 3 vertical pixels, and 6 pixels (3 horizontal pixels x 2 vertical pixels). 1 consisting of pixels consisting of 1 picture element E2, 1 consisting of 3 pixels arranged in a key shape
It should be expressed as picture element E3. However, to make one picture element E3 symmetrical, it should be composed of 2 horizontal pixels x 15 vertical pixels, but 03 pixels cannot be displayed on a matrix panel, and in order to represent white on a color display, , R in one picture element
, G, and B pixels in the same number. Also, if each picture element is made up of twice as many pixels, one picture element E3 will also be symmetrical, but
This is disadvantageous in terms of panel yield and the number of displayable pixels. Based on the above, in order to make one picture element E3 as small as possible, it is composed of three pixels arranged in a key shape.

In order to perform the above conversion operation, as shown in FIG. The data is written to addresses on the frame memory corresponding to each pixel of the panel constituting E3. FIG. 3 shows the write operation to the frame memory at this time. l picture elements on the frame memory are represented by a matrix,
Input signals assigned the same row and column numbers are written to each address constituting one picture element. For example, in the case of (1),
Each pixel information of a signal with a number of pixels of M/3 x V4 dots is written to 12 addresses in 3 rows and 4 columns, and 1
One picture element E1 is formed. As a result, M/38N74 pieces of picture element information can be associated with MXN addresses without excess or deficiency. The same applies to cases (2) and (3). In this way, the signals converted by DMA and written into the frame memory are displayed on the matrix display device 30.
displayed by.

FIG. 4 is a block diagram showing the structure of a liquid crystal module using a TPT liquid crystal panel as a specific example of the IJ display device 30. FIG. 4 is a TPT liquid crystal panel, 2 is a horizontal scanning circuit, 3 is a vertical scanning circuit, 4G is a gate bus, 4D is a drain bus, and 41 is a TFT.

42 is a liquid crystal cell. The TPT liquid crystal panel 4 has pixels consisting of TFTs 41 and liquid crystal cells 42 arranged in a matrix, a drain bus 4D that connects the drain terminals of TPTs for one column, and gate terminals of TPTs for one row. The color filter arrangement is made up of a gate bus 4G and a color filter arrangement in which RlG and B three primary colors are arranged diagonally in a straight line.

The signals stored in the frame memory are read out line by line from the top left by the read address generation circuit 204.
After being D/A converted, it is manually input to the horizontal scanning circuit 2.

The horizontal scanning circuit 2 internally sequentially stores video signals for one vehicle in a -horizontal scanning period, and then outputs video signals for one vehicle at a time to the drain bus 4D.

Then, when a certain gate bus 4G is selected by the vertical scanning circuit 3 while the video signal is being output to the drain bus 4D, all the TFTs 41 in that row are turned on, and the liquid crystal cell 42 is not soaked. It is done. The horizontal scanning circuit 2 repeats the above operation, and the vertical scanning circuit 3 writes video signals to all pixels of the TPT liquid crystal panel 4 by sequentially selecting the gate buses 4G one by one from top to bottom.
It becomes possible to compose a picture.

FIG. 5 is a configuration diagram showing a specific example of the horizontal scanning circuit 2, and FIG.
The figure is a waveform diagram showing the operating waveforms.

The horizontal scanning circuit 2 includes a shift register 21, four level shifters, a sample hold (S/H) circuit, and a buffer amplifier U.

A start pulse STH and a shift clock CPH are input to the shift register 21, and the start pulse STH is sequentially delayed and outputted to its output SH in synchronization with the shift clock CPH. The output SR of this shift register 21
The voltage is converted into a voltage sufficient to operate the S/H circuit at the next stage through the level shifter 22, and then applied to the S/H circuit. The S/H circuit is a collection of the same number of sample and hold units as the drain bus, and includes a level shifter 22.
The video signals corresponding to the display positions are sequentially sampled and held by the output of the . The S/H circuit circuit power is input as is to the output buffer, and after sampling is completed for all pixels in the - row, the output enable signal OE is input.
At the timing, the video signals for - rows are simultaneously output onto the drain bus 4D.

FIG. 7 is a configuration diagram showing a specific example of a vertical scanning circuit;
The figure is a waveform diagram showing the operating waveforms.

The vertical scanning circuit 3 includes a shift register 31, a level shifter 32, and an output buffer amplifier.

The shift register 31 receives a start pulse STV and a shift clock CPv. A start pulse STY is sequentially delayed and outputted to the output Sv in synchronization with the shift clock CPv. The output Sv of this shift register 31 is converted by a level shifter 32 into a voltage sufficient for driving the next stage, and then sequentially outputted via an output buffer.

As described above, according to this embodiment, each video signal x1 output from the personal computers 10 to 12 is stored in the frame memory 201.
~x3 1 pixel, each 4 pixels horizontally x 3 pixels vertically, total 1
They are converted into one picture element E1 consisting of two pixels, one picture element E2 consisting of six pixels (3 horizontal pixels x two vertical pixels), and one picture index E3 consisting of three pixels arranged in a key shape, and then input to the panel. As a result, in a matrix panel with MXN pixels, valley W3 x 1'M4 pixels, outer 4 x V3 pixels, M/15 x
Three types of signals having different numbers of y2 picture elements can be displayed in color without excess or deficiency.

FIG. 9 is a block diagram of a system according to a second embodiment of the present invention. 101 is a selector for selecting an input signal; 2
02 is a D/A conversion circuit, 203 is a storage address generation circuit, 205 is a line memory, 206 is a control circuit, 207
is an S/P conversion circuit (serial/parallel conversion circuit). A signal selected by the user by switching the selector 101 is subjected to S/P conversion, and by switching the switch SWI by the control circuit 206, data for one row is sequentially convoluted into the three line memories 205. However, input signals Xi,
In case 2, only two line memories are used and one is left floating. A horizontal frequency ff, a vertical frequency fr1, and a dot clock fD are applied to the control circuit 206 through the selector 101. fB/fH is the number of horizontal picture elements, fI
Since I/lr is the number of vertical pixels, the control circuit 206 automatically determines how many pixels the input signal is and switches the switch. In addition, the user can freely control the control circuit 20.
It is also possible to determine six switching modes.

At the same time, the control circuit 206 also switches the distribution circuit 209,
Give a write-in address to the line memory to be written to. In the same way as in the case of filling in the line, the control circuit 206 switches the switch SW2 to continue writing from the line memory in which writing has been completed.

At this time, the control circuit 206 also controls the distribution circuit 209
is switched, a read address is given to the line memory that performs bladder evacuation, and the read order is controlled. As described above, the second embodiment is a system that performs the conversion shown in FIG. 2 by switching the input/output switches SWI, SW2 and the distribution circuit 209 by the control circuit 206.

FIG. 10 shows a timing chart showing the input/output relationship and the operation of the line memory 205 due to switch switching. (a), (bl, and (c) are the input signals xi, respectively).

x2. Compatible with x3. The operation will be explained below using (a) as an example. First, input 1 has one horizontal scanning period (I
H) is written to line memory A. Next, the switch is changed and the human power 2 is stored in the line memory C. At the same time, input 1 is output from line memory A three times during IH. That is, the same data is written in three rows of the matrix panel during IH. By repeating the above operations alternately, one line of data can be displayed on three lines of the panel6. The same applies to (b) and (c).

However, in (C), where the read operations overlap in the two line memories, the switches are changed and read is performed alternately in order to realize a key-shaped picture element.

Next, FIG. 11 is a memory map of the line memory, and each address is represented by a matrix. During a write operation, each search information of the input signal is R and G.

Divide into B and write in one column from the left. During a read operation, the data are read in the order of addresses given by the start address generation circuit 204. For example, when the input signal is x1, one pixel is represented by four pixels in the horizontal direction as shown in Figure 2, and because the color filter is arranged in a mosaic pattern diagonally downward to the right, (1
,1), (2,1), (3,1).

(1,1), (2,2), (3,2), (
1,2), (2,2)..., that is, (2)
The direction is shifted one row at a time, and the same column in the ■ direction is selected four times and shifted to the right.

Furthermore, the row address to be retrieved first is also shifted row by row. Almost the same operation is performed for other input signals.

As described above, in the system shown in FIG. 9, one pixel as shown in the circle in FIG. 2 can be configured by controlling the switches and the distribution circuit by the control circuit. Therefore,
According to this embodiment, by using a 3-line memory without using a field memory, a matrix panel having MXN pixels is provided with M/3 x N/4 pixels and M/2 x 1 pixels, respectively.
Three types of signals xl, x2, and x3 having different numbers of picture elements (3 picture elements, M/1B x K picture elements) can be displayed in color to fill the entire screen without excess or deficiency.

FIG. 12 is a block diagram of a system according to a third embodiment of the invention. 301 is a matrix display device, and 102 is a control circuit that controls the output of the drive circuit.

In this embodiment, by switching the driving method of the matrix display device 301 using the control circuit described above, 3m signals x1°x2. x3 is displayed in color.

FIG. 13 is a block diagram of a matrix display device 301 having means for switching the picture element configuration used in the third embodiment. 2 are horizontal scanning circuits, 3A is vertical scanning circuits, 4
A is a TPT liquid crystal panel. As in the first embodiment, R,
The color filter arrangement is such that the three primary colors G and B are arranged diagonally in a straight line downward to the right. Further, the drain bus 4D connects the drain terminals of the TPTs for one column as in the first embodiment, but as shown in the circle, the gate bus 4G connects the drain terminals of the TPTs for the horizontal to rows. There are rows in which the gate terminals of the - rows of TPTs are connected to the gate terminals of the TPTs, and rows in which the gate terminals of the TPTs in the - rows are alternately connected to the two gate buses. In order to realize a key-shaped one picture element E3, one out of three rows is selected by two gate buses 4G. Therefore, Gate Bus 4G is
It requires 4/3 times the number of vertical pixels.

FIG. 14(a) is a diagram showing the configuration of two horizontal scanning circuits. The shift matrix 5 is a circuit that changes the combination of input and output connections. In addition, the S/H circuit 26 is shown in FIG.
As shown in b), there are six sample and hold circuits 261 for one output, and the sample and hold circuits 261,
The same sampling clock is supplied to Q31, C), (to), (■), and (prompt).

FIG. 15 is a diagram showing the input/output relationship of the shift matrix 5. Modes (1) to (3) correspond to picture element configurations E1 to E3 in FIG. 2, respectively. For example, in the case of the human input signal x1, the output SHI of the shift register is outputted to the outputs M)11-MH4 of the shift matrix in mode (1). Hereinafter, SH2 is MH5 to MH8, SH3 is M
The same sunfling pulse is outputted in each of the four columns from H9 to MH12. With this tz, four consecutive horizontal rows of S/Hs are driven with the same sampling pulse. Similarly, mode (2) is S/3 columns each, and mode (3) is S/2 columns each.
H is driven by the same sampling pulse. Further, the above operation can be performed even in a horizontal scanning circuit without the shift matrix 25.
This can also be achieved by increasing the clock frequency.

FIG. 16(a) is a timing chart showing the operation of the S/H circuit in the case of picture element configuration E1, and FIG. 16(bl) is a timing chart showing the operation of the S/H circuit in case of picture element configuration E2 and E3 6 for picture element configurations E2 and E3.
Of the two sample and hold circuits, only four are used and the remaining two are left floating. The operation will be explained below with reference to FIG. 16(a). wi'iv write operation, R indicates read operation, and H indicates hold state.

First, during the first horizontal scanning period (IH), the sample and hold circuit Q31 (C) performs writing, and the next IH is divided into three equal parts and sequentially read out. When the sample and hold circuits (4), (B), and (C) are reading, the sample and hold circuits (■), ■, [
F] performs writing. Thereafter, the commit operation and read operation are repeated in order.

FIG. 17(a) shows a configuration diagram of the vertical scanning circuit 3A.

Similar to the two horizontal scanning circuits, a shift matrix is inserted between the shift register 31 and the level shifter 32.

FIG. 17(b) is a diagram showing the input/output relationship of the shift matrix. Modes (1) to (3) correspond to picture element configurations E1 to E3 in FIG. 2, respectively. The operation is almost the same as that of the shift matrix 5 of two horizontal scanning circuits, and by switching the mode by the control circuit 102, the number of vertical pixels can be controlled to have each picture element configuration E1 to E3.

As described above, according to this embodiment, the TFT liquid crystal panel 4A with irregularly arranged gate buses, two horizontal scanning circuits, and three vertical scanning circuits can form a matrix having MXN pixels without an interface using a memory or the like. 13 XV4 pixels each on panel, g/2 x V3 pixels, M/1.5
Three types of signals xi with different numbers of picture elements
x2. x3 can be displayed in full color on the screen without too much or too little. In addition, for signals with a number of picture elements between the above three types of signals, the display is performed in a mode in which the number of picture elements that can be displayed on the panel is similar to the number of picture elements of the signal and is the minimum, and furthermore, an image is displayed. In order to equalize the pixel surplus around the part,
By displaying an image in the center of the panel, it is possible to reduce the amount of non-displayed areas around the image.

〔Effect of the invention〕

As described above, according to the present invention, the number of picture elements that can be displayed on the matrix panel can be switched so that it does not become less than the number of picture elements of the input signal and becomes the minimum number.

Fill the screen with signals with different numbers of picture elements on the same panel.
Alternatively, a matrix display device that can display in color without missing information and with less non-display portions can be obtained.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the system of the first embodiment of the present invention, and FIGS. 2 and 3 are diagrams of the operating principle of FIG. 1, respectively.
Fig. 4 is a block diagram of a matrix display device, Fig. 5 is a block diagram of a horizontal scanning circuit, Fig. 6 is its operating waveform diagram, and Fig. 7 is a block diagram of a horizontal scanning circuit.
The figure is a configuration diagram of the vertical scanning circuit, and Figure 8 is its operating waveform diagram.
FIG. 9 is a block diagram showing the system of the second embodiment of the present invention, FIG. 10 is a timing chart of the line memory,
Figure 11 is an explanatory diagram of the line memory memory map;
13 is a block diagram showing a system according to a third embodiment of the present invention, FIG. 13 is a configuration diagram of the display device shown in FIG. 12, and FIG.
Figure (a) is a configuration diagram of two horizontal scanning circuits, and Figure 14 (bl
15 is a diagram showing the input/output relationship of the shift matrix 5, and FIG. 16(a), (bl is S
Timing chart showing the operation of the /H circuit, Fig. 17 (
al is a configuration diagram of the three vertical scanning circuits, and FIG. 17 (bl is a diagram of the input/output relationship of the shift matrix. ...Computer 300...DMA xi~x3...
- Input signal El-E3...Picture element configuration 1...Matrix panel 205...Line memory 206, 10
2... Control circuit 203... Fractional address generation circuit 204... Read address generation circuit 209... Distribution circuit 202... D/A converter 207... S/P converter 〒1 Figure （1） F A4283C48 5B
5B 6CH-Hault 4 people separate, side 11 figure (X) Helmet I2 figure 15 figure A Shovel 14 figure I15 figure Old figure of porridge - 7 also - 1 hill) - 1 person 1 hill

Claims (1)

[Claims] 1. A matrix having a matrix panel in which R (red), G (green), or B (blue) monochrome display pixels are arranged at each intersection of signal lines arranged in the horizontal and vertical directions. In the display device, depending on the number of picture elements constituting one screen of the video signal to be displayed, three picture elements adjacent to each other of the monochromatic display pixels are arranged.
Select n pieces (n is an integer) to form one picture element,
A matrix display device characterized in that a plurality of video signals having different numbers of picture elements per screen can be selectively displayed on the same matrix panel. 2. The matrix display device according to claim 1, wherein the matrix panel has nx pixels in the horizontal direction and ny pixels in the vertical direction, that is, (nx x ny) pixels,
The color filter arrangement is such that R, G, and B monochrome pixels are arranged in a mosaic pattern diagonally downward to the right, and the video signal to be displayed is (nx/4) x (ny/3), (n
x/3)×(ny/2), (nx/2)×(ny/1.
5), (nx/3) x (ny/4), (nx/2) x (
1. A matrix display device characterized in that a video signal having pixels of (ny/3) or (nx/1.5)×(ny/2) can be selectively displayed. 3. The matrix display device according to claim 1, wherein the R, G, or B monochrome display pixels are comprised of liquid crystal, plasma, or electroluminescence (EL) display elements. 4. The matrix display device according to claim 1, wherein the matrix panel has horizontal signal lines or vertical signal lines of a non-integer multiple of the number of pixels in the horizontal or vertical direction. Device. 5. Selecting an address for each pixel of a video signal output from a frame memory, a matrix display device, a read address generation circuit, and a computer as a video signal source so as to correspond to a pixel in the display device. a direct memory access device that writes to the frame memory; a D/A converter that converts a signal read from the frame memory into digital/analog according to an address generated by the read address generation circuit and outputs the converted signal to the matrix display device; A matrix display device comprising: 6. A plurality of line memories arranged in parallel, a matrix display device, a write address generation circuit, a read address generation circuit, and an image from a computer selected from among a plurality of computers as a video signal source. a serial/parallel converter that performs serial/parallel conversion on a signal and then writes into a corresponding one of the line memories according to an address generated from the write address generation circuit; a D/A converter that performs digital/analog conversion on a signal read out according to the address generated by the read address generation circuit and then outputs the converted signal to the matrix display device. .