JPH0230596B2 - - Google Patents

Info

Publication number
JPH0230596B2
JPH0230596B2 JP54122228A JP12222879A JPH0230596B2 JP H0230596 B2 JPH0230596 B2 JP H0230596B2 JP 54122228 A JP54122228 A JP 54122228A JP 12222879 A JP12222879 A JP 12222879A JP H0230596 B2 JPH0230596 B2 JP H0230596B2
Authority
JP
Japan
Prior art keywords
substrate
semiconductor
layer
metal layer
coating layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP54122228A
Other languages
Japanese (ja)
Other versions
JPS5646583A (en
Inventor
Noboru Masuda
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Murata Manufacturing Co Ltd
Original Assignee
Murata Manufacturing Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Murata Manufacturing Co Ltd filed Critical Murata Manufacturing Co Ltd
Priority to JP12222879A priority Critical patent/JPS5646583A/en
Publication of JPS5646583A publication Critical patent/JPS5646583A/en
Publication of JPH0230596B2 publication Critical patent/JPH0230596B2/ja
Granted legal-status Critical Current

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Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/818Bonding techniques
    • H01L2224/81801Soldering or alloying
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01049Indium [In]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/0105Tin [Sn]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01082Lead [Pb]

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Die Bonding (AREA)
  • Hall/Mr Elements (AREA)

Description

【発明の詳細な説明】 本発明はインジウムアンチモナイド半導体等を
用いた半導体装置に関する。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor device using an indium antimonide semiconductor or the like.

従来の半導体装置、例えば磁電変換装置は、例
えば特公昭45―40746号公報に記載されているよ
うに、ガラスやフエライトから成る薄い基板の上
に、エポキシ樹脂接着剤のような有機接着剤を使
用して研磨されたウエハを接着し、所定の形状に
エツチングして構成している。
Conventional semiconductor devices, such as magnetoelectric transducers, use an organic adhesive such as an epoxy resin adhesive on a thin substrate made of glass or ferrite, as described in Japanese Patent Publication No. 40746/1983. It is constructed by bonding polished wafers and etching them into a predetermined shape.

しかし、上述のように接着剤の層をウエハと基
板の間に介在すると、均一な厚さの接着層が得ら
れ難いことから、ウエハごとに或はウエハを分割
して成るペレツトごとに厚味が相違し、特性のそ
ろつた磁電変換装置を多量に生産することは困難
であつた。
However, when an adhesive layer is interposed between the wafer and the substrate as described above, it is difficult to obtain an adhesive layer with a uniform thickness. However, it has been difficult to mass produce magnetoelectric transducers with uniform characteristics.

また、このような従来の磁電変換装置は、雰囲
気の温度が高くなると、接着剤と半導体部材の熱
膨張係数が相違することから、基板上の磁電変換
素片が変形しピエゾ効果によるピエゾ電圧を発生
する。すなわち、高温の雰囲気中では不平衡電圧
の温度特性が悪化し、これは磁電変換装置の出力
特性を悪化する欠点を生じる。このことは微少レ
ベルの磁束密度変化を計測する場合に極めて障害
になるものであつた。
In addition, in such conventional magnetoelectric transducer devices, when the temperature of the atmosphere rises, the thermal expansion coefficients of the adhesive and the semiconductor material differ, so the magnetoelectric transducer element on the substrate deforms and the piezo voltage due to the piezo effect is reduced. Occur. That is, in a high-temperature atmosphere, the temperature characteristics of the unbalanced voltage deteriorate, which causes a drawback of deteriorating the output characteristics of the magnetoelectric transducer. This was an extremely hindrance when measuring minute level changes in magnetic flux density.

本発明は上述のような欠点を解決するためにな
されたもので、有機接着剤を使用しないで構成し
たバルク形の半導体装置を提供するものである。
The present invention was made to solve the above-mentioned drawbacks, and provides a bulk type semiconductor device constructed without using an organic adhesive.

以下本発明の一実施例を添付図面を参照して詳
細に説明する。
An embodiment of the present invention will be described in detail below with reference to the accompanying drawings.

第1図および第2図はホール装置を構成する場
合で、マンガンジンク(MnZn)系或はニツケル
ジンク(NiZn)系から成るフエライトまたは半
導体シリコンから作られた基板1の表面に、一酸
化シリコン(SiO)或は二酸化シリコン(SiO2
の絶縁被膜層2を形成し、或は金属間化合物半導
体の基板1では酸化膜や半絶縁層、例えばガリウ
ムヒ素では炭酸ガス拡散やクロム拡散を施した層
2を形成し、基板1の4つの角部分には被膜層2
の上に相互に分離7された金属層3,4,5,6
を形成する。この金属層3,4,5,6は、使用
される半導体例えばインジウムアンチモナイド
(InSb)とのオーム性や融点を考慮して、インジ
ウム(In)、スズ(Sn)、ナマリ(pb)等、半導
体より融点の低い金属が選ばれる。金属層3,
4,5,6は、其れ其れ四辺形の表面を有する基
板1の各角部分を占め四辺形状の形状であるが、
基板1の中心部分に位置する角部分は基板1の対
角線と平行に形成されている。
Figures 1 and 2 show the case of constructing a Hall device, in which silicon monoxide (SiO ) or silicon dioxide (SiO 2 )
In the case of the substrate 1 of an intermetallic compound semiconductor, an oxide film or a semi-insulating layer is formed, for example, in the case of gallium arsenide, a layer 2 with carbon dioxide gas diffusion or chromium diffusion is formed. Coating layer 2 on the corners
metal layers 3, 4, 5, 6 separated from each other 7 on top of the
form. These metal layers 3, 4, 5, and 6 are made of indium (In), tin (Sn), sulfur (pb), etc. in consideration of the ohmic properties and melting points of the semiconductor used, such as indium antimonide (InSb). , a metal with a lower melting point than the semiconductor is selected. metal layer 3,
4, 5, and 6 each occupy a corner portion of the substrate 1 having a quadrilateral surface, and have a quadrilateral shape.
A corner portion located at the center of the substrate 1 is formed parallel to a diagonal line of the substrate 1.

金属層3,4,5,6の上には、これらを電極
とする半導体プレート8が装着されている。半導
体プレート8は、InSbのインゴツトを0.3〜1.0mm
程度の厚さに切断し、これを研磨して作つたウエ
ハを所定形状、例えばホール素子の場合には十字
状に形成され、厚さは50〜100μmとなつている。
即ち、プレート8は、感磁部9と入力電極部1
0,11と出力電極部12,13を備え、入力電
極部10,11が金属層3,5と接着され、また
出力電極部12,13が金属層4,6と接着され
ている。これら電極部10,11,12,13と
金属層3,4,5,6との接着は、金属層の熔融
によつて行なわれる。
A semiconductor plate 8 is mounted on the metal layers 3, 4, 5, 6 using these as electrodes. The semiconductor plate 8 is made of InSb ingot with a thickness of 0.3 to 1.0 mm.
The wafer is cut into a certain thickness and polished to form a predetermined shape, for example, a cross shape in the case of a Hall element, and the thickness is 50 to 100 μm.
That is, the plate 8 has a magnetic sensing part 9 and an input electrode part 1.
0 and 11 and output electrode sections 12 and 13, the input electrode sections 10 and 11 are bonded to the metal layers 3 and 5, and the output electrode sections 12 and 13 are bonded to the metal layers 4 and 6. The electrode parts 10, 11, 12, 13 and the metal layers 3, 4, 5, 6 are bonded together by melting the metal layers.

上述の構成では、半導体プレート8の感磁部9
と絶縁被膜層2の間に空隙14が形成されている
が、プレート8の厚さが50〜100μm程度のときに
は、このままでもプレート8の割れや応力歪はさ
ほど考慮する必要はないが、適切な樹脂、例えば
ポリエステル系樹脂のように耐熱性が優れ粘度の
低い熱硬化性樹脂を真空含浸法で充填すれば信頼
性が増大する。
In the above configuration, the magnetically sensitive portion 9 of the semiconductor plate 8
A gap 14 is formed between the plate 8 and the insulating coating layer 2, but when the thickness of the plate 8 is about 50 to 100 μm, there is no need to take into account cracking or stress distortion of the plate 8 as it is. Reliability will increase if a resin, for example a thermosetting resin with excellent heat resistance and low viscosity such as a polyester resin, is filled by vacuum impregnation.

しかし、半導体プレート8が、5〜10μm程度
と薄い場合には、第3図に示すように、空隙14
に相当する部分に、第2の絶縁被膜層15が形成
する。この被膜層15は、金属層3,4,5,6
とほぼ同じか或は若干薄い厚さにする。
However, if the semiconductor plate 8 is as thin as about 5 to 10 μm, as shown in FIG.
A second insulating coating layer 15 is formed in a portion corresponding to . This coating layer 15 includes metal layers 3, 4, 5, 6.
The thickness should be approximately the same or slightly thinner.

また、他の実施例としては、第4図に示すよう
に、基板1を半導体シリコン基板に特定し、基板
1の表面に上述の空隙14に対応して突部16を
形成し、この基板の上に絶縁被膜層2を形成す
る。金属層3,4,5,6は突部16の部分を除
いて上述同様に形成する。
Further, as another embodiment, as shown in FIG. 4, the substrate 1 is specified as a semiconductor silicon substrate, and a protrusion 16 is formed on the surface of the substrate 1 in correspondence with the above-mentioned void 14. An insulating coating layer 2 is formed thereon. The metal layers 3, 4, 5, and 6 are formed in the same manner as described above except for the protrusion 16 portion.

上述には、ウエハを用いる例について説明した
が、蒸着によるInSb層を使用するときには、第
5図に示すように、第2図の半導体プレート8に
代えて第2の基板17の上に、例えばInSb半導
体層18を第1図のような十字状の形状に蒸着し
たものを使用する。この場合、基板17は、レー
ザ光線例えば波長0.6〜0.9μmが透過する素材、例
えばケイ皮酸ガラスやナトリウムガラスの中から
選定して構成するが、レーザ光線を透過する素材
であればガラスでなくても良い。
In the above, an example using a wafer has been described, but when using a vapor-deposited InSb layer, as shown in FIG. An InSb semiconductor layer 18 deposited in the shape of a cross as shown in FIG. 1 is used. In this case, the substrate 17 is made of a material that transmits the laser beam, for example, a wavelength of 0.6 to 0.9 μm, such as cinnamate glass or sodium glass. It's okay.

上述した説明は磁気抵抗効果素子の場合にも適
用し得る。第1図および第2図に示した例を応用
すると、第6図および第7図のように、基板19
の表面に絶縁被膜層20が設けられ、その上には
基板19の両端に電極用の金属層21,22が形
設され、この金属層21と22の間には等間隔に
且つ並行に短絡電極用条線金属層23が多数設け
られている。そしてこれらの上には半導体プレー
ト24が接着されている。接着は金属層21,2
2,23の熔融によつて行なわれ、また空隙25
は上述の第1図乃至第4図の例と同様に処理し得
る。また、蒸着による素子では第5図の手法が適
用される。
The above explanation can also be applied to the case of magnetoresistive elements. If the example shown in FIGS. 1 and 2 is applied, the substrate 19 as shown in FIGS.
An insulating film layer 20 is provided on the surface of the substrate 19, and metal layers 21 and 22 for electrodes are formed on both ends of the substrate 19, and short circuits are formed between the metal layers 21 and 22 at equal intervals and in parallel. A large number of wire metal layers 23 for electrodes are provided. A semiconductor plate 24 is bonded onto these. Adhesion is the metal layer 21, 2
This is done by melting 2, 23, and the void 25
can be processed in the same way as the examples shown in FIGS. 1 to 4 above. Furthermore, the method shown in FIG. 5 is applied to devices formed by vapor deposition.

上述の全ての実施例では、基板の側に金属層を
形成する場合について説明したが、半導体プレー
トおよび蒸着半導体層の所定位置に金属層を蒸着
形成し、基板上の金属層との両者を融着して接着
し得る。
In all of the above embodiments, the case where the metal layer is formed on the substrate side has been described, but it is also possible to deposit the metal layer at predetermined positions on the semiconductor plate and the deposited semiconductor layer, and fuse both with the metal layer on the substrate. Can be attached and glued.

第8図は半導体シリコン基板26にトランジス
タ等の接合形の半導体装置を構成した場合で、P
形のシリコン基板26にN形領域、即ちコレクタ
領域27,28を形成し、この領域の中にP形領
域、即ちベース領域29,30を形成し、更に領
域29,30の中にN形領域、即ちエミツタ領域
31,32を形成して2つのトランジスタを構成
している。基板26の表面は、SiO或はSiO2の絶
縁被膜層33で全面を被覆している。絶縁被膜層
33の所定位置には、上述した各領域の半導体表
面が露出する窓孔34,35,36,37,3
8,39を形成し、被膜層33の上に窓孔を通し
て各領域と結がる金属層40,41,42,4
3,44,45を形成する。これらの金属層は、
其れ其れコレクタ電極40,43、ベース電極4
2,45、エミツタ電極41,44となる。
FIG. 8 shows a case where a junction type semiconductor device such as a transistor is formed on the semiconductor silicon substrate 26, and P
N-type regions, ie, collector regions 27 and 28, are formed in the shaped silicon substrate 26, P-type regions, ie, base regions 29 and 30 are formed in these regions, and further N-type regions are formed in the regions 29 and 30. That is, emitter regions 31 and 32 are formed to constitute two transistors. The entire surface of the substrate 26 is covered with an insulating coating layer 33 of SiO or SiO 2 . At predetermined positions of the insulating coating layer 33, there are window holes 34, 35, 36, 37, 3 through which the semiconductor surface of each region mentioned above is exposed.
Metal layers 40, 41, 42, 4 are formed on the coating layer 33 and connected to each region through a window hole.
3, 44, 45 are formed. These metal layers are
Collector electrodes 40, 43, base electrode 4
2, 45 and emitter electrodes 41, 44.

ベース電極42,45の上には、ホール素子を
構成する半導体プレート46が跨設され、その出
力電極部が電極42,45と接着されている。半
導体プレート46の入力電極部も同様に図示しな
い金属層に接着されている。
A semiconductor plate 46 constituting a Hall element is placed over the base electrodes 42 and 45, and its output electrode portion is bonded to the electrodes 42 and 45. The input electrode portion of the semiconductor plate 46 is similarly bonded to a metal layer (not shown).

磁気抵抗効果素子を構成する半導体プレートの
場合は、2つのトランジスタに跨ることなく1つ
のトランジスタのベース電極に一方の端部を接着
して行なわれる。3端子型の素子の場合は2つの
磁気抵抗効果素子が結合したものと考えれば良
い。
In the case of a semiconductor plate constituting a magnetoresistive element, one end is bonded to the base electrode of one transistor without spanning two transistors. In the case of a three-terminal type element, it can be considered that two magnetoresistive elements are coupled.

次に、本発明磁電変換装置の製造方法について
述べる。
Next, a method for manufacturing the magnetoelectric transducer of the present invention will be described.

厚さ100〜300μm程度の表面が鏡面状に研磨さ
れたフエライト或は半導体シリコンから成る基板
50の表面に、SiO或はSiO2を厚さ約1500Åに蒸
着して絶縁被膜層51を形成する(第9図A)。
次に、絶縁被膜層51の上に良導体、例えばIn等
を全面蒸着して金属層52を形成し、この後この
層52をレジスタ層を形成して所定のパターン、
例えば第1図の金属層3,4,5,6の形状にエ
ツチング処理し、しかる後レジスト層を除去する
(第9図B)。
An insulating coating layer 51 is formed by depositing SiO or SiO 2 to a thickness of about 1500 Å on the surface of a substrate 50 made of ferrite or semiconductor silicon and having a mirror-polished surface of about 100 to 300 μm. Figure 9A).
Next, a good conductor such as In is deposited on the entire surface of the insulating film layer 51 to form a metal layer 52, and this layer 52 is then used to form a resistor layer to form a predetermined pattern.
For example, etching is performed in the shape of the metal layers 3, 4, 5, and 6 shown in FIG. 1, and then the resist layer is removed (FIG. 9B).

一方、InSbのインゴツトを厚さ0.3〜0.7mm程度
に切断し、一方の粗面を熱可塑性接着剤、例えば
グリースやワツクス或は松ヤニ等の融点が130℃
以上のもので作業基板に接着し、機械研磨、化学
研磨によつて鏡面状に研磨し、しかる後加熱して
片面が研磨された厚さ0.2〜0.5mmのウエハ53を
得る(第10図)。以上の製造工程は従来から公
知の製造方法を適用し得る。
On the other hand, cut the InSb ingot to a thickness of about 0.3 to 0.7 mm, and glue one rough surface with a thermoplastic adhesive such as grease, wax, or pine resin with a melting point of 130°C.
The above material is adhered to a work substrate, polished to a mirror surface by mechanical polishing or chemical polishing, and then heated to obtain a wafer 53 with a thickness of 0.2 to 0.5 mm with one side polished (Fig. 10). . Conventionally known manufacturing methods can be applied to the above manufacturing process.

次に、ウエハ53の鏡面を対向させてウエハ5
3を基板50の金属層52の上に乗せ弱い押圧力
を加えたまま維持する。即ち、ウエハ53と金属
層52の位置合わせを、例えば第1図のように行
なう。しかる後、レーザ装置49を用いてレーザ
光線48をウエハ53の上方から照射し、金属層
52の部分に集束して金属層52を部分的に熔融
し、ウエハ53を基板50に接着する(第1図)。
この接着工程は、第1図の場合には金属層3,
4,5,6ごとに、また第6図の場合には金属層
21,22,23ごとに行われる。
Next, the mirror surfaces of the wafers 53 are placed opposite each other, and the wafers 53
3 on the metal layer 52 of the substrate 50 and maintain it while applying a weak pressing force. That is, the wafer 53 and the metal layer 52 are aligned as shown in FIG. 1, for example. Thereafter, a laser beam 48 is irradiated from above the wafer 53 using a laser device 49, focused on the metal layer 52, partially melting the metal layer 52, and bonding the wafer 53 to the substrate 50 ( Figure 1).
In the case of FIG. 1, this bonding process includes the metal layer 3,
This is done every 4, 5, 6, or in the case of FIG. 6, every metal layer 21, 22, 23.

レーザ装置49は、出力が10ジユール程度のも
ので良く、固体レーザ例えばルビーレーザ装置
(発振波長約0.7μm)やガスレーザ装置例えばN2
―Co2ガスレーザ装置(発振波長約10.6μm)を使
用し得る。レーザ光線の焦点を金属層52で結ば
せると、Inは400〜500℃に熱せられて熔融しウエ
ハ53に被着し、ウエハ52と基板50を絶縁被
膜層51を介在させたままで接着する。従つて、
レーザ光線はウエハ53や基板50更には絶縁被
膜層51に影響を及ぼすことはない。
The laser device 49 may have an output of about 10 joules, and may be a solid-state laser such as a ruby laser device (oscillation wavelength of about 0.7 μm) or a gas laser device such as N 2
-Co2 gas laser equipment (oscillation wavelength approximately 10.6μm) can be used. When the laser beam is focused on the metal layer 52, the In is heated to 400 to 500° C., melts, and adheres to the wafer 53, thereby bonding the wafer 52 and the substrate 50 with the insulating coating layer 51 interposed therebetween. Therefore,
The laser beam does not affect the wafer 53, the substrate 50, or even the insulating coating layer 51.

次に、ウエハ53の他の粗面を機械的化学的手
段で鏡面状に研磨し、厚さ50〜100μmに形成す
る。このウエハ53の表面には、所定パターンの
レジスト層を形成しエツチングしそのレジスト層
を除去する。エツチング液は従来のもので良い。
斯くして、基板50上には電極部が金属層52に
接着した所定形状の半導体プレートが得られる。
Next, the other rough surface of the wafer 53 is polished to a mirror-like surface by mechanical or chemical means to a thickness of 50 to 100 μm. A resist layer having a predetermined pattern is formed on the surface of the wafer 53, and the resist layer is removed by etching. A conventional etching solution may be used.
In this way, a semiconductor plate having a predetermined shape is obtained on the substrate 50, the electrode portion being bonded to the metal layer 52.

ウエハ53の最終的厚さを50〜100μmとすると
きには、他の製造工程を利用することが出来る。
即ち、片面を研磨した第10図のウエハ53を、
作業基板に研磨面を対向して上述の熱可塑性接着
剤で固定し、上述のように機械的研磨、化学的研
磨を経て研磨し、然る後加熱剥離して厚さ50〜
100μmの両面研磨されたウエハを得る。
Other manufacturing processes can be used to achieve a final thickness of wafer 53 of 50-100 μm.
That is, the wafer 53 in FIG. 10, which has been polished on one side, is
The polished surface is fixed to the work substrate with the thermoplastic adhesive described above, and polished through mechanical polishing and chemical polishing as described above, and then heated and peeled to a thickness of 50 ~
Obtain a 100 μm double-sided polished wafer.

このウエハを図示しない治具で吸持しつつ基板
50の所定位置に乗せ、上述のように若干の押圧
力を加えつつレーザ光線を発射し接着させる。こ
の後、ウエハをエツチングして所定の半導体プレ
ートを得る。
This wafer is placed on a predetermined position on the substrate 50 while being held by a jig (not shown), and a laser beam is emitted while applying a slight pressing force as described above to bond the wafer. Thereafter, the wafer is etched to obtain a desired semiconductor plate.

InSbの蒸着技術を使用する場合は、第5図に
於て述べたように、レーザ光線を透過する第2の
基板上にInSbを蒸着して所定形状の半導体層を
形成する。然る後、半導体層の電極部を第9図B
の金属層52に合わせて位置づけ、レーザ光線に
よつて金属層52を部分的に熔融し、接着する。
従つて、半導体層は基板50と第2の基板に狭持
された状態になる。
When using the InSb vapor deposition technique, as described in FIG. 5, InSb is vapor deposited on the second substrate through which the laser beam passes, thereby forming a semiconductor layer having a predetermined shape. After that, the electrode part of the semiconductor layer is shown in FIG. 9B.
, and the metal layer 52 is partially melted and bonded using a laser beam.
Therefore, the semiconductor layer is held between the substrate 50 and the second substrate.

ウエハ53の最終的厚みを5〜10μm程度と薄
くする場合には、第2図に示すように、空隙14
が存在するため上述の製造工程だけでは不完全で
ある。このような場合には次の工程を付加する。
If the final thickness of the wafer 53 is to be as thin as about 5 to 10 μm, as shown in FIG.
Therefore, the above manufacturing process alone is incomplete. In such a case, the following step is added.

即ち、第9図Bの金属層52形成後、絶縁被膜
層52と同じ酸化物を全表面に蒸着して第2の絶
縁被膜層54を形成する。この被膜層54の厚さ
は、金属層52と殆ど同じ厚さか或は若干薄い厚
さに形成する(第12図A)。
That is, after forming the metal layer 52 in FIG. 9B, the same oxide as the insulating coating layer 52 is deposited on the entire surface to form the second insulating coating layer 54. The thickness of this coating layer 54 is approximately the same as that of the metal layer 52, or is formed to be slightly thinner (FIG. 12A).

次に、第2の被膜層54の上に従来技術でレジ
スト層を作り、金属層52の存在しない部分にの
み被膜層54が残るようにエツチング処理し、そ
の後レジスト層を除去する(第12図B)。この
場合、金属層52と被膜層54の境界部分に溝孔
55が生じるようにレジスト層を形成する。この
溝孔55は、金属層52をレーザ光線で熔融した
とき、融解物の広がり圧力を吸収する。
Next, a resist layer is formed on the second coating layer 54 using a conventional technique, and an etching process is performed so that the coating layer 54 remains only in the areas where the metal layer 52 is not present.Then, the resist layer is removed (FIG. 12). B). In this case, the resist layer is formed so that a groove 55 is formed at the boundary between the metal layer 52 and the coating layer 54. This slot 55 absorbs the spreading pressure of the melt when the metal layer 52 is melted with a laser beam.

他の実施例としては、第13図に示すように、
先ず半導体シリコンの基板を用い、この基板56
の表面にレジスト層を形成してエツチング処理し
突部57を形成する(第13図A)。この突部5
7は、第2図の構成の例で説明すれば、空隙14
を埋めるために作られたもので、高さは金属層
3,6の厚さとほぼ同じか或は若干低く形成され
る。次に、基板56の表面に絶縁被膜層58を蒸
着形成し(第13図B)、更にその上に金属層5
9を蒸着する(第13図C)。次に、金属層59
の上に所定のパターンのレジスト層を作り、エツ
チング処理し、その後レジスト層を除去する(第
13図D)。この場合、突部57部分の被膜層6
0と金属層59との境界部分に第12図同様に溝
孔61が形成されることが望ましい。
As another example, as shown in FIG.
First, a semiconductor silicon substrate is used, and this substrate 56 is
A resist layer is formed on the surface and etched to form protrusions 57 (FIG. 13A). This protrusion 5
7 is an air gap 14 if explained using the example of the configuration shown in FIG.
The height is approximately the same as or slightly lower than the thickness of the metal layers 3 and 6. Next, an insulating film layer 58 is formed by vapor deposition on the surface of the substrate 56 (FIG. 13B), and a metal layer 58 is further formed on the surface of the substrate 56 (FIG. 13B).
9 is deposited (FIG. 13C). Next, metal layer 59
A resist layer with a predetermined pattern is formed on the substrate, etched, and then the resist layer is removed (FIG. 13D). In this case, the coating layer 6 at the protrusion 57 portion
It is desirable that a groove hole 61 be formed at the boundary between the metal layer 59 and the metal layer 59 as in FIG.

基板に半導体装置を構成するのは従来の製造方
法を適用し得るのでその説明を省略する。
Since a conventional manufacturing method can be applied to construct a semiconductor device on a substrate, a description thereof will be omitted.

上述の製造工程は、多数の短絡電極用条線金属
層を備えた磁気抵抗効果素子の製造にも適用し得
ることは言うまでもない。
It goes without saying that the above manufacturing process can also be applied to manufacturing a magnetoresistive element having a large number of striped metal layers for short-circuiting electrodes.

また、上述の製造工程では全く基板側に金属層
を形成する場合について説明したが、半導体プレ
ートまたは蒸着半導体層の電極部に金属層を形成
する工程を付加することが出来る。即ち、半導体
プレートまたは蒸着半導体層の片面全体に金属層
を蒸着し、電極部分にレジスト層を形成してエツ
チング処理し、然る後レジスト層を除去して電極
部の上に金属層を重層形成する。この後この金属
層と基板上の金属層が所定の通り対接する如く、
半導体プレートまたは蒸着半導体層を基板の上に
乗せ、レーザ光線で熔融接着する。この工程を付
加すると、接着が両金属層の溶融混合によつて行
われるため、接着作業が容易になる。この工程を
付加するときは、第12図の第2の被膜層54の
厚みは、上述した2つの金属層の厚みの和より若
干薄く形成する。また、第13図の突部57の高
さも上述同様に形成する。
Further, in the above manufacturing process, the case where the metal layer is entirely formed on the substrate side has been described, but a step of forming the metal layer on the electrode portion of the semiconductor plate or the vapor-deposited semiconductor layer can be added. That is, a metal layer is deposited on the entire surface of a semiconductor plate or a deposited semiconductor layer, a resist layer is formed on the electrode part and then etched, and then the resist layer is removed and a metal layer is formed on the electrode part. do. After that, this metal layer and the metal layer on the substrate are brought into contact with each other in a predetermined manner,
A semiconductor plate or a vapor-deposited semiconductor layer is placed on the substrate and fused and bonded with a laser beam. Adding this step facilitates the bonding work because bonding is performed by melting and mixing both metal layers. When this step is added, the thickness of the second coating layer 54 shown in FIG. 12 is formed to be slightly thinner than the sum of the thicknesses of the two metal layers described above. Further, the height of the protrusion 57 shown in FIG. 13 is also formed in the same manner as described above.

叙上の如く、本発明は、基板の上に絶縁被膜層
を形成し、その上に電極となる金属層を形成する
から基板の材質が導電性であると否とに拘らず基
板として利用でき、また基板と半導体部材の接着
に接着剤を全く使用しないから、半導体装置が配
設された場所の周囲の雰囲気の温度が高くなつて
も、熱膨張係数の相違によつて半導体にピエゾ効
果は生ぜず、従つて誤差電圧が著しく小さくなる
から精密計測に多大の効果を生じる。
As mentioned above, since the present invention forms an insulating coating layer on a substrate and forms a metal layer serving as an electrode on it, it can be used as a substrate regardless of whether the material of the substrate is conductive or not. Also, since no adhesive is used to bond the substrate and semiconductor components, even if the temperature of the atmosphere around the location where the semiconductor device is installed increases, the piezoelectric effect will not affect the semiconductor due to the difference in thermal expansion coefficient. Therefore, the error voltage is significantly reduced, which has a great effect on precision measurement.

また、磁電変換装置として構成した場合には、
全体の厚さも従来に比して薄くなるため、より狭
い磁路空隙中に挿着でき、磁気レラクタンスを小
さくして磁束の集中を高め、高い磁電変換効率を
得るので、磁気センサや磁気ヘツド等のような微
少出力を利用する装置に使用して効果大である。
In addition, when configured as a magnetoelectric conversion device,
The overall thickness is also thinner than before, so it can be inserted into a narrower magnetic path gap, reducing magnetic reluctance, increasing concentration of magnetic flux, and achieving high magnetoelectric conversion efficiency, so it can be used in magnetic sensors, magnetic heads, etc. It is highly effective when used in devices that utilize minute output such as.

更に、従来ウエハを接着剤で基板に固定した後
研磨すると、接着層の厚みが均一にならないため
半導体プレートの厚みが不均一になつて不平衡電
圧発生の要因となつていたが、本発明では金属層
は蒸着によつて均一な厚さとなるため、ウエハを
基板に接着した後形成した半導体プレートは全体
的に均一な厚さとなる。これはまた、大きなウエ
ハから多数の半導体プレートを得る場合でも、一
様に同じ厚さの半導体プレートを得ることが出来
るため、多量生産時の歩留りを向上する。
Furthermore, in the past, when a wafer was fixed to a substrate with an adhesive and then polished, the thickness of the adhesive layer was not uniform, resulting in an uneven thickness of the semiconductor plate, which caused unbalanced voltage generation. Since the metal layer is deposited to a uniform thickness, the semiconductor plate formed after bonding the wafer to the substrate has a uniform thickness throughout. This also improves the yield in mass production because even when a large number of semiconductor plates are obtained from a large wafer, the semiconductor plates can be uniformly of the same thickness.

更にまた、半導体プレートに物理的歪が伴わな
いため、仮に不平衡電圧が発生しても回路で電気
的に容易に修正し得る特性となる。
Furthermore, since there is no physical strain on the semiconductor plate, even if an unbalanced voltage occurs, the characteristics can be easily corrected electrically using a circuit.

なお、上述の実施例では磁電変換装置の例につ
いて説明したが、光電変換素子等他のバルク形半
導体装置に適用し得ることは言うまでもない。
In the above embodiments, an example of a magnetoelectric conversion device has been described, but it goes without saying that the present invention can be applied to other bulk type semiconductor devices such as a photoelectric conversion element.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明半導体装置の一例を示す平面
図、第2図は第1図の破線−に於ける断面
図、第3図乃至第5図は本発明装置の其れ其れ他
の実施例を示す断面図、第6図は本発明装置を磁
気抵抗効果装置として構成した場合の平面図、第
7図は第6図の破線―に於ける断面図、第8
図は半導体装置を構成した基板を使用した本発明
装置の断面図、第9図乃至第11図は本発明半導
体装置の製造工程の説明図、第12図および第1
3図は本発明に於ける基板部分の製造工程の説明
図である。 図中の1,19,26,50,56は基板、
2,20,33,51,58は絶縁被膜層、3,
4,5,6,21,22,23,40,41,4
2,43,44,45,52,59は金属層、
8,24,46は半導体プレート、14は空隙、
15,54は第2の絶縁被膜層、16,57は突
部、17は第2の基板、18は蒸着半導体層、4
9はレーザ装置、55,61は溝孔である。
FIG. 1 is a plan view showing an example of the semiconductor device of the present invention, FIG. 2 is a sectional view taken along the dashed line - in FIG. 1, and FIGS. 6 is a plan view of the device of the present invention configured as a magnetoresistive device; FIG. 7 is a sectional view taken along the broken line in FIG. 6; FIG.
The figure is a sectional view of the device of the present invention using a substrate constituting the semiconductor device, FIGS. 9 to 11 are explanatory diagrams of the manufacturing process of the semiconductor device of the present invention, and FIGS.
FIG. 3 is an explanatory diagram of the manufacturing process of the substrate portion in the present invention. 1, 19, 26, 50, 56 in the figure are substrates,
2, 20, 33, 51, 58 are insulating coating layers, 3,
4, 5, 6, 21, 22, 23, 40, 41, 4
2, 43, 44, 45, 52, 59 are metal layers,
8, 24, 46 are semiconductor plates, 14 is a void,
15 and 54 are second insulating coating layers, 16 and 57 are protrusions, 17 is a second substrate, 18 is a vapor deposited semiconductor layer, 4
9 is a laser device, and 55 and 61 are slot holes.

Claims (1)

【特許請求の範囲】 1 四辺形の表面を有する基板と、該基板の表面
に形成された絶縁被膜層と、前記基板の4つの角
部分の前記絶縁被膜層の上に形成した金属層と、
該金属層の上に入力電極部および出力電極部を載
置して前記金属層を熔融することにより前記基板
に接着固定した半導体部材と、から構成したこと
を特徴とする半導体装置。 2 前記基板はフエライトで構成したことを特徴
とする特許請求の範囲第1項記載の半導体装置。 3 前記半導体部材は、第2の基板上に半導体を
蒸着した部材であることを特徴とする特許請求の
範囲第1項または第2項記載の半導体装置。 4 四辺形の表面を有する基板と、該基板の表面
に形成された絶縁被膜層と、前記基板の前記絶縁
被膜層の上に形成した入力電極となる金属層と、
該金属層間に設けた短絡電極となる金属層と、こ
れら金属層の上に載置して前記金属層を熔融する
ことにより前記基板に接着固定した半導体部材と
から構成したことを特徴とする半導体装置。 5 N形領域およびP形領域を形成して半導体装
置を構成した半導体基板と、該基板の表面に前記
領域の電極取り出し部分を除いて形成した絶縁被
膜層と、前記電極取出部分を含んで前記被膜層の
上に形成した良導体金属の電極と、該電極を熔融
して前記基板に電極部を接着した半導体部材と、
から構成したことを特徴とする半導体装置。
[Scope of Claims] 1. A substrate having a quadrilateral surface, an insulating coating layer formed on the surface of the substrate, and a metal layer formed on the insulating coating layer at four corners of the substrate,
A semiconductor device comprising: a semiconductor member having an input electrode portion and an output electrode portion placed on the metal layer and adhesively fixed to the substrate by melting the metal layer. 2. The semiconductor device according to claim 1, wherein the substrate is made of ferrite. 3. The semiconductor device according to claim 1 or 2, wherein the semiconductor member is a member in which a semiconductor is deposited on a second substrate. 4. a substrate having a quadrilateral surface, an insulating coating layer formed on the surface of the substrate, and a metal layer serving as an input electrode formed on the insulating coating layer of the substrate;
A semiconductor characterized in that it is composed of a metal layer that serves as a shorting electrode provided between the metal layers, and a semiconductor member that is placed on these metal layers and adhesively fixed to the substrate by melting the metal layer. Device. 5. A semiconductor substrate in which a semiconductor device is formed by forming an N-type region and a P-type region, an insulating coating layer formed on the surface of the substrate excluding the electrode extraction portion of the region, and the above-mentioned semiconductor substrate including the electrode extraction portion. a well-conducting metal electrode formed on a coating layer; a semiconductor member having an electrode portion bonded to the substrate by melting the electrode;
A semiconductor device comprising:
JP12222879A 1979-09-21 1979-09-21 Semiconductor device and manufacture thereof Granted JPS5646583A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP12222879A JPS5646583A (en) 1979-09-21 1979-09-21 Semiconductor device and manufacture thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP12222879A JPS5646583A (en) 1979-09-21 1979-09-21 Semiconductor device and manufacture thereof

Publications (2)

Publication Number Publication Date
JPS5646583A JPS5646583A (en) 1981-04-27
JPH0230596B2 true JPH0230596B2 (en) 1990-07-06

Family

ID=14830733

Family Applications (1)

Application Number Title Priority Date Filing Date
JP12222879A Granted JPS5646583A (en) 1979-09-21 1979-09-21 Semiconductor device and manufacture thereof

Country Status (1)

Country Link
JP (1) JPS5646583A (en)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5839047A (en) * 1981-09-02 1983-03-07 Hitachi Ltd Semiconductor device and manufacture thereof
FR2569052B1 (en) * 1984-08-10 1987-05-22 Thomson Csf METHOD FOR INTERCONNECTING INTEGRATED CIRCUITS
JPS63152185A (en) * 1986-12-16 1988-06-24 Sharp Corp Manufacture of magneto-sensitive semiconductor device
US5316803A (en) * 1992-12-10 1994-05-31 International Business Machines Corporation Method for forming electrical interconnections in laminated vias

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5137424U (en) * 1974-09-09 1976-03-19
JPS5561024A (en) * 1978-10-31 1980-05-08 Bbc Brown Boveri & Cie Method of manufacturing electric contact of semiconductor element

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5544364Y2 (en) * 1972-07-26 1980-10-17

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5137424U (en) * 1974-09-09 1976-03-19
JPS5561024A (en) * 1978-10-31 1980-05-08 Bbc Brown Boveri & Cie Method of manufacturing electric contact of semiconductor element

Also Published As

Publication number Publication date
JPS5646583A (en) 1981-04-27

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