JPH02305441A - Wafer - Google Patents

Wafer

Info

Publication number
JPH02305441A
JPH02305441A JP12741289A JP12741289A JPH02305441A JP H02305441 A JPH02305441 A JP H02305441A JP 12741289 A JP12741289 A JP 12741289A JP 12741289 A JP12741289 A JP 12741289A JP H02305441 A JPH02305441 A JP H02305441A
Authority
JP
Japan
Prior art keywords
wafer
basket
bulk
film
diffusion
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP12741289A
Other languages
Japanese (ja)
Other versions
JP2612935B2 (en
Inventor
Takashi Okano
隆 岡野
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP1127412A priority Critical patent/JP2612935B2/en
Publication of JPH02305441A publication Critical patent/JPH02305441A/en
Application granted granted Critical
Publication of JP2612935B2 publication Critical patent/JP2612935B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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  • Cleaning Or Drying Semiconductors (AREA)

Abstract

PURPOSE:To prevent the diffusion of particles due to the diffusion of a cleaning residue from the end part of a wafer into a chip formation region by a method wherein at least one round of annular SiO2 film to rise from the surface of the bulk Si part of the wafer is provided on the periphery, which encircles the chip formation region, of the wafer. CONSTITUTION:At least one round of annular SiO2 film 7 to rise from the surface of a bulk Si part 3 of a wafer 1 is provided on the periphery, which encircles a chip formation region 5, of the wafer 1. In the wafer constituted in such a way, a cleaning residue to remain between a basket 4 for housing the wafer 1 and the peripheral edge of the wafer 1 is stopped by the film 7 and is prevented from diffusing into the region 5 at the time of a drying process to be performed after the wafer 1 is housed and cleaned in the basket 4. Thereby, particles being contained in a cleaning fluid or particles being adhered on the basket 4 are prevented from diffusing into the region 5.

Description

【発明の詳細な説明】 [概要] 半導体チップを形成するウェハに関し、ウェハ端部から
チップ形成領域内への洗浄残液の拡散によるパーティク
ルの拡散を防止することを目的とし、 チップ形成領域を取囲むウェハ周囲位置に該ウェハのバ
ルクSi表面より盛上がる環状の5i02躾を少なくと
も1周設けて構成する。
[Detailed Description of the Invention] [Summary] With respect to a wafer on which semiconductor chips are formed, the chip forming area is removed for the purpose of preventing the diffusion of particles due to the diffusion of cleaning residual liquid from the wafer edge into the chip forming area. An annular 5i02 groove that protrudes from the bulk Si surface of the wafer is provided at least once around the surrounding wafer.

[産業上の利用分野] この発明は半導体チップを形成するウェハに関するもの
である。
[Industrial Field of Application] This invention relates to a wafer on which semiconductor chips are formed.

近年の高集積化された半導体装置ではその製造過程にお
いてウェハ上に描画されるパターンが益々微細化され、
これにともなって従来では問題とならなかった微細なパ
ーティクルがつ1ハの洗浄時等に付着してもそのウェハ
から形成される半導体装置の歩留りや信頼性を低下させ
る原因となっている。
In recent years, the patterns drawn on wafers during the manufacturing process of highly integrated semiconductor devices have become increasingly finer.
As a result, even if fine particles, which have not been a problem in the past, adhere to the wafer during cleaning, it becomes a cause of deterioration in the yield and reliability of semiconductor devices formed from the wafer.

[従来の技術] 従来、MOSトランジスタの製造工程ではそのゲート酸
化膜形成工程に先立ってウェハ上にパターニングされた
5i3N411をマスクとしてバルクS!上に5i02
111が形成されるLOGO8工程が行なわれ、その5
i02!!が形成された後には3i3N411が除去さ
れて、第3図に示すようにウェハ1表面に盛り上がった
状態で形成される3i02膜2の間にバルクSi3が露
出される。そして、このようなウェハ1が第4図に示す
ような石英で形成されたバスケット4に多数枚収容され
た状態で洗浄かつ乾燥された後、次工程に送られる。
[Prior Art] Conventionally, in the manufacturing process of MOS transistors, prior to the gate oxide film formation process, bulk S! 5i02 on top
The LOGO8 process in which 111 is formed is performed, and the 5th
i02! ! After the 3i3N411 is formed, the 3i3N411 is removed, and the bulk Si3 is exposed between the 3i02 films 2 formed in a raised state on the surface of the wafer 1, as shown in FIG. A large number of such wafers 1 are housed in a basket 4 made of quartz as shown in FIG. 4, and after being cleaned and dried, they are sent to the next process.

[発明が解決しようとする課題] 上記のような工程で形成されたウェハ1は第4図に鎖線
で示すように同ウェハ1中央部に多数のチップが形成さ
れるチップ形成領15が形成され、そのチップ形成領域
において5i0212が所定のパターンで形成される。
[Problem to be Solved by the Invention] The wafer 1 formed by the above process has a chip forming area 15 in which a large number of chips are formed in the center of the wafer 1, as shown by the chain line in FIG. , 5i0212 is formed in a predetermined pattern in the chip forming region.

チップ形成領域5の周囲はバルクSi3が露出され、各
チップ間のスクライブラインもバルクSi3が露出され
ている。
Bulk Si3 is exposed around the chip forming region 5, and bulk Si3 is also exposed in the scribe line between each chip.

そして、5i021!2は撥水性を備え、バルクS13
は親水性を備えている。
5i021!2 is water repellent and bulk S13
has hydrophilic properties.

このようなウェハ1を前記工程でバスケット4に収容し
て洗浄すると、バスケット4内周面に形成されたウェハ
保持片6とウェハ1端縁部表面との間隙に洗浄液が残り
易く、その洗浄液がウェハ1端縁部からウェハ1中央部
に溝状に連なるスクライブラインを毛管現象により上昇
し、洗浄液中に含まれるパーティクルやバスケット4に
付着しているパーティクルがチップ形成領域中に例えば
第4図に破線で示す範囲りで拡散する。このため、この
範囲り内のチップの多角りが低下してしまう。
When such a wafer 1 is housed in the basket 4 and cleaned in the above process, cleaning liquid tends to remain in the gap between the wafer holding piece 6 formed on the inner peripheral surface of the basket 4 and the edge surface of the wafer 1, and the cleaning liquid tends to A scribe line extending in the form of a groove from the edge of the wafer 1 to the center of the wafer 1 rises due to capillary action, and particles contained in the cleaning liquid and particles attached to the basket 4 are deposited in the chip forming area as shown in FIG. 4, for example. It spreads within the range shown by the broken line. Therefore, the polygon of the chip within this range is reduced.

そこで、このような不具合を防止するために洗浄液を浄
化装置で常に浄化しながら洗浄することが行なわれてい
るが充分な効果を期待することはできなかった。
Therefore, in order to prevent such problems, cleaning is carried out while constantly purifying the cleaning liquid using a purifying device, but a sufficient effect cannot be expected.

この発明の目的は、ウェハの乾燥工程においてウェハ端
部からチップ形成領域内への洗浄残液の拡散によるパー
ティクルの拡散を防止可能とするウェハを提供するにあ
る。
SUMMARY OF THE INVENTION An object of the present invention is to provide a wafer that can prevent the diffusion of particles due to the diffusion of cleaning residual liquid from the wafer edge into the chip forming region during the wafer drying process.

[課題を解決するための手段〕 第1図は本発明の原理説明図である。すなわち、チップ
形成領域5を取囲むウェハ1周囲位置に該ウェハ1のバ
ルクSi3表面より盛上がる環状の5i02膜7を少な
くとも1周設けている3゜[作用コ ウェハ1の乾燥工程時に同ウェハ1を収容するバスケッ
トと同ウェハ1周縁との間に残留する洗浄残液はSi0
2gt7に阻止されてチップ形成領域5内への拡散が防
止される。
[Means for Solving the Problems] FIG. 1 is a diagram illustrating the principle of the present invention. That is, the annular 5i02 film 7 that protrudes from the bulk Si3 surface of the wafer 1 is provided at least once around the wafer 1 surrounding the chip forming region 5. The cleaning residual liquid remaining between the basket and the periphery of the wafer is Si0
2gt7 to prevent diffusion into the chip forming region 5.

[実施例] 以下、この発明を具体化した一実施例を第2図に従って
説明する。なお、前記従来例と同一構成部分は同一番号
を付して説明する。
[Example] An example embodying the present invention will be described below with reference to FIG. Note that the same components as those in the conventional example will be described with the same numbers.

ウェハ1のチップ形成領域5の周囲には5i02!l!
7が環状に形成されている。この5i02!17はLO
CO8工程でチップ形成領域5に3i02pII!2を
形成する工程においてチップ形成領域5内で所定のパタ
ーンで3i3N4mを除去すると同時に、チップ形成領
域5荊囲の5i3N411Jを環状に除去した状態でウ
ェハ1表面を酸化すると、チップ形成領域5中に第3図
に示す5i02膜2が形成されると同時にチップ形成1
i1jl!5周囲に3i02膜7が形成される。
5i02! around the chip forming area 5 of the wafer 1. l!
7 is formed in a ring shape. This 5i02!17 is LO
3i02pII! in the chip formation area 5 in the CO8 process! In the process of forming wafer 2, 3i3N4m is removed in a predetermined pattern in chip forming area 5, and at the same time, 5i3N411J around chip forming area 5 is oxidized in a state in which 5i3N411J is removed in a ring shape. At the same time as the 5i02 film 2 shown in FIG.
i1jl! A 3i02 film 7 is formed around 5.

そして、5i3N41等を除去しC所定のパターンでバ
ルクSi3を露出させたものであり、第3図に示す51
02膜2と同様に5i02膜7ちバルクSi3表面より
盛上がった状態で形成されている。また、この5i02
膜7はウェハ1をバスケット4に収容した状態でウェハ
保持片6より内側を通過する位置に形成されている。
Then, the 5i3N41 etc. were removed to expose the bulk Si3 in a predetermined pattern, and the 51N41 shown in FIG.
Similar to the 02 film 2, the 5i02 film 7 is formed in a raised state from the surface of the bulk Si3. Also, this 5i02
The membrane 7 is formed at a position passing inside the wafer holding piece 6 with the wafer 1 housed in the basket 4.

さて、このように構成されたウェハ1ではバスケット4
に収容して洗浄した後の乾燥工程では、ウェハ保持片6
に洗浄液が残留してもその洗浄液のウェハ1中央部l\
の移動は5102膜7で阻止され、毛管現象による洗浄
液のスクライブラインに沿った拡散が阻止される。従っ
て、fc?’j液中に含まれるパーティクルあるいはバ
スケット4に付着しているパーティクルのデツプ形成領
域5内/\の拡散が防止されるので、このウェハ1から
形成される多数のチップの歩留り及び信頼性を向上させ
ることができる。
Now, in the wafer 1 configured in this way, the basket 4
In the drying process after cleaning and accommodating the wafer, the wafer holding piece 6
Even if the cleaning liquid remains on the central part of the wafer 1
5102 membrane 7 prevents the cleaning liquid from spreading along the scribe line due to capillary action. Therefore, fc? Since particles contained in the liquid or particles attached to the basket 4 are prevented from diffusing into the depth forming region 5, the yield and reliability of a large number of chips formed from this wafer 1 are improved. can be done.

なお、前記実施例では環状の5i02!l!7をチップ
形成領域5荊囲に一周だけ形成したが、これを複数回形
成すればパーティクルの拡散をさらに確実に阻止するこ
とができる、また、5i02膜7はウェハ1周囲に塗布
されたフォトレジストを環状に露光して除去した後、露
出されたバルクSiを酸化することにより形成すること
もできる。
In addition, in the above example, the annular 5i02! l! Although 5i02 film 7 was formed only once around the chip forming area 5, it is possible to more reliably prevent particle diffusion by forming this film multiple times. It can also be formed by annularly exposing and removing Si, and then oxidizing the exposed bulk Si.

[発明の効果] 以上詳述したように、この発明はウェハの乾燥工程にお
いてウェハ端部から中央部への洗浄残液の拡散によるパ
ーティクルの拡散を防止することができる優れた効果を
発揮する。
[Effects of the Invention] As described in detail above, the present invention exhibits an excellent effect of preventing the diffusion of particles due to the diffusion of cleaning residual liquid from the edge of the wafer to the center in the wafer drying process.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明の原理説明図、 第2図は本発明を具体化した一実施例のウェハをバスケ
ットに収容した状態を示す正面図、第3図はチップ形成
領域に酸化膜を形成した状態のウェハを示す断面図 第4図は従来のウェハ乾燥工程時を示す正面図である。 図中、 1はウェハ、 3はバルク511 5はチップ形成領域、 7は5i02膜である。 第1図 本発明の原理説明図 第3図 第4図
Fig. 1 is a diagram explaining the principle of the present invention, Fig. 2 is a front view showing a state in which a wafer according to an embodiment embodying the present invention is housed in a basket, and Fig. 3 is a diagram illustrating the state in which an oxide film is formed in the chip forming area. FIG. 4 is a cross-sectional view showing the wafer in a state in which the wafer is dried. FIG. 4 is a front view showing the conventional wafer drying process. In the figure, 1 is a wafer, 3 is a bulk 511, 5 is a chip forming region, and 7 is a 5i02 film. Figure 1: Explanation of the principle of the present invention Figure 3: Figure 4

Claims (1)

【特許請求の範囲】[Claims] 1、チップ形成領域(5)を取囲むウェハ(1周囲位置
に該ウェハ(1)のバルクSi(3)表面より盛上がる
環状のSiO_2膜(7)を少なくとも1周設けたこと
を特徴とするウェハ。
1. A wafer surrounding a chip forming region (5) (a wafer characterized in that at least one circumference of the wafer (1) is provided with an annular SiO_2 film (7) that rises from the bulk Si (3) surface of the wafer (1)) .
JP1127412A 1989-05-19 1989-05-19 Wafer Expired - Fee Related JP2612935B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1127412A JP2612935B2 (en) 1989-05-19 1989-05-19 Wafer

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1127412A JP2612935B2 (en) 1989-05-19 1989-05-19 Wafer

Publications (2)

Publication Number Publication Date
JPH02305441A true JPH02305441A (en) 1990-12-19
JP2612935B2 JP2612935B2 (en) 1997-05-21

Family

ID=14959330

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1127412A Expired - Fee Related JP2612935B2 (en) 1989-05-19 1989-05-19 Wafer

Country Status (1)

Country Link
JP (1) JP2612935B2 (en)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58103139A (en) * 1981-12-16 1983-06-20 Fujitsu Ltd Heat treatment of semiconductor wafer

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58103139A (en) * 1981-12-16 1983-06-20 Fujitsu Ltd Heat treatment of semiconductor wafer

Also Published As

Publication number Publication date
JP2612935B2 (en) 1997-05-21

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