JPH0230187B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor integrated circuit, and particularly to a semiconductor integrated circuit having a substrate bias voltage generation circuit built into the same chip.

The substrate of a semiconductor integrated circuit having a metal-insulator-semiconductor (MIS) type structure is normally biased to a constant potential. This bias power supply may be applied from outside the integrated circuit, but is more preferably provided on the same chip inside the integrated circuit. FIG. 1 shows a circuit diagram of a conventionally proposed on-chip substrate bias generation circuit. Here 1
01 is an oscillation circuit, 102 is a drive circuit, 103 is an AC coupling capacitor, and 104 and 105 are diode-connected MIS type transistors. 108
is a substrate, and the output terminal 106 of the substrate generation circuit is connected to this substrate. 109 is a capacitance generated between the diffusion region connected to the ground line and the substrate.

Next, the operation will be explained. To simplify the explanation, an n-channel MOS type integrated circuit using a P-type substrate will be taken as an example. The output of oscillator 101 is supplied to capacitor 103 via drive circuit 102 . The threshold voltage of transistors 105 and 104 is VTH, and the output amplitude of transistor 102 is
VPP, the potential at node 107 reaches its maximum value due to the clamping action of transistor 105.
VTH becomes a negative voltage square wave whose minimum value is VTH - VPP. This negative voltage causes transistor 1 to
04, electrons are pumped to the substrate 1
The potential of 08 is negatively biased. Since the substrate potential in the steady state is shifted by the threshold voltage of the transistor 104, it becomes approximately 2VTH-VPP. Since the oscillator 101 and the drive circuit 102 are normally designed to have a logic amplitude ranging from 0 to the power supply voltage VCC, the substrate potential VBB is 2VTH - VCC.
For example, when VTH is 0.6V and VCC is 5.0V, a body bias of approximately -3.8V can be obtained.

Next, consider the fluctuation of the substrate bias generation voltage VBB with respect to the fluctuation of the power supply voltage. When the power supply voltage changes from VCC1 to the lower power supply voltage VCC2, the steady-state value of the body bias voltage generated is 2VTH−
Changes from VCC1 to 2VTH−VCC2. However, in the transient state, as shown in Figure 2, VBB becomes more negative than the potential determined by 2VTH-VCC1 due to capacitive coupling between the n-type diffusion region connected to the power supply line and the P-type substrate. Once it becomes low, it rises toward the steady value 2VTH-VCC2 with a certain time constant τ. This time constant τ is determined by the output resistance of the terminal 106 in FIG. 1 and the capacitance between the board and the ground or between the board and the power supply. The output resistance of the terminal 106 is determined by the leakage current in the reverse bias shape of the PN junction formed by the n-type diffusion region connected to the power supply and ground line and the p-type substrate, so it exhibits a very high resistance value, for example, several The value becomes 10GΩ or more. Therefore, even when the capacity is about 100PF, the time constant τ
is 1 second or more.

The substrate bias in semiconductor integrated circuits is set to the optimum voltage value in a steady state for a given VCC, so the abnormal substrate bias that occurs transiently as described above will affect the operation of the integrated circuit. Undesirable.

Conventional substrate bias generation circuits for semiconductor integrated circuits are configured as described above, so the time constant for abnormal substrate bias that occurs transiently to return to a steady value in response to fluctuations in VCC is large; The drawback was that it interfered with the normal operation of the integrated circuit.

This invention was made in order to eliminate the drawbacks of the conventional ones as described above, and includes providing bypass means having a relatively small resistance value between the output terminal of the substrate bias generation circuit and the ground line or power line. By doing so, it is an object of the present invention to provide a device in which the response of the substrate bias generation voltage to VCC is accelerated.

An embodiment of the present invention will be described below with reference to the drawings. In FIG. 3, 201 is a free-running oscillator;
03 is a drive circuit 20 on the output side of this oscillator 201.
an AC coupling capacitor connected via 2;
05 is a first diode connected between this coupling capacitor 203 and the ground which is a reference potential line.
The MIS transistor 204 is connected between the electrode of the first MIS transistor 205 on the side connected to the coupling capacitor 203 and the substrate 209 via the output terminal 206 of the substrate generation circuit. A second MIS transistor that generates a substrate potential by the voltage of the electrode of the transistor 205; 210 is a grounded n-type diffusion region and the substrate 2;
The junction capacitance 211 generated between the substrate 209 and the substrate 209 is constituted by one depletion type third MIS transistor whose gate is grounded and diode-connected between the substrate 209 and the ground, and the substrate potential is set to the desired potential 2. This is a bypass means to bypass the current so that _VTH - V _CC .

Next, the operation will be explained.

The oscillator 201 is a free-running oscillator, oscillates at a constant oscillation frequency, and supplies a rectangular wave or an output close to a rectangular wave to the drive circuit. Drive circuit 202
In response to this, the waveform is shaped and applied to one end of the AC coupling capacitor 203. The logic amplitude of the signal here is close to VCC. Due to the clamping action of diode-connected transistor 205, the signal at the other end of the capacitor is at the threshold value.
The level is converted to a signal whose maximum value is VTH and minimum value is VTH - VCC. This negative voltage pumps electrons to the substrate through transistor 204, biasing the substrate negatively. transistor 2
Since the threshold voltage of 04 is shifted by VTH, the substrate potential in the steady state becomes 2VTH−VCC,
It is considered that the stray capacitance 210 between the board and the ground is charged by the voltage of 2VTH-VCC. now
When VCC changes from VCC1 to a lower power supply voltage VCC2, the steady-state value of the generated body bias voltage changes from 2VTH-VCC1 to 2VTH-VCC2. In the transient state at this time, as mentioned above, VBB is 2VTH- due to capacitive coupling between the power supply and the board.
The potential is further lowered once in the negative direction than the potential determined by VCC1, but because the third MIS transistor 211 that functions as a resistor is provided between the terminal 206 and the ground to bypass it, the charge stored in the capacitor 210 is It is quickly discharged through the MIS transistor 211, and the steady value 2VTH-
Reaches VCC2. In other words, when the substrate potential is negative and its absolute potential is low, the second MIS transistor 20
4 is cut off in a reverse bias state, and the substrate potential is increased by the third MIS transistor 211, which is equivalent to a resistor. Then, when the substrate potential rises to 2V _TH - V _CC , the second MIS transistor 204 becomes forward biased, and since the conductance of the second MIS transistor 204 is set larger than the conductance of the third MIS transistor, the substrate potential increases. The potential stops rising and settles here. Therefore, it is possible to significantly reduce the adverse effects of the transiently generated body bias voltage in response to a sudden drop in VCC.

With respect to an increase in VCC, since the forward impedance of the transistor 204 is sufficiently lower than that of the third MIS transistor 211, there is little delay in the response of the VBB generated voltage, and this is not a problem.

In the above embodiment, one depletion type MOS transistor with its gate and source short-circuited was used as a diode as the bypass means, but in order to make the impedance of the bypass means variable, as shown in FIG. Wiring 2
It is also possible to adopt a configuration in which trimming can be performed by changing the contact hole 15 or by changing the shape of the contact hole.

Further, in the above embodiment, a ground wire is used as the reference voltage line and a bypass means is provided between the output end of the substrate bias generation circuit and the ground wire, but a power line is used as the reference voltage line and the bypass means is provided between the output end and the power line. It may be provided in between.

As described above, the present invention provides a bypass means consisting of a depletion type transistor whose gate is connected to the reference potential side between the output terminal of the substrate bias generation circuit and the reference potential. This has the effect of making the response faster and providing an integrated circuit with a high operating margin.

[Brief explanation of drawings]

Fig. 1 is a circuit diagram showing a conventional substrate bias generation circuit, Fig. 2 is a schematic diagram showing the response of the generated voltage to power supply voltage fluctuation when using the conventional circuit, and Fig. 3
The figure is a circuit diagram of a substrate bias circuit in one embodiment of the present invention, and FIG. 4 is a circuit diagram showing another embodiment of the bypass means according to the present invention. 201 is an oscillator, 203 is a coupling capacitor,
204 is a second MIS type transistor, 205 is a first MIS type transistor, 209 is a substrate, 211
indicates the third MIS transistor. Note that the same reference numerals in each figure indicate the same or corresponding parts.

Claims (1)

[Claims] 1. In a semiconductor integrated circuit having a substrate potential generation circuit built into the same chip, a coupling capacitor connected to the output side of an oscillator, and a coupling capacitor between the coupling capacitor and the ground. A diode-connected first MIS transistor is connected between the electrode of the first MIS transistor connected to the coupling capacitor and the substrate, and is connected by the voltage of the electrode of the first MIS transistor. It is composed of a second MIS transistor that generates a substrate potential, and a depletion-type third MIS transistor whose gate is connected to a reference potential line and which is diode-connected between the substrate and the reference potential line. 1. A semiconductor integrated circuit comprising: bypass means for bypassing a current so that the voltage reaches a desired potential. 2. The semiconductor integrated circuit according to claim 1, wherein the reference potential line is grounded. 3 The bypass means is formed by connecting a plurality of third MIS transistors in series, and
3. The semiconductor integrated circuit according to claim 1, wherein input terminals of the transistors are selectively grounded.