JPH02301854A - Distributed processing system - Google Patents

Abstract

PURPOSE:To eliminate the necessity of special consideration to the software so that the reliability of the system can be improved by monitoring the quantity of the data fetched to a data latching mechanism and, when the quantity exceeds a fixed value, outputting a fault detecting signal. CONSTITUTION:When abnormality occurs in a processor 11 and the processor 11 does not make data access, new data arriving thereafter are successively stored in a data latching mechanism 16. When the value of an addressing mechanism 17 exceeds a fixed value, it is discriminated that the processor 11 becomes defective and the defective processor 11 is switched to a normal processor 11 so as to secure the function of the whole system by transmitting a fault detecting signal, namely, switch changeover signal to a crossbar switch 15 for making route switching. Therefore, it becomes unnecessary to add a special excessive function to the software of the processor 11 and the reliability of the system is improved.

Description

[Detailed description of the invention] [Object of the invention] (Industrial application field) The present invention is a field processing system applied to fields where high reliability of computers is required, such as nuclear power plants and space technology. Regarding.

(Prior Art) In recent years, distributed processing systems composed of a plurality of processors have come to be used as a means to improve the reliability of computers.

In this distributed processing system, a plurality of processors are provided, each performing a given function, and the entire system is connected through a data transmission path to exchange data and operate in cooperation.

Distributed processing systems were originally intended to improve processing efficiency, but by taking advantage of the characteristics of distributed processing, it has become possible to improve reliability.

Several types of specific hardware configurations for distributed processing systems have been proposed, but even if a part of the processor fails, other healthy processors can take over some of the functions, and the system A distributed processing system using a crossbar switch has been proposed as a method to avoid the failure of the functions of the computer.

FIG. 2 shows an example of a conventional distributed processing system using a crossbar switch. This system connects multiple processors 21, multiple memories 22, and multiple input/output interfaces 23 to transmission lines The crossbar switch 25 allows arbitrary access by switching the set address when the processor 21 accesses the memory 22 and the input/output interface 23. It's supposed to be.

By the way, in this kind of distributed processing system, when all the processors 2 are healthy, the addresses of the crossbar switch 25 are fixed on a one-to-one basis for the memory 22 and the input/output interface 23 for each processor 21. That is, the addresses are set such that the processor 21, memory 22, and input/output interface 2B are either a set or a plurality of sets, and each set can perform a different function.

On the other hand, if a failure occurs in one of the processors 2, the function that the processor 2 was performing will normally go down, or in this system, if one of the processors 2 When this is detected, the crossbar switch 25 switches the address of another processor 21, and the processor 21, the memory 22 and the input/output interface 23 that were originally accessed, are The memory 22 and the input/output interface 2B that were accessed by the processor 21 can also be accessed.

In this way, the functions of the failed processor 2 can be taken over by another processor 2 without any downtime, and the overall functionality can be ensured. Furthermore, since the malfunction of a part of the processor 21 will not spread to the functions of the entire system, it is possible to improve the reliability of the system.

By the way, in this kind of distributed processing system, the most important thing is that if a failure occurs in processor 2,
It is possible to reliably detect the failure.

Conventionally, a watchdog timer has been used as such a failure detection method.

In a distributed processing system using a watchdog timer,
As shown in FIG. 2, in a distributed system using a crossbar switch, each processor 21 also has a timer 2.
6, and each timer 26 constantly counts up the time. On the other hand, the processor
The value of the timer 26 is cleared at regular intervals by software.

By using such a method, the value of the timer 26 will never exceed a certain value as long as the functions of the processors 1 and 21 are healthy.
If it exceeds the fixed value, it can be determined that an abnormality has occurred in the processor 21.

When the timer 26 exceeds a certain value, the timer 26 generates a failure occurrence signal, sends a signal to the crossbar switch 25, and switches the address.

In the watchdog timer type distributed processing system having the above configuration, the software used for each processor 21 must include a function to periodically clear the timer 26. Generally, in computer systems that require high reliability, similar reliability is also required for the software, so the software configuration must be kept as simple as possible and do not include unnecessary functions. Therefore, the watchdog timer type distributed processing system requires special consideration for the software, which poses a problem in terms of software reliability.

Therefore, some people have proposed a distributed processing system using a common memory as shown in FIG.

As shown in FIG. 3, this system is composed of a plurality of processors 31, a plurality of memories 32, and a plurality of input/output interfaces 33 connected by a transmission line 34 and a crossbar switch 35. 3
A common memory 36 is provided which can be accessed in common by all. This common memory 36 stores information indicating the status of each processor 31 while it performs its own function. If the information includes information indicating some kind of abnormal state, the crossbar switch 35 is informed of this fact and address switching is performed.

(Problems to be Solved by the Invention) In the conventional distributed processing system using a common memory, all of the diagnostic information of each processor 31 is concentrated in the common memory 36, so in the unlikely event that this common memory 36 There is a problem in that if a failure occurs, it will have a serious impact on the system.

The present invention has been made with these points in mind, and it provides distributed processing that can detect failures that occur in processors without the need to add extra functions to software and without providing common parts. The purpose is to provide a system.

[Structure of the invention]

(Means for Solving the Problems) As a means for achieving the above-mentioned object 1, the present invention provides a plurality of processors, a plurality of memories, a plurality of input/output interfaces, and a plurality of processors, memories, and input/output interfaces. In a fractional processing system that includes a crossbar switch mechanism that switches paths so that a transmission path is secured between data latch means and data latch mechanism.

The present invention is characterized in that it is provided with a failure detection means for monitoring the amount of data taken into the stage and outputting a failure detection signal when the amount exceeds a certain value.

(Function) In the distributed processing system according to the present invention, the data latch means periodically stores the process data obtained from the target processor and stores it in chronological order, while the processor receives the process data from the data latch means. F I F O (Fj
rst In First 0ut) -Q
- access the data. The amount of data such as the number of data stored in the data latch means is constantly monitored by the failure detection means.

By the way, if the data acquisition cycle of the data latch means and the data reference cycle are made the same, for example, the address value will be approximately constant, and therefore will not normally exceed a certain value.

However, if one of the processors fails and no longer accesses data, the address value gradually increases and eventually exceeds a certain value. This is detected by a failure detection means, and the fact that a failure has occurred in a certain processor is notified to other healthy processors, and the crossbar switch is switched to take over the function of the failed processor.

(Example) An embodiment of the present invention will be described below with reference to FIG.

In FIG. 1, reference numeral 1] indicates a plurality of processors;
These processors 11, multiple memories 2, and multiple input/output interfaces 13 are connected to a crossbar switch 15 via a -Q transmission line 14.

Each input/output interface] 3 is provided with a data latch mechanism 16 and an address mechanism 17, respectively, as shown in FIG. , processor]], data is sequentially sent out from the earliest stored data. The number of data stored in this data latch mechanism 6 is determined so as to be held in the address mechanism 17.

Next, the operation of this embodiment will be explained.

Each input/output interface 13 takes in data at a constant cycle, stores the data in the data latch device +M 16, and counts up the value of the address mechanism 17 by one.

On the other hand, each processor 11 has an input/output interface 1
When data from 3 is required, data access is made to the input/output interface 13. Then, the input/output interface 13 passes the earliest data stored in the data latch mechanism 16 to the processor 1 and counts down the value of the address mechanism 17 by one.

Here, if the data acquisition cycle at the input/output interface 13 and the data access cycle from the processor] are made the same, the process data transmitted to the processor 11 can be sufficiently new, and moreover, the address machine The value held at +1417 also becomes 1 or 0 and does not increase any further. therefore,
In order to confirm the health of the processor 11, it is sufficient to monitor that the value of the address mechanism 17 is 1 or less.

That is, when an abnormality occurs in the processor 11 and data access is no longer performed, new data is stored one after another in the data latch mechanism 16, and the address mechanism 1
The value of 7 also gradually increases accordingly. Then, when the value of the address mechanism reaches a certain value, for example 3 or more, it is determined that a failure has occurred in that processor 11, and the failure is detected by the crossbar switch 5 (r3, Convey the switching signal and switch the route 11
A healthy processor 11 takes over the functions of the failed processor]1, and the functions of the entire system are maintained (1n).

As described above, according to the present embodiment, failure detection can be performed without adding special functions to the software of the processor 1, and reliability can be improved due to the simplicity of the software. In addition, since the diagnostic mechanism is distributed among each subsystem and has no common parts, it is possible to improve the reliability of the entire system.

In addition, in the above embodiment, the case where the number of data of the data latch mechanism 16 is stored in the address mechanism]7 is explained, or the number of data itself does not need to be stored. A method such as having an address register storing data and monitoring the difference therebetween may also be used.

Furthermore, in the embodiment, the data acquisition period and the data access period from the processor 11 are the same.
- However, it is not necessary to make both synchronizations the same. For example, the same function can be achieved by appropriately manipulating the value of the register using a method using the address register.

〔Effect of the invention〕

As explained above, the present invention does not require any special extra functions to be added to the software of the processor, and there is no common part where failure of that part would seriously affect the entire system. Reliability can be significantly improved.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing a distributed processing system according to an embodiment of the present invention, FIG. 2 is a block diagram showing a conventional distributed processing system using a watchdog timer method, and FIG. 3 is a block diagram showing a conventional distributed processing system using a common memory method. FIG. 1 is a configuration diagram showing a processing system. DESCRIPTION OF SYMBOLS 11... Processor, 12... Memory, ]3. Input/output interface, ]-4... Transmission line, 15. Crossbar switch, 16... Data latch machine hL]-7
...Address mechanism.

Claims (1)

[Claims] Distributed processing that includes multiple processors, multiple memories, multiple input/output interfaces, and a crossbar switch mechanism that switches paths so that transmission paths are secured between arbitrary processors, memories, and input/output interfaces. In the system, there is a data latch means that periodically captures input/output data and sends out the captured data through data access from the processor, and a data latch means that monitors the amount of data captured by the data latch means and maintains the value at a constant value. A distributed processing system comprising: failure detection means for outputting a failure detection signal when a failure detection signal is exceeded.