JPH0230138A - Semiconductor device - Google Patents

Abstract

PURPOSE:To obtain a highly reliable semiconductor device which is free from passivation cracks and Al slide by surrounding at least part of the periphery of an LSI chip with metallic wiring separately from the circuit wiring. CONSTITUTION:At least part of the periphery of an LSI chip is surrounded by a metallic pattern 4' separately from the circuit wiring 4. When the metallic patter 4' is covered with a polyimide 6', the optimum result can be obtained. For example, an element separating insulating film 2 and inter-layer insulating film 3 are formed on an Si substrate 1 in the vicinity of a chip edge 7 and an Al pad or the wiring 4 is formed on the inter-layer insulating film 3, with the film 3 and wiring 4 being covered with a passivation 5. Moreover, the Al pattern 4', a passivation 5', and polyimide pattern 6' are formed on the inside of the chip edge 7. The Al pattern 4' is a dummy pattern and formed simultaneously with the Al pad and Al wiring 4.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Field of Application 1] The present invention relates to a semiconductor device. In particular, a semiconductor device that is resistant to thermal stress is provided.

[Prior art 1] Conventionally, in an LSI chip, an AL pad was present at the outermost periphery, and the AL pad and a lead frame were connected with a gold wire. However, as chips and packages become larger, the stress on the sealing resin increases, resulting in frequent problems such as misalignment of AL pads and AL wiring and cracks in the chip protective film.

[Problem M to be Solved by the Invention] It is an object of the present invention to avoid such one drawback of the conventional technology and provide a highly reliable semiconductor device in which passivation cracks and AL sliding do not occur.

[Means for Solving the Problems 1] In the present invention, a dummy pattern is formed at least in a portion around the LSI chip, for example, at the four corners of the chip where stress concentration is large. Stress in the resin is applied horizontally to the chip from the periphery toward the center of the chip, but because the stress is absorbed or relaxed by the dummy pattern, no stress is applied to the circuit parts including the pads inside the depth, and no stress is applied to the circuit area other than the dummy pattern. No AL sliding or passivation cracks occur.

Embodiment 1 FIG. 1 is a sectional view of a semiconductor device according to the present invention, near a chip end. An element isolation insulating film 2 and an interlayer insulating film 3 are accumulated on the Si substrate 1, and an AL pad 4 or a wiring 4 is formed on the interlayer insulating film 3 and covered with a passivation 5. In the embodiment, AL4' is placed inside the chip end 7.
, passivation 5', and polyimide pattern 6'
is formed. The AL pattern 4' is a dummy pattern and can be formed simultaneously with the AL pad and AL wiring 4 in the circuit of the chip. Figure 2 is a diagram of the chip viewed from the surface, where 10 indicates the chip edge and 11 indicates the position of a dummy pattern made of AL heavy metal. It may be a melting point metal or a heavy metal such as Cu.

[Effect of the invention 1] According to the present invention, the dummy patterns 4', 5', and 6' absorb resin stress, and the stress is not concentrated inside the dummy pattern 11, that is, on the AL wiring 4 and the passivation film 5. Thermal stress applied during mold resin sealing and mounting can be avoided, and passivation cracks and AL slides do not occur in the LSI chip circuit element and AL pad portion, providing a highly reliable semiconductor device.

[Brief explanation of the drawing]

FIG. 1 is a sectional view of a semiconductor device according to the present invention. FIG. 2 is a plan view of a semiconductor device according to the present invention.・Si substrate ・Element isolation insulating film ・Interlayer insulating film ・AL pad or AL wiring ・Passivation film ・Polyimide protective film ・AL dummy pattern ・Passivation dummy pattern ・Polyimide dummy pattern ・LSI chip end 11... Dummy pattern or more Applicant Seiko Epson Corporation Representative Patent Attorney Masaharu Kamiyanagi (and 1 other person) ¥11
Including φ 2 wards

Claims (2)

[Claims] (1) A semiconductor device characterized in that at least a portion of the periphery of the LSI chip is surrounded by a metal pattern separate from circuit wiring. (2) The semiconductor device according to claim 1, wherein the metal pattern is covered with polyimide.