JP4326891B2 - Manufacturing method of semiconductor device - Google Patents

Manufacturing method of semiconductor device Download PDF

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JP4326891B2
JP4326891B2 JP2003325962A JP2003325962A JP4326891B2 JP 4326891 B2 JP4326891 B2 JP 4326891B2 JP 2003325962 A JP2003325962 A JP 2003325962A JP 2003325962 A JP2003325962 A JP 2003325962A JP 4326891 B2 JP4326891 B2 JP 4326891B2
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semiconductor substrate
resin
forming
semiconductor
alignment mark
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JP2005093776A (en
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博之 倉田
文彦 山崎
由光 唐澤
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New Japan Radio Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA

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  • Dicing (AREA)

Description

本発明は、半導体装置の製造方法に関する。さらに詳しくは、個々の半導体装置に切断して分割する際、切断位置の位置合わせ精度を良くすることができる半導体装置の製造方法に関する。   The present invention relates to a method for manufacturing a semiconductor device. More particularly, the present invention relates to a method for manufacturing a semiconductor device that can improve the alignment accuracy of a cutting position when the semiconductor device is divided into individual semiconductor devices.

近年、電子機器の小型化に伴い、部品として搭載される半導体装置の小型化の要求が強まってきている。半導体装置の小型化を実現する手段として、図１３または図１４に示す構造の半導体装置が提案されている。これは、半導体チップ２１の周囲に形成される電極パッド２１ａを半導体チップ２１の面積全体に分散させて外部電極２７を形成するチップサイズパッケージ（以下ＣＳＰという）と呼ばれる構造である。ＣＳＰには材料構成、構造上様々なタイプがあるが、図１３に示す例は、セラミック基板、ポリイミドなどの有機材基板、フィルムテープなどからなるインターポーザ２６の一面に配線（図示せず）を形成し、半導体チップ２１の電極パッド２１ａとインターポーザ２６の配線とを金線２４を用いて接続し、さらにインターポーザの配線を外部電極２７と接続している。半導体チップ２１は、被覆樹脂２５により封止されている。また図１４に示す例は、半導体チップ２１の電極パッド２１ａとインターポーザ２６の配線とを金線２４で接続する代わりにバンプ２１ｂによって接続している。なお、２８は半導体チップ２１を固定する樹脂層である。   In recent years, with the miniaturization of electronic devices, there is an increasing demand for miniaturization of semiconductor devices mounted as components. As means for realizing miniaturization of a semiconductor device, a semiconductor device having a structure shown in FIG. 13 or FIG. 14 has been proposed. This is a structure called a chip size package (hereinafter referred to as CSP) in which the electrode pads 21 a formed around the semiconductor chip 21 are dispersed over the entire area of the semiconductor chip 21 to form the external electrodes 27. There are various types of CSPs in terms of material structure and structure. In the example shown in FIG. 13, wiring (not shown) is formed on one surface of an interposer 26 made of a ceramic substrate, an organic material substrate such as polyimide, or a film tape. The electrode pads 21a of the semiconductor chip 21 and the wiring of the interposer 26 are connected using the gold wire 24, and the wiring of the interposer is connected to the external electrode 27. The semiconductor chip 21 is sealed with a coating resin 25. In the example shown in FIG. 14, the electrode pads 21 a of the semiconductor chip 21 and the wiring of the interposer 26 are connected by the bumps 21 b instead of the gold wires 24. Reference numeral 28 denotes a resin layer for fixing the semiconductor chip 21.

このようにインターポーザを介在させることにより、半導体チップの周囲に非常に狭い間隔で設けられている電極パッドをインターポーザの面積全体に分散させてパッケージ機能をもたせることによって、実装基板などに直接接続することが可能となる。すなわち、通常は半導体チップの周囲に設けられた電極パッドの間隔は１００〜２００μｍ程度以下であるのに対し、実装基板の配線間隔は０．５mm程度のため、半導体チップの電極パッドと実装基板の配線を直接接続することはできないが、図１３、図１４に示すようにインターポーザを介在させることで、電極を分散させ実装基板に直接接続することを可能にしている。   By interposing the interposer in this way, the electrode pads provided at very narrow intervals around the semiconductor chip are distributed over the entire area of the interposer to provide a package function, thereby connecting directly to a mounting board or the like. Is possible. That is, the interval between the electrode pads provided around the semiconductor chip is usually about 100 to 200 μm or less, whereas the wiring interval between the mounting substrates is about 0.5 mm. Although wiring cannot be directly connected, the interposer is interposed as shown in FIGS. 13 and 14, so that the electrodes can be dispersed and directly connected to the mounting board.

しかし、インターポーザを用いる方法はリードフレームを使用する半導体装置に比べて、一般的にコストが高くなる。そこで本願出願人は、半導体基板上へのバンプの形成から半導体装置の完成まで製造工程を減らすため、半導体基板に一括してボンディングバッドやバンプ等を形成し、樹脂封止およびダイシングによる分割等を行う方法を提案した（特願２００２−１４４１２４号）。   However, the method using an interposer is generally more expensive than a semiconductor device using a lead frame. Therefore, in order to reduce the manufacturing process from the formation of bumps on the semiconductor substrate to the completion of the semiconductor device, the applicant of the present application forms bonding pads and bumps on the semiconductor substrate all at once, and performs resin sealing and dicing division, etc. The method of performing was proposed (Japanese Patent Application No. 2002-144124).

しかし本願出願人が提案した方法では、半導体基板全面を樹脂封止してしまい、個々の半導体装置にダイシングブレードを用いて切断分離する際、切断位置の位置決めが困難になってしまうという問題があった。この種の半導体装置においては、品質を確保するためには高い位置精度が要求され、その要求を満足することができなかった。このような問題を解決する方法として特開平１１−２６０７６８号公報には、樹脂封止膜のアライメントマーク（位置合わせマーク）に対応する部分に選択的に開口部を設ける方法が開示されている。その開口部を形成する具体的な方法として、トランスファモールド法による樹脂形成や、樹脂封止膜を全面に形成した後、薬品あるいはレーザ光を用いて開口部を作成する方法が開示されている。しかしこれらの方法では、加工設備を必要とし、また開口部を形成するため工程が増加してしまい、コストが高くなるという問題があった。   However, the method proposed by the applicant of the present application has a problem that the entire semiconductor substrate is sealed with resin, and it becomes difficult to position the cutting position when cutting and separating each semiconductor device using a dicing blade. It was. In this type of semiconductor device, high positional accuracy is required to ensure quality, and the requirement cannot be satisfied. As a method for solving such a problem, Japanese Patent Application Laid-Open No. 11-260768 discloses a method of selectively providing an opening in a portion corresponding to an alignment mark (positioning mark) of a resin sealing film. As a specific method for forming the opening, there is disclosed a method of forming an opening using a chemical or laser light after forming a resin by a transfer molding method or forming a resin sealing film on the entire surface. However, in these methods, there is a problem that processing equipment is required and the process is increased because the opening is formed, resulting in an increase in cost.

また位置合わせマークを露出して樹脂形成を行うため、印刷法によるのが簡便であるが、印刷法では位置合わせマークを被覆するマスクを、半導体基板外周部から延出するように形成するため、図１５に示すように開口部２９が形成されてしまう。このように位置合わせマークとともに半導体基板の外周方向の領域を露出する形状の開口部２９では、半導体基板を研磨する際、開口部２９の半導体基板の外周部分に割れ、欠け、クラック、樹脂剥離等が生じるという問題があった。
特開平１１−２６０７６８号公報 In addition, since the alignment mark is exposed and the resin is formed, it is easy to use the printing method, but in the printing method, the mask that covers the alignment mark is formed so as to extend from the outer periphery of the semiconductor substrate. As shown in FIG. 15, an opening 29 is formed. Thus, in the opening 29 having a shape that exposes the region in the outer peripheral direction of the semiconductor substrate together with the alignment mark, when the semiconductor substrate is polished, the outer peripheral portion of the semiconductor substrate of the opening 29 is cracked, chipped, cracked, resin peeled, etc. There was a problem that occurred.
JP-A-11-260768

インターポーザを介在させたＣＳＰは、小型、薄型、軽量化は実現できてもコスト高になるという問題があった。また本願出願人が提案した方法では、個々の半導体装置に切断分離する際、位置合わせ精度を向上させることができないという問題があった。本発明はこれらの問題を解決するために、インターポーザを用いずに直接実装基板に接合することが可能な構造で、個々の半導体装置に切断分離する際、位置決め精度の高い半導体装置の製造方法を提供することを目的とする。   The CSP with the interposer interposed has a problem that the cost is increased even if the CSP can be reduced in size, thickness, and weight. Further, the method proposed by the applicant of the present application has a problem that the alignment accuracy cannot be improved when cutting and separating into individual semiconductor devices. In order to solve these problems, the present invention provides a method for manufacturing a semiconductor device having a high positioning accuracy when cutting and separating into individual semiconductor devices with a structure that can be directly bonded to a mounting substrate without using an interposer. The purpose is to provide.

本発明は上記目的を達成するため、半導体基板の一主面に、電子回路を形成し、該電子回路の電極端子を前記半導体基板上で配線を介して分散することによる再配置させた電極パッドを形成すると共に、前記半導体基板一主面の外周部近傍に、前記半導体基板を切断分離する際、切断位置の基準となる位置合わせマークを形成する工程と、前記電極パッド上にハンダコアを形成する工程と、前記ハンダコアを形成した前記半導体基板の一主面を印刷法により樹脂封止する工程と、該封止樹脂及び前記ハンダコアを研磨し、前記ハンダコアの一部を露出させる工程と、前記半導体基板の別の一主面を研磨した後、該別の一主面に樹脂層を形成する工程と、前記露出したハンダコア上にハンダバンプを形成する工程と、前記露出する位置合わせマークを基準として前記半導体基板を切断分離し、個々の半導体装置に分割する工程とを備えた半導体装置の製造方法において、前記ハンダコアを形成した前記半導体基板の一主面を印刷法により樹脂封止する際、前記半導体基板の外周部に向かって開口する凹部により前記位置合わせマークを含む領域を露出するように開口部を形成すると共に、前記位置合わせマークより前記半導体基板の外周方向の領域に樹脂補強部を形成する工程を含むことを特徴とする。 In order to achieve the above object, the present invention provides an electrode pad that is rearranged by forming an electronic circuit on one main surface of a semiconductor substrate and dispersing electrode terminals of the electronic circuit via wiring on the semiconductor substrate. And forming an alignment mark serving as a reference for the cutting position when the semiconductor substrate is cut and separated in the vicinity of the outer peripheral portion of the one main surface of the semiconductor substrate, and a solder core is formed on the electrode pad A step of resin-sealing one main surface of the semiconductor substrate on which the solder core is formed by a printing method, a step of polishing the sealing resin and the solder core to expose a part of the solder core, and the semiconductor After polishing another principal surface of the substrate, a step of forming a resin layer on the other principal surface, a step of forming solder bumps on the exposed solder core, and the exposed alignment mask A method of cutting and separating the semiconductor substrate with reference to a substrate and dividing the semiconductor substrate into individual semiconductor devices, wherein one main surface of the semiconductor substrate on which the solder core is formed is resin-sealed by a printing method When forming, an opening is formed so as to expose a region including the alignment mark by a recess opening toward the outer peripheral portion of the semiconductor substrate, and a resin is formed in the outer peripheral direction region of the semiconductor substrate from the alignment mark The method includes a step of forming a reinforcing portion .

本発明の製造方法によれば、半導体基板表面に通常の半導体装置の製造プロセスを用いて電極端子の再配置を行い、電極パッドの間隔を広げて形成することができ、インターポーザを用いることなく実装基板に直接接続することができる半導体装置を形成することができるので、低コスト化を図ることができる。
同時に、樹脂層の形成は少なくとも位置合わせマークを含む領域を開口しているので、この位置合わせマークを基準にして寸法精度の高い切断分離が可能となる。特に、この位置合わせマークを含む領域より半導体基板の外周方向の領域には樹脂層を形成しているため、半導体基板全面に樹脂層が形成された場合同様、半導体基板裏面の研磨時に半導体基板の割れ、欠け、クラック、樹脂の剥離等の発生がない。 According to the manufacturing method of the present invention, the electrode terminals can be rearranged on the surface of the semiconductor substrate by using a normal semiconductor device manufacturing process, and the electrode pads can be formed with a wider interval, and can be mounted without using an interposer. Since a semiconductor device that can be directly connected to the substrate can be formed, cost reduction can be achieved.
At the same time, since the formation of the resin layer opens at least a region including the alignment mark, it becomes possible to perform cutting and separation with high dimensional accuracy based on the alignment mark. In particular, since the resin layer is formed in the outer peripheral region of the semiconductor substrate from the region including the alignment mark, as in the case where the resin layer is formed on the entire surface of the semiconductor substrate, the semiconductor substrate is polished when the back surface of the semiconductor substrate is polished. There is no occurrence of cracks, chips, cracks, and resin peeling.

本発明は、半導体装置表面に設けられる電極端子を再配置して電極パッド間の間隔を広げ、インターポーザを用いることなく実装基板に直接接続することができるよう構成し、電極パッド、位置合わせマーク、ハンダコア、ハンダバンプ、樹脂層形成等の各工程を効率的に形成する。さらに樹脂層を形成する際、位置合わせマークが露出するように開口部を形成すると共に、半導体基板の外周方向の領域に樹脂補強部を形成することにより、半導体基板の研磨時に半導体基板の割れ、欠け、クラック、樹脂の剥離等を発生させず、寸法精度の高い切断分離を行う。   The present invention rearranges the electrode terminals provided on the surface of the semiconductor device to widen the space between the electrode pads, and is configured to be directly connected to the mounting substrate without using an interposer. The electrode pads, alignment marks, Each process such as solder core, solder bump, and resin layer formation is efficiently formed. Further, when forming the resin layer, by forming the opening so that the alignment mark is exposed, and forming the resin reinforcing portion in the region in the outer peripheral direction of the semiconductor substrate, the semiconductor substrate is cracked during polishing of the semiconductor substrate, Performs cutting and separation with high dimensional accuracy without causing chipping, cracking, resin peeling and the like.

以下、本発明の半導体装置の製造方法について詳細に説明する。まず図１に示すように、半導体基板１の表面（一主面）に電子回路（図示せず）やその電子回路の電極端子２を形成する。半導体基板１の表面には、絶縁膜３を形成して回路素子を保護している。半導体基板１上には、複数の半導体装置が形成されている。なお図１〜１０においては、１個の電極端子およびその電極端子に接続して設ける１個のバンプ電極が示されているが、複数の半導体装置上にある複数の電極端子について、同時に同様の方法でバンプ電極の形成が行なわれる。   The method for manufacturing a semiconductor device of the present invention will be described in detail below. First, as shown in FIG. 1, an electronic circuit (not shown) and electrode terminals 2 of the electronic circuit are formed on the surface (one main surface) of the semiconductor substrate 1. An insulating film 3 is formed on the surface of the semiconductor substrate 1 to protect circuit elements. A plurality of semiconductor devices are formed on the semiconductor substrate 1. 1 to 10 show one electrode terminal and one bump electrode provided to be connected to the electrode terminal, the same applies to a plurality of electrode terminals on a plurality of semiconductor devices at the same time. The bump electrode is formed by the method.

つぎに、Ａｌ-Ｓｉ（Ｓｉが１ｗｔ％）などからなる電極材料をスパッタ法などにより１μm程度の厚さに成膜してパターニングすることにより、図２に示すように、電極端子２と接続してバンプ電極を形成する所望の場所まで引き延ばし、再配置するための配線４を形成する。ここでは配線４と同時に位置合わせマーク１６を半導体基板１上に形成する。位置合わせマーク１６は、前述の電子回路や電極端子２と同時に形成しても良い。その後図３に示すように、ＣＶＤ法などにより被覆層５を全面に設け、バンプ電極形成予定領域のみが露出するようにパターニングする。この際、バンプ電極形成予定領域として配線４を露出させた再配置の電極パッド４ａは、実装基板に直接接続可能となる間隔となるように形成されている。   Next, an electrode material made of Al—Si (Si is 1 wt%) is formed to a thickness of about 1 μm by sputtering or the like and patterned to connect to the electrode terminal 2 as shown in FIG. Then, the bump 4 is extended to a desired place to form a wiring 4 for rearrangement. Here, the alignment mark 16 is formed on the semiconductor substrate 1 simultaneously with the wiring 4. The alignment mark 16 may be formed simultaneously with the electronic circuit and the electrode terminal 2 described above. Thereafter, as shown in FIG. 3, a coating layer 5 is provided on the entire surface by CVD or the like, and is patterned so that only the bump electrode formation scheduled region is exposed. At this time, the rearranged electrode pads 4a in which the wirings 4 are exposed as the bump electrode formation scheduled regions are formed so as to have an interval that allows direct connection to the mounting substrate.

次に図４に示すように、再配置した電極パッド４ａ上にバリアメタル層６を無電界メッキ法によって形成する。次に図５に示すように、バリアメタル層６の表面にハンダペーストを印刷する。その後不活性ガス雰囲気で、熱処理することによりハンダコア７を形成する。   Next, as shown in FIG. 4, a barrier metal layer 6 is formed on the rearranged electrode pad 4a by an electroless plating method. Next, as shown in FIG. 5, a solder paste is printed on the surface of the barrier metal layer 6. Thereafter, the solder core 7 is formed by heat treatment in an inert gas atmosphere.

次に図６に示すように、半導体基板表面（ハンダコア７を形成した面）側にたとえばフィラー入りエポキシ樹脂を大気圧下で印刷マスクを介して塗布し、樹脂層８を形成する。本発明では、図１２に半導体基板上の樹脂形成領域の平面図を示すように形成することがポイントとなる。図１２において、斜線部分が樹脂形成領域、白い部分が開口領域１４（位置合わせマーク１６を含む樹脂未封止領域）である。開口領域１４は、図には１ヶ所のみ表示しているが実施例では半導体基板の外周部に、少なくとも３箇所以上設けると、位置合わせが容易となる。図６に示す断面図では、右端に示す領域が図１２に示す樹脂補強部１７に相当し、樹脂層８で被覆された領域が半導体装置形成領域１９に相当する。   Next, as shown in FIG. 6, for example, a filler-filled epoxy resin is applied to the semiconductor substrate surface (surface on which the solder core 7 is formed) side through a printing mask under atmospheric pressure to form a resin layer 8. In the present invention, the point is to form the resin formation region on the semiconductor substrate as shown in FIG. In FIG. 12, the hatched portion is the resin formation region, and the white portion is the opening region 14 (resin unsealed region including the alignment mark 16). Although only one opening region 14 is shown in the figure, in the embodiment, when at least three or more locations are provided on the outer peripheral portion of the semiconductor substrate, alignment becomes easy. In the cross-sectional view shown in FIG. 6, the region shown at the right end corresponds to the resin reinforcing portion 17 shown in FIG. 12, and the region covered with the resin layer 8 corresponds to the semiconductor device formation region 19.

本発明では、図１２に示すように位置合わせマーク１６より半導体基板１の外周方向に設ける樹脂補強部１７と半導体装置形成領域１９とが形成されるように樹脂形成領域を形成することで、位置合わせマーク１６を直接視認でき、ダイシング時の高精度の位置合わせが可能となる。また、樹脂補強部１７によって、以降の半導体基板の研磨工程時に、半導体基板の欠け等を防止できる。なお、樹脂補強部１７は、図１２に示す構造に限定されるものではなく、半導体装置形成領域１９に一部が連結していてもよい。しかし、印刷法によるため、開口領域１４は半導体基板の外周部にむかって開口することになる。これは、位置合わせマーク１６を露出させるために用いる印刷マスクの連結部分に相当する部分である。なお、この連結部分を十分に細く形成することにより、あるいは流動性のある樹脂を用いることにより、連結部にマスクされた領域も樹脂で被覆できる場合がある。   In the present invention, as shown in FIG. 12, the resin forming region is formed so that the resin reinforcing portion 17 and the semiconductor device forming region 19 provided in the outer peripheral direction of the semiconductor substrate 1 from the alignment mark 16 are formed. The alignment mark 16 can be directly visually confirmed, and high-precision alignment during dicing is possible. Further, the resin reinforcing portion 17 can prevent chipping of the semiconductor substrate during the subsequent polishing process of the semiconductor substrate. The resin reinforcing portion 17 is not limited to the structure shown in FIG. 12, and a part of the resin reinforcing portion 17 may be connected to the semiconductor device forming region 19. However, because of the printing method, the opening region 14 opens toward the outer periphery of the semiconductor substrate. This is a portion corresponding to a connection portion of a print mask used for exposing the alignment mark 16. In addition, by forming the connecting portion sufficiently thin or using a fluid resin, the region masked by the connecting portion may be covered with the resin in some cases.

次に図７に示すように、半導体基板表面側の樹脂層８を研磨してハンダコア７の一部を露出させる。この研磨により、樹脂補強部１７は樹脂層８と同じ高さになるよう研磨される。次に図８に示すように、半導体基板１の裏面（別の一主面）を研磨する。その後、図９に示すように、研磨した半導体基板１の裏面側に、例えばフィラー入りエポキシ樹脂を大気圧下で印刷により塗布して裏面樹脂層９を形成する。その後、熱処理し、樹脂を硬化させる。   Next, as shown in FIG. 7, the resin layer 8 on the surface side of the semiconductor substrate is polished to expose a part of the solder core 7. By this polishing, the resin reinforcing portion 17 is polished so as to have the same height as the resin layer 8. Next, as shown in FIG. 8, the back surface (another main surface) of the semiconductor substrate 1 is polished. Thereafter, as shown in FIG. 9, for example, an epoxy resin containing a filler is applied by printing under atmospheric pressure to the back side of the polished semiconductor substrate 1 to form the back side resin layer 9. Thereafter, heat treatment is performed to cure the resin.

次に図１０に示すように、ハンダコア７上にハンダペーストを印刷法により形成し、熱処理を行うことでハンダバンプ１０をする。次に図１１に示すように、半導体基板上に多数形成された半導体装置の境界部でダイシングソー１３を用いて切断分離し、個片化する。具体的には半導体基板の裏面側をダイシングテープ１２に貼着し、表面側３箇所の樹脂層開口部に露出した位置合わせマーク１６を視認して位置合わせを行い、ダイシングソー１３を走査させることにより個々の半導体装置に切断分離し、半導体装置を完成する。   Next, as shown in FIG. 10, a solder paste is formed on the solder core 7 by a printing method, and a solder bump 10 is formed by heat treatment. Next, as shown in FIG. 11, a dicing saw 13 is used for cutting and separating into individual pieces at the boundary portions of the semiconductor devices formed on the semiconductor substrate. Specifically, the rear surface side of the semiconductor substrate is attached to the dicing tape 12, and the alignment marks 16 exposed at the resin layer openings at three positions on the front surface side are visually recognized and aligned, and the dicing saw 13 is scanned. The semiconductor device is completed by cutting and separating into individual semiconductor devices.

このように、先に本願出願人が提案した半導体装置の製造方法に基づき、半導体基板表面を樹脂封止するときに、予め形成された位置合わせマークを露出するパターンニングを行うことで、位置合わせ精度が格段に向上した。なお、位置合わせマークの形成は、電子回路、あるいは配線と同時に形成するため、コストアップを招くことはない。また、半導体基板表面の樹脂封止工程は、印刷法により行われるため、特別な装置、追加工程を必要とすることがなく、低コストの半導体装置の製造方法を提供することができる。   Thus, based on the semiconductor device manufacturing method previously proposed by the applicant of the present application, when the semiconductor substrate surface is resin-sealed, by performing patterning that exposes a pre-formed alignment mark, alignment is performed. The accuracy has been greatly improved. The alignment mark is formed at the same time as the electronic circuit or the wiring, so that the cost is not increased. In addition, since the resin sealing process on the surface of the semiconductor substrate is performed by a printing method, a special apparatus and an additional process are not required, and a low-cost manufacturing method of a semiconductor device can be provided.

本発明の実施例の製造工程を示す説明図である。It is explanatory drawing which shows the manufacturing process of the Example of this invention. 本発明の実施例の製造工程を示す説明図である。It is explanatory drawing which shows the manufacturing process of the Example of this invention. 本発明の実施例の製造工程を示す説明図である。It is explanatory drawing which shows the manufacturing process of the Example of this invention. 本発明の実施例の製造工程を示す説明図である。It is explanatory drawing which shows the manufacturing process of the Example of this invention. 本発明の実施例の製造工程を示す説明図である。It is explanatory drawing which shows the manufacturing process of the Example of this invention. 本発明の実施例の製造工程を示す説明図である。It is explanatory drawing which shows the manufacturing process of the Example of this invention. 本発明の実施例の製造工程を示す説明図である。It is explanatory drawing which shows the manufacturing process of the Example of this invention. 本発明の実施例の製造工程を示す説明図である。It is explanatory drawing which shows the manufacturing process of the Example of this invention. 本発明の実施例の製造工程を示す説明図である。It is explanatory drawing which shows the manufacturing process of the Example of this invention. 本発明の実施例の製造工程を示す説明図である。It is explanatory drawing which shows the manufacturing process of the Example of this invention. 本発明の実施例の製造工程を示す説明図である。It is explanatory drawing which shows the manufacturing process of the Example of this invention. 本発明の実施例における半導体基板上の樹脂形成領域を示した説明図である。It is explanatory drawing which showed the resin formation area on the semiconductor substrate in the Example of this invention. 従来の半導体装置における構造の一例を示す説明図である。It is explanatory drawing which shows an example of the structure in the conventional semiconductor device. 従来の半導体装置における別の構造の一例を示す説明図である。It is explanatory drawing which shows an example of another structure in the conventional semiconductor device. 従来の半導体基板上の樹脂形成領域の一例を示す説明図である。It is explanatory drawing which shows an example of the resin formation area | region on the conventional semiconductor substrate.

符号の説明Explanation of symbols

１ 半導体基板、２ 電極端子、３ 絶縁膜、４ 配線、４ａ 電極パッド、５ 被覆層、６ バリアメタル層、７ ハンダコア、８ 樹脂層、９ 裏面樹脂層、１０ ハンダバンプ、１２ ダイシングテープ、１３ ダイシングソー、１４ 樹脂開口領域、１６ 位置合わせマーク、１７ 樹脂補強部、１８ 半導体チップ形成領域、２１ 半導体チップ、２１ａ 電極パッド、２１ｂ ハンダバンプ、２４ 金線、２５ 被覆樹脂、２６ インターポーザ、２７ 外部電極、２８ 樹脂層   DESCRIPTION OF SYMBOLS 1 Semiconductor substrate, 2 Electrode terminal, 3 Insulating film, 4 Wiring, 4a Electrode pad, 5 Cover layer, 6 Barrier metal layer, 7 Solder core, 8 Resin layer, 9 Back surface resin layer, 10 Solder bump, 12 Dicing tape, 13 Dicing saw , 14 Resin opening region, 16 Alignment mark, 17 Resin reinforcement part, 18 Semiconductor chip formation region, 21 Semiconductor chip, 21a Electrode pad, 21b Solder bump, 24 Gold wire, 25 Coating resin, 26 Interposer, 27 External electrode, 28 Resin layer

Claims (1)

半導体基板の一主面に、電子回路を形成し、該電子回路の電極端子を前記半導体基板上で配線を介して分散することによる再配置させた電極パッドを形成すると共に、前記半導体基板一主面の外周部近傍に、前記半導体基板を切断分離する際、切断位置の基準となる位置合わせマークを形成する工程と、前記電極パッド上にハンダコアを形成する工程と、前記ハンダコアを形成した前記半導体基板の一主面を印刷法により樹脂封止する工程と、該封止樹脂及び前記ハンダコアを研磨し、前記ハンダコアの一部を露出させる工程と、前記半導体基板の別の一主面を研磨した後、該別の一主面に樹脂層を形成する工程と、前記露出したハンダコア上にハンダバンプを形成する工程と、前記露出する位置合わせマークを基準として前記半導体基板を切断分離し、個々の半導体装置に分割する工程とを備えた半導体装置の製造方法において、
前記ハンダコアを形成した前記半導体基板の一主面を印刷法により樹脂封止する際、前記半導体基板の外周部に向かって開口する凹部により前記位置合わせマークを含む領域を露出するように開口部を形成すると共に、前記位置合わせマークより前記半導体基板の外周方向の領域に樹脂補強部を形成する工程を含むことを特徴とする半導体装置の製造方法。 An electronic circuit is formed on one main surface of the semiconductor substrate, and electrode pads rearranged by dispersing electrode terminals of the electronic circuit through wiring on the semiconductor substrate are formed, and the semiconductor substrate main in the vicinity of the outer periphery of the surface, the time of cutting and separating the semiconductor substrate, forming a positioning mark as a reference for the cutting position, and forming a solder core on the electrode pad, the semiconductor forming the solder core A step of resin-sealing one main surface of the substrate by a printing method, a step of polishing the sealing resin and the solder core to expose a part of the solder core, and another main surface of the semiconductor substrate were polished A step of forming a resin layer on the other main surface; a step of forming a solder bump on the exposed solder core; and the semiconductor substrate on the basis of the exposed alignment mark. And the cross-sectional separated, in the manufacturing method of a semiconductor device having a step of dividing into individual semiconductor devices,
When resin-sealing one main surface of the semiconductor substrate on which the solder core is formed by a printing method, an opening is formed so that a region including the alignment mark is exposed by a recess opening toward the outer periphery of the semiconductor substrate. A method for manufacturing a semiconductor device, comprising: forming a resin reinforcing portion in a region in an outer peripheral direction of the semiconductor substrate from the alignment mark .
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