JPH02299251A - Manufacture of semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To eliminate the shift of laser beam irradiation for relieving redundancy and to contrive the improvement of a yield by a method wherein a wafer alignment is performed using second wafer alignment marks formed by a mask for fuse formation use. CONSTITUTION:A mask alignment in every manufacturing process is performed on a wafer 1 using first wafer alignment marks 2 to 4 which are used as a reference. In a fuse formation process, second wafer alignment marks are provided on a mask for fuse formation use and the second wafer alignment marks 5 to 7 consisting of a material identical with a fuse material are formed on the wafer 1 simultaneously with the formation of a fuse at the time of formation of the fuse. Moreover, the wafer 1 having a relivable redundancy item is made to perform a water alignment by a laser processing device using the marks 5 to 7 and the fuse is cut. Thereby, the shift of laser beam irradiation can be eliminated and a yield can be improved.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a method for manufacturing a semiconductor integrated circuit in which a semiconductor wafer is processed with high precision positioning and laser beam irradiation, and in particular relates to a method for manufacturing a semiconductor integrated circuit, in which a semiconductor wafer is processed with high precision positioning and laser beam irradiation. This relates to redundancy relief technology.

2. Description of the Related Art Semiconductor integrated circuits, especially semiconductor memories, are becoming larger and smaller year by year. Therefore, dust and defects
The resulting decline in semiconductor memory yields has become a major problem. As a method to solve this problem, there is a redundancy relief technique. This technology is.

A redundant circuit is formed in the semiconductor memory at intervals of τ, and the wafer is inspected at t.
When a defective memory of a defective chip is detected from C, the fuse in the redundant circuit of the defective chip is cut by laser processing equipment using the data lζ at the time of wafer inspection, and the defective memory and the spare memory of the redundant circuit are separated. This is a replacement technology, and as described above, defective chips are converted into good products and rescued. In this redundancy repair technique, it is necessary to determine the position of a fuse in a redundant circuit in a semiconductor integrated circuit with high precision, and then cut the fuse by laser beam irradiation. In the conventional fuse cutting method, first, the wafer 11 is aligned using wafer alignment marks 12, 13, and 14 that serve as the bases on the semiconductor integrated circuit wafer 11 shown in FIG. That is, in the laser processing apparatus, the wafer alignment marks 12 and 13 are used to level the wafer 11 in the horizontal direction and determine the X coordinate of the wafer 11, and then the wafer alignment marks 1
2) The X coordinate of the wafer 110) is determined using the wafer alignment marks 4 which are perpendicular to the horizontal direction of wafers 110 and 13. In this way 1. τThe determined X coordinate of the wafer 11 and
From the coordinates, calculate the fuse position of the chip where the fuse cutting process for redundant relief processing is to be performed, and move wafer 1 to the uncalculated wafer position. In other words, the wafer 11 is moved so that the fuse (not shown) to be cut in the lower tube ζ tip is located at the position where the laser beam is irradiated [1, then the laser beam is irradiated to cut the fuse. ing.

Problems to be Solved by the Invention However, in the conventional manufacturing method lzet fuse cutting, the fuse position of the wafer 1 and the laser beam irradiation position t
However, there was a problem in that a large overlay error occurred. In other words, the wafer alignment marks 32, 1 on the wafer 11, which are usually not formed in the selective oxide film separation process.
3 and 14, mask alignment for each process is performed. First, during the process of fuse formation, wafer alignment marks 12, 13, and 14 are formed.

An alignment error E occurs in the overlap with the fuse forming mask. Next, in the redundancy relief process, an alignment error E2 occurs when wafer alignment is performed using the wafer alignment marks 12, 13, and 14 on the wafer 11 formed in the selective oxide film separation process. Therefore, the total error E in wafer alignment between the laser beam irradiation position and the fuse position to be cut, which occurs when cutting the fuse, is
T is mainly ET■E1+E.

becomes. Usually, these alignment errors E1. E2 is approximately 0.3 μm to 0.5 μm, and other errors are so small as to be ignored. Therefore, the total error in wafer alignment E
T is 0.6 μm to 1.0 μm. As above.

There has been a problem in that trench formation by redundant relief of semiconductor integrated circuits cannot be performed with high precision, and laser beam irradiation irregularities occur, resulting in a decrease in yield.

The present invention solves the above problems.6. It is an object of the present invention to provide a method for manufacturing a semiconductor integrated circuit that prevents the irradiation of a laser beam from occurring when cutting a fuse in a redundant circuit and improves the yield.

Means for Solving the Problems In order to solve the above problems, 1. The method for manufacturing a semiconductor integrated circuit of the present invention includes a fuse formation mask +c second Cn wafer alignment mark, in addition to a first wafer alignment mark serving as a reference. a fuse forming step of forming a second wafer alignment mark made of the same material as the fuse material at the same time as forming the fuse on the wafer; The method includes a cutting process in which wafer alignment is performed using a second wafer alignment mark, and the fuse is cut using laser light 1C.

Effects of the above-mentioned manufacturing method Due to the above manufacturing method, by performing τ wafer alignment using the second wafer alignment mark in the cutting process E, the wafer alignment error between this second wafer alignment mark and the laser beam WA irradiation position is reduced. However, the error between the fuse position 11i77 cut by the laser beam and the laser beam irradiation position is 1ζ. Therefore, the second
The alignment error between the first wafer alignment mark on the wafer and the fuse formation mask during the fuse formation process for forming the wafer alignment mark of 1 is ignored, and the deviation in laser beam irradiation during fuse cutting is reduced.

Example Hereinafter, one embodiment of the present invention will be described based on the drawings.

FIG. 1 is a plan view of a wafer on which iζ is formed after the fuse forming step using the method of manufacturing a semiconductor integrated circuit of the present invention.

On the semiconductor integrated circuit wafer 1, mask alignment is performed for each manufacturing process using the first wafer alignment mark 2.3.4 as a reference, and a large number of semiconductor integrated circuit chips are aligned over the entire surface of the wafer 1. 8 manufacturing steps proceed. In the fuse formation step, a second wafer alignment mark is provided on the fuse formation mask, and when forming a fuse (not shown), a second wafer alignment mark made of the same material as the fuse is simultaneously formed. Marks 5.6.7 are formed on the wafer 1. After this.

In the inspection process EC of semiconductor integrated circuits, good products, defective products,
Inspect and select the redundant salvageable amount. Then, for the wafer l that has a redundant salvageable amount, the laser processing device performs wafer alignment using the second wafer alignment mark 5, 617, and cuts the fuse at the position calculated from the data at the time of inspection.

That is, in the laser processing apparatus, first, the second wafer alignment mark 5.6 is used to level the wafer 1 in the horizontal direction and the X coordinate of the wafer l is determined, and then the second wafer alignment mark 5. . Using the wafer alignment mark 7 of @2 perpendicular to the horizontal direction of 6, determine the X coordinate of wafer 1, and from the X coordinate of wafer l and the The fuse position of the chip 8 where the fuse cutting process is to be performed is calculated, the wafer 1 is moved to the calculated wafer position, and the fuse is cut.

In this way, in the fuse cutting process, by performing wafer alignment using the second wafer alignment mark 5.6.7, the first wafer alignment mark 2.3.4 and the fuse forming mask can be aligned. The alignment error between the fuse position and the laser beam irradiation position can be suppressed to the alignment error between the second wafer alignment mark 5°6.7 and the laser beam irradiation position. It is possible to eliminate the irradiation gap and improve the yield.

In the embodiment shown in FIG. 1, the X coordinate of the second wafer alignment mark 5.6 is different from the X coordinate of the first wafer alignment mark 2.3, which is shown as 7, but they may be the same. Second wafer alignment mark 5.
The X coordinate of 6 is the first wafer alignment mark 2, 3
If the X coordinate is the same as the X coordinate of the second wafer 1, the X coordinate of the second wafer 1 alignment mark 5.degree. Also, if the X coordinate of the second wafer alignment mark 5.6 is the same as the X coordinate of the first wafer alignment mark 2.3, the second wafer alignment mark 5 overlaps with the first wafer alignment mark 2. Also, the second wafer alignment mark 6 must not overlap the first wafer alignment mark 3. Similarly, although the X coordinate of the second wafer alignment mark 7 is shown to be different from the X coordinate of the first wafer alignment mark 4, it may be the same. 1 alignment mark 7 and first wafer alignment mark 4 must not overlap. The X coordinate of the second wafer alignment mark 7 is the same as the X coordinate of the first wafer alignment mark 4.
If the coordinates are the same, the extent to which wafer alignment is possible (
(approximately 500 μm or more) second wafer alignment mark 7
The X coordinates of the two must be far apart. In either case, the respective wafer alignment marks must be arranged so as not to adversely affect each other.

Effects of the Invention As described above, according to the present invention, the fuse forming mask l
Since wafer alignment is performed using the second wafer alignment mark formed in this manner, the deviation between the cut-out fuse and the laser beam irradiation position should be within about 0.5 μm of the one-time wafer alignment error. This makes it possible to manufacture semiconductor integrated circuits by redundancy relief with high precision, eliminate laser beam irradiation deviations, and improve yield.

[Brief explanation of drawings]

FIG. 1 is a plan view of a wafer that is an embodiment of the present invention and is formed after a fuse forming step using the semiconductor integrated circuit manufacturing method of the present invention. FIG. 2 is a plan view of a wafer formed using a conventional semiconductor integrated circuit manufacturing method. 1... Semiconductor integrated circuit wafer, 2.3.4... First
5.6.7...Second wafer alignment mark, 8...Semiconductor integrated circuit chip.

Claims (1)

[Claims] 1. Separately from the first wafer alignment mark that serves as a reference, a second wafer alignment mark is provided on the fuse formation mask, wafer alignment is performed using the first wafer alignment mark, and fuse formation is performed on the wafer. At the same time, a second fuse made of the same material as the fuse material
A method for manufacturing a semiconductor integrated circuit, comprising: a fuse forming step of forming a wafer alignment mark; and a cutting step of performing wafer alignment using the second wafer alignment mark and cutting the fuse with a laser beam. .