JP2807028B2 - Laser repair method - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a laser repair method for repairing a defective cell by cutting a link in a memory chip of a semiconductor wafer on which a plurality of memory chips are formed with a laser.

[Prior Art] In order to improve the yield in the manufacture of semiconductor memory, when forming a plurality of memory chips on a semiconductor wafer, a plurality of redundant cells are formed simultaneously for each memory chip, and each memory chip is formed. Is tested, and when a defective cell is found, the link on the chip is cut with a laser so that the address given to the defective cell is given to the redundant cell, and the defective cell is relieved.

The laser repair device for this has the configuration shown in FIG. A stage 12 is mounted on a stage driving mechanism 11, and a semiconductor wafer 13 is disposed on the stage 12. The positioning control circuit 15 is set and controlled by the control computer 14, and the positioning control circuit 15 refers to the position of the stage 12 detected by the stage position detection circuit 16 so as to reach the set position through the stage driving circuit 17 through the stage driving mechanism 17. The stage 11 is controlled to move and control the stage 12. The laser 18 is controlled by the control computer 14, and the laser light 19 from the laser 18 is emitted.
Is reflected by the reflecting mirror 21 and is incident on the semiconductor wafer 13,
The reflected light is detected by a laser reflected light detector 22, and the output of the laser reflected light detector 22 is supplied to a mark detection circuit 23,
Light reflected from alignment marks formed at positions corresponding to the four corners of each memory chip on the semiconductor wafer 13 is detected by a mark detection circuit 23, and the detection output is supplied to a control computer 14. After controlling the stage 12 so that the laser light is incident on the position of the link to be cut based on the alignment mark, the power of the laser light is instantaneously increased to cut the link.

The position of the link to be cut often deviates from the design position due to distortion such as warpage or distortion of the semiconductor wafer. Therefore, each memory chip (hereinafter simply referred to as chip)
For each of the three positions, the position of the three alignment marks is detected, the deviation between the detected position and the original position (design position) is obtained, a correction coefficient is calculated from these deviations, and this correction coefficient is used. The design position of the link to be cut is corrected, and the corrected position is irradiated with laser light.

[Problem to be Solved by the Invention] As described above, in the conventional laser repair method, since three alignment marks are detected for each chip and the correction coefficient is obtained, the detection of the alignment mark is performed for each chip. Must be performed three times, and this mark detection takes time,
Laser repair could not be performed efficiently.

According to the present invention, the positions of at least three alignment marks are detected for at least two selected chips on a semiconductor wafer, and the positions of the detected alignment marks are detected. Calculates the correction coefficients for correcting the deviation from the design position for each of the selected chips, and uses these correction coefficients to determine the position of at least one alignment mark with respect to the chip having the link to be cut. Calculating, detecting the position of at least one other alignment mark of the chip, and correcting a deviation of the calculated alignment mark position and the detected alignment mark position from a design position with respect to the chip. Calculate the correction coefficient to be cut, use the correction coefficient to correct the position of the link to be cut, and The link is cut by irradiating the position with laser.

"Embodiment" FIG. 1 shows a flow of processing in an embodiment of the method of the present invention. First, the semiconductor wafer 13 is placed on the stage 12 (S ₁ ). Next, as shown in FIG. 2, the detection of the positions of the three alignment marks of the selected chip A on the semiconductor wafer 13 is executed (S ₂ ). Using the position of the alignment mark the detected (referred to as a combined correction coefficient) correction coefficient for correcting the deviation from a design position for the chip A to calculate the a to f (S _3). This calculation may be performed in the same manner as a conventionally performed method. Correction position (X, Y) for design position (x, y)
Is given by, for example, the following equation as a distortion correction equation: X = a + bx + cy Y = d + ex + fy (1) When each position of the detected alignment mark is (X ₁ , Y ₁ ), (X ₂ , Y ₂ ), (X X ₃ , Y ₃ ), and when their design values (positions) are (x ₁ , y ₁ ), (x ₂ , y ₂ ), and (x ₃ , y ₃ ), these are substituted into equation (1). And From these six equations, the unknown value numbers a to f, which are correction coefficients, are calculated. When the chip has no distortion, a = c = d = e = 0, b
= F = 1, the design value (x, y) and the detected (measured) value (X,
Y) matches.

In the processing operation of FIG. 1, perform the following detection of the position of the three alignment marks other selected chip B on the semiconductor wafer 13 (S _4), the chip B with the detected mark position Similarly to calculate a correction coefficient a~f combined for (S _5). Further performs the detection of the positions of the three alignment marks other selected chip C on the semiconductor wafer 13 (S _6), similarly a correction coefficient a~f combined for chip C by using the detected mark position calculated to (S _7). Note that these chips A to C are selected on the semiconductor wafer 13 as far as possible from each other.

The respective correction coefficients a to c of these selected chips A to C
Using f, the position of at least one alignment mark relative to any other chip on semiconductor wafer 13 is calculated.
This alignment mark is called a virtual mark. Therefore, the first
In the figure, a correction coefficient function using each position on the semiconductor wafer 13 as a variable is obtained using the respective adjustment correction coefficients a to f of the chips A to C, that is, the correction coefficients a to f on the semiconductor wafer 13 are obtained.
Is calculated (S ₈ ). This function is obtained, for example, as follows. When the coordinates of the center of the semiconductor wafer 13 of the chip _{A (X WA, Y WA)} , a in combined in the correction coefficient calculated in step S ₃ for chip A and a _A, a correction coefficient function with the quadratic function , _{A A} = a ₀ + a ₁ X _WA + a ₂ (X _WA ) ² ... (3), and similarly, the center coordinates (X _WB ,
Y _WB ) (X _WC , Y _WC ) and a in the previously obtained matching correction coefficient
When a _B and a _C are set, the following formula is made.

from _{a B = a 0 + a 1} X WB + a 2 (X WB) 2 ... (4) a C = a 0 + a 1 X WC + a 2 (X WC) 2 ... (5) These (3) - (5) , Unknowns a ₀ , a ₁ , a ₂ are obtained. Similarly, coefficients b _{0 to} b ₂ , c _{0 to} c ₂ , d _{0 of the} correction coefficient function
~d _2, determine the _{e 0 ~e 2, f 0 ~f} 2.

Next, an arbitrary chip (recognition chip) on the semiconductor wafer 13
When the center of n is set to coordinates (X _Wn , Y _Wn ) on the semiconductor wafer 13 as shown in FIG. 3, the alignment correction coefficient a _{n of the} chip _n
Ff _{n is obtained} by the following equation (S ₉ ).

 a_n= A₀+ A₁X_Wn+ A_Two(X_Wn)² … (6) b_n= B₀+ B₁X_Wn+ B_Two(X_Wn)² … (7) c_n= C₀+ C₁X_Wn+ C_Two(X_Wn)² … (8) d_n= D₀+ D₁Y_Wn+ D_Two(Y_Wn)² … (9) e_n= E₀+ E₁Y_Wn+ E_Two(Y_Wn)² … (10) f_n= F₀+ F₁Y_Wn+ F_Two(Y_Wn)² ... (11) The alignment correction section for the chip n thus obtained
Number a_n~ F_nIs used to calculate a virtual mark of the chip n.
(S_Ten). That is, the alignment mark of chip n,
Each design position of (X_Wn2, Y_Wn2), (X_Wn3, Y_Wn3)
And the coefficients a to f in the equation (1)_TenA determined by_n~ F
_nAs the position of the virtual mark (X , Y ) Is X = A_n+ B_nX_Wn2+ C_nY_Wn2 … (12) Y = D_n+ E_nX_Wn2+ F_nY_Wn2 … (13), and the position of the virtual mark (X , Y )
Is also found.

 Next, an alignment mark different from the virtual mark of chip n is used.
Position (X , Y ) Is detected by laser irradiation
(S₁₁). Calculated value of each position of these virtual marks
(X , Y ), (X , Y ) And the position of the alignment mark
Measured value (X , Y ) And these alignment marks,
Using each of the design values of the position n
Find the numbers a to f (S₁₂). This is similar to equation (2)
Ask. That is, each position of the alignment mark,,
The design values of (x₁, y₁), (X_Two, y_Two), (X_Three, y_Three)
WhenThen, unknown numbers a to f of these equations are obtained. This switch
Using the alignment correction coefficients a to f for the chip n, the chip
Correct the design value of the position of the link to be cut in n
And irradiate the corrected position with laser light to establish a link.
Disconnect (S₁₃). This link disconnection is performed on one chip n
One or more operations are performed. Next, the relief on the semiconductor wafer 13
Check if there are no more chips to complete
(S₁₄), If not, step S₉Move on to the other
Perform laser cutting on the chip in the same way
If there are no more chips, the process ends.

Although two virtual marks have been calculated in the above description, the number may be one and two actual measurements of the alignment mark may be performed. Also, in the above description, the alignment correction coefficients a to
Although f was obtained, it is also possible to perform correction with higher accuracy using the four alignment marks.
One to three are virtual marks. In the above description, the correction coefficient function is a quadratic function, but may be a linear function. In this case, the coefficients are a ₀ , a ₁ , b ₀ , b ₁ , c ₀ , c in Equations (6) to (11). _1, d _0,
Since d ₁ , e ₀ , e ₁ , f ₀ , and f ₁ , only two chips, for example, A and B, may be selected on the semiconductor wafer 13.

[Effects of the Invention] As described above, according to the present invention, the position of three or four alignment marks is actually detected for the selected two or three chips on the semiconductor wafer. With respect to the chip (i), the state of change of the alignment correction coefficient on the semiconductor wafer is obtained from the deviation between the detection position of the alignment mark and the design position of the selected chip, and the positions of one to three virtual marks are calculated from this. , From this and the position of at least one other alignment mark actually measured,
Since the alignment correction coefficient of the chip is obtained and the position of the link is corrected using this, correction can be made with relatively high accuracy, and the number of position detections of the alignment mark is equal to the number of virtual marks. Since the number of chips is reduced, the time required to detect the position of the alignment mark is significantly reduced as a whole, and laser repair can be performed efficiently.

[Brief description of the drawings]

FIG. 1 is a flowchart showing a processing flow in an embodiment of the present invention, FIG. 2 is a view showing a selected chip on a semiconductor wafer, FIG. 3 is a view showing an arbitrary chip on a semiconductor wafer, FIG. FIG. 1 is a block diagram showing a general configuration of a laser repair device.

Claims (1)

(57) [Claims] 1. A laser repair method for repairing a defective cell by cutting a link in a memory chip of a semiconductor wafer on which a plurality of memory chips are formed by a laser, wherein at least two selected memories on the semiconductor wafer are provided. For each chip, the positions of at least three alignment marks are detected. Based on the positions of the detected alignment marks, a first correction coefficient for correcting a deviation from a design position for each of the selected memory chips is respectively determined. Calculating, using these first correction factors, calculating the position of at least one alignment mark with respect to the memory chip having the link to be severed, and calculating the position of at least one other alignment mark of the memory chip. From the calculated position of the alignment mark and the position of the detected alignment mark. Calculating a second correction coefficient for correcting a deviation from a design position with respect to the memory chip, correcting the position of the link to be cut using the second correction coefficient, and irradiating the corrected position of the link with a laser beam. And disconnecting the link.