JP3313543B2 - Alignment apparatus and alignment method for exposure apparatus - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an improvement in detection accuracy of a positioning device for an exposure apparatus used in a process of manufacturing a semiconductor device such as an IC and an LSI.

[0002]

2. Description of the Related Art In recent years, with the miniaturization of circuit patterns such as LSIs, optical reduction exposure apparatuses having high resolution performance have been widely used as pattern transfer means. When exposing a device pattern of a photoresist using such an exposure apparatus, it is necessary to align the wafer with high accuracy prior to exposure. FIG. 8 is a perspective view of a light exposure apparatus, and FIG. 9 is a schematic block diagram showing a configuration of an alignment apparatus of the light exposure apparatus and an alignment signal processing system. As shown in this figure, an alignment device 3 is arranged close to a projection lens 1 and irradiates an alignment mark 6 on a semiconductor wafer (hereinafter, referred to as a wafer) 2 with an alignment light such as a HeNe laser. The alignment light reflected and diffracted by the alignment mark 6 is converted into an electric signal by a light receiver in the alignment device 3 and converted into position information as an alignment output signal by an alignment signal processing circuit 7. On the other hand, the wafer stage 11 on which the wafer 2 is mounted can be moved in the x direction / y direction by the stage driving mechanism 9. The laser interferometer 8 outputs the laser light 5
The position of the stage 11 is measured by detecting the light reflected by the mirror 4 on the wafer stage 11. The position information obtained by the laser interferometer 8 and the position information obtained by the alignment device 3 are processed by the calculation unit 10 to control the position of the wafer stage 11.

FIG. 10 shows an example of the arrangement of alignment marks 6 formed on the wafer 2 in advance. Prior to exposing the wafer 2 with an optical exposure apparatus, the wafer stage 11
Alignment mark 6 with wafer 2 mounted on top
Is measured by the alignment optical system 3. Exposure apparatuses are increasingly required to have improved pattern resolution and alignment accuracy due to the higher integration of LSIs. The alignment error occurs when the alignment mark is asymmetric due to uneven aluminum spatter or uneven resist applied on the alignment mark. In recent years, a flattening technique has been introduced, and a step of an alignment mark expressed by unevenness has been reduced, thereby causing a problem that alignment becomes impossible. As a conventional alignment detector, for example, K. Ota, N. Magome, and K. Nishi: New Align
ment Sensor for wafer Stepper, SPIE Vol.1463 Optic
al / Laser Microlithography 4, pp. 343-314 (1991) is known.

[0004] After the devices are formed, the wafer is cut for each device and separated into a plurality of semiconductor devices (chips). As shown in FIG. 4, a chip formation region 20 is arranged and formed on the wafer 2. In the chip formation region 20, marks 21 having an arbitrary shape with irregularities are formed. FIG. 5 is an enlarged plan view of one of the chip forming regions 20 arranged on the wafer. In the alignment process, some of the chip forming regions 20 are selected, and the marks 21 formed therein are used as the alignment marks 6 for performing the normal alignment process. FIG.
FIG. 2 is a system block diagram showing an alignment principle of an apparatus for detecting a diffraction light intensity from an alignment mark using laser light from a HeNe laser as alignment light. Although any process mark can be aligned to some extent and is widely used, it has a wide versatility. However, there are drawbacks in that alignment cannot be performed with a low step mark or alignment accuracy is easily affected by mark asymmetry due to uneven aluminum spatter. FIG. 12 shows that the alignment light is He.
FIG. 3 is a system block diagram illustrating an alignment principle of an apparatus that detects a phase of diffracted light from an alignment mark using a Ne laser. Since the phase of the alignment light is detected, the detection sensitivity is high, and alignment is possible even with a low step mark. However, although phase detection has high detection sensitivity, it tends to be easily affected by multiple reflections in the resist.

FIG. 13 shows the alignment principle of an apparatus that forms an alignment mark on a detector surface such as a CCD using alignment light containing a wideband frequency component such as white light. When this alignment principle is used, alignment errors due to asymmetry of the alignment marks and multiple reflections within the resist are reduced, but alignment marks with low steps tend to be difficult to align. As described above, the alignment mark has various shapes such as a low step mark, an asymmetric mark due to uneven aluminum spatter, and a mark susceptible to multiple reflection. However, it is not possible to cope with any kind of mark, and in order to solve this problem, a plurality of alignment devices having different mark detection principles have been mounted on an exposure apparatus. Further, an alignment error that affects the alignment mark due to the process can be reduced by changing the shape of the alignment mark. FIG. 14A is a plan view showing an example of an alignment mark used for the alignment processing. The alignment mark 6 has a strip shape, and an alignment waveform signal obtained by detecting the alignment mark 6 is shown in a characteristic diagram of FIG.
FIG. 14B shows the light intensity on the vertical axis and the wafer stage position on the horizontal axis.

As shown in the figure, a light intensity peak exists at a position of an alignment mark 6 formed on a wafer. FIG. 15A is a plan view in which a plurality of the alignment marks of FIG. 14A are periodically arranged. The waveform signal obtained from the alignment mark 6 is shown in the characteristic diagram of FIG. FIG. 15B shows the light intensity on the vertical axis and the wafer stage position on the horizontal axis. As shown in the figure, a light intensity peak exists at the position of the alignment mark 6 formed on the wafer. The alignment mark 6 in this figure is obtained by arranging a plurality of alignment marks 6 in FIG. 14A, and the light intensity curve has a waveform. By averaging these waveforms, alignment accuracy is improved. As described above, the alignment accuracy can be improved by selecting the alignment detector and arbitrarily selecting the shape of the alignment mark.

[0007]

As described above, it has been shown that the alignment accuracy can be improved by selecting an alignment detector and selecting the shape of an alignment mark for a wafer having undergone a predetermined process step. There was such a problem. Means for confirming that the alignment mark is affected by the process include: (1) a method of detecting an alignment signal and measuring the reproducibility of the signal;
(2) There is a method of actually performing exposure and measuring overlay accuracy. In the method (1) of detecting the alignment signal and measuring the reproducibility of the signal, the alignment waveform when the alignment mark is asymmetric has no change in the shape of the waveform signal as compared with the case where the alignment mark is not asymmetric. is there. For example, FIGS. 16 and 17 show examples in which the alignment detection position has changed due to asymmetry of the resist on which the alignment mark is applied. FIG. 16 is a sectional view showing a convex alignment mark and a characteristic diagram showing an alignment waveform signal obtained by detecting the alignment mark. This alignment mark 6
Is formed by forming a photoresist 12 on a convex portion on the surface of the wafer 2, and the photoresist 12 is formed uniformly along the convex portion.

In the characteristic diagram, the light intensity is plotted on the vertical axis, and the wafer stage position is plotted on the horizontal axis. As shown in the figure, a light intensity peak exists at the position of the alignment mark 6 formed on the wafer, and the center of the convex portion coincides with the light intensity peak. FIG. 17 is a cross-sectional view showing a convex alignment mark and a characteristic diagram showing an alignment waveform signal obtained by detecting the alignment mark. The photoresist 12 is formed on the convex portion on the surface of the wafer 2. However, the photoresist is not formed uniformly along the convex portion, and the peak of the photoresist is slightly shifted from the center of the convex portion of the wafer. In the characteristic diagram, the vertical axis indicates light intensity, and the horizontal axis indicates a wafer stage position. As shown in the figure, the peak of the light intensity at the position of the alignment mark 6 formed on the wafer does not coincide with the center of the convex portion of the wafer. That is, FIG. 16 shows a case where the mark has no asymmetry, and FIG. 17 shows a case where the mark has asymmetry. The alignment detection signal of FIG. 17 is often output with the signal waveform of FIG. 16 shifted in parallel. In this case, the detection reproducibility of the alignment detection position is the same between FIG. 16 and FIG. 17, and it is not possible to determine the alignment accuracy based on the asymmetry of the mark shape.

The method (2) of actually performing exposure and measuring overlay accuracy is to prepare wafers having different alignment mark shapes, perform actual exposure, and detect an optimal alignment for an arbitrary wafer process. The method and the optimal alignment mark are selected. However, in this method, exposure must be performed on each process wafer, each alignment detector, and each alignment mark shape using the alignment mark, which is complicated. For example, the alignment process is performed about 20 times for one wafer, and if there are three types of alignment detectors and ten types of alignment mark irregularities or patterns as described above, for one wafer, for example, , 600 times, the exposure accuracy cannot be determined. The present invention has been made under such circumstances, and it is possible to easily select an optimal alignment detector for an arbitrary process wafer without actually performing exposure processing, and to easily perform positioning from an alignment mark. It is intended to provide a way.

[0010]

According to the present invention, there is provided an exposure apparatus having an alignment detector for aligning an alignment mark on a wafer formed in an arbitrary wafer processing step. And a systematic error is calculated from the position error of the alignment mark position, and the alignment accuracy is obtained by a residual amount obtained by removing the systematic error from the position error of the alignment mark position. In addition, a residual amount is obtained by using a plurality of alignment detectors having different position detection principles, and an alignment detector having the smallest residual amount is selected as an optimal device for the wafer.

That is, an alignment apparatus for an exposure apparatus according to the present invention processes an alignment detector for aligning an alignment mark position on a semiconductor wafer to a predetermined position, and processes an alignment output signal output from the alignment detector. An alignment signal processing unit, the semiconductor wafer is mounted, a wafer stage driven by a stage driving unit, a stage position measurement unit that measures the position of the wafer stage, and an output signal obtained from the alignment signal processing unit An arithmetic unit for performing an arithmetic operation for controlling the position of the wafer stage by comparing an output signal obtained from the stage position measuring unit, and detecting a plurality of alignment mark positions on the semiconductor wafer to obtain a position error thereof; The position error of the detected alignment mark position Calculated systematic errors, the first characterized in that it comprises means for determining the alignment accuracy by the residual amount excluding systematic error from the position error. Further, a plurality of alignment detectors each having a different position detection principle for aligning the alignment mark position on the semiconductor wafer to a desired position, and an alignment signal processing unit for processing an alignment output signal output from the alignment detector, The semiconductor wafer is mounted,
A wafer stage driven by a stage driving unit, a stage position measuring unit that measures the position of the wafer stage, and an output signal obtained from the alignment signal processing unit and an output signal obtained from the stage position measuring unit. An arithmetic unit that performs an arithmetic operation to control the position of the wafer stage by comparison, and using each of the alignment detectors, detects a plurality of alignment mark positions on the semiconductor wafer and obtains position errors thereof. System error from the position error of the alignment mark position
A means for obtaining alignment accuracy by a residual amount obtained by removing a system error from the position error; anda means for selecting an alignment detector having the smallest residual amount from the plurality of alignment detectors. The second feature is that the alignment is performed using the alignment detector.

An alignment mark having a different shape is arranged on the surface of the semiconductor wafer, a plurality of alignment mark positions on the semiconductor wafer are detected by the alignment detector, and positional errors thereof are obtained. Means may be provided for obtaining a systematic error from the position error and selecting an alignment mark having a shape with the smallest residual amount obtained by removing the systematic error from the position error. Further, the alignment method of the present invention is a step of aligning the alignment mark position on the semiconductor wafer to a predetermined position using an alignment detector,
Processing an alignment output signal output from the alignment detector by an alignment signal processing unit; driving a wafer stage on which the semiconductor wafer is mounted by a stage driving unit; and Measuring the position of, and controlling the position of the stage by comparing the output signal obtained from the alignment signal processing unit and the output signal obtained from the stage position measurement unit in a calculation unit, Detecting a plurality of alignment mark positions on the semiconductor wafer to determine their position errors, obtaining a systematic error from the detected position errors of the alignment mark positions, and performing alignment by a residual amount obtained by removing the systematic errors from the position errors. And the step of seeking accuracy And butterflies.

[0013]

According to the present invention, the alignment accuracy can be easily obtained for an arbitrary process wafer without actually performing exposure from the residual amount obtained by removing the systematic error from the position error of the alignment mark position. Further, by selecting an alignment apparatus having the smallest residual amount, an optimum alignment detector can be easily selected.

[0014]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a flowchart illustrating a process of the positioning apparatus for an exposure apparatus according to the present invention. 2. Description of the Related Art In the manufacture of semiconductor devices, a photoresist is required, and the step of patterning the photoresist is more than 20 times on one wafer.
When the photoresist on the wafer is exposed and developed, a positional error occurs on the wafer. 8 and 9 are a perspective view and a schematic cross-sectional view of an exposure apparatus having an alignment detector. FIGS. 11 to 13 show an example of an exposure apparatus provided with an alignment detector used in the present invention. The alignment detectors have different principle of position detection. The exposure apparatus shown in FIG. 11 can perform alignment to some extent even with an arbitrary process mark, and can perform alignment with wide versatility. However, in the case where alignment cannot be performed with a low step mark or alignment accuracy is low due to unevenness of mark due to uneven aluminum spatter. There are drawbacks that are easily affected. The exposure apparatus in FIG. 12 can perform alignment even on a low step mark having a concave portion or a convex portion. But,
Although phase detection has high detection sensitivity, it tends to be easily affected by multiple reflections in the resist.

FIG. 13 shows that alignment errors due to asymmetry of the alignment marks and multiple reflections in the resist are reduced, but alignment marks with low steps tend to be difficult to align. Such a plurality of alignment detectors cannot deal with any kind of mark, and it is necessary to mount a plurality of alignment devices having different mark detection principles on an exposure apparatus. Various causes can be considered for the position error of the wafer as shown in FIGS. 2 and 3 are plan views of the wafer showing the causes of errors in the alignment marks. FIG. 2 shows a linear error, and FIG. 3 shows a random error. FIG.
(A) is a linear error in which the alignment mark 6 is shifted in parallel on the wafer 2, and a mark detection error on the wafer is represented by (αx, αy). FIG. 2 (b)
Is a linear error formed by rotating the alignment mark 6 on the wafer 2, and a mark detection error on the wafer is represented by (θc). FIG. 2C shows a linear error in which the alignment mark 6 is formed on the wafer 2 due to a change in magnification depending on the position in the wafer 2. The mark detection error on the wafer is represented by (Mx, My). It is.

FIG. 2D shows a linear error in which the alignment marks 6 are formed orthogonal to each other on the wafer 2, and the mark detection error on the wafer is represented by (θo). FIG. 3 shows randomly generated random errors of the alignment marks 6 formed on the wafer 2. As described above, the position error of the alignment mark detected by the alignment apparatus in the exposure apparatus can be separated into a linear error (parallel shift error, rotation, magnification, orthogonality) and a random error. This linear error can be corrected by moving the exposure apparatus (by moving the wafer stage 11 as shown in FIG. 10). If the difference between the designed mark position (x, y) and the mark position obtained by the measurement is (dx, dy), the mark detection position error on the wafer can be expressed by the following equation. dx = αx− (θc + θo) · y + Mx · x + Sx dy = αy + θc · x + My · y + Sy (1) where (αx, αy) is a parallel shift error coefficient in the x and y directions, and (Mx, My) is a magnification error. Coefficient, θc is an error coefficient in the rotation direction, θo is an orthogonality error coefficient, (Sx, Sy
) Represents the remaining random error.

These linear error coefficients (αx, αy, Mx
, My, θc, θo) are obtained by the arithmetic unit 10 using the least squares method as described above. Here, the linear error coefficient is a systematic error, and the residual amount obtained by removing the systematic error from the mark position is a random error. In the present invention, the alignment accuracy is obtained from this error. In general, the mark position on the design (x, y) and, when the difference dx between the mark position obtained by the measurement obtained by the least squares method, dx = a0 + a1 x + a2 y + a3 x 2 + a4 y 2 + a5 xy + a6 x 3 + a7 y n is represented by the following equation of ^{3 + a8 x 2 y + a9} xy 2 + ··· (2). In the n-th order equation shown in the equation (2), in the above embodiment, up to the first order coefficient is regarded as a systematic error,
Although the residual equal to or smaller than the second-order coefficient is used as the residual, it is also possible to use the systematic error up to the second-order, third-order and higher-order components.

The residual at this time is a higher-order component than the higher-order component. For example, if coefficients up to the (n-1) th order are systematic errors, the residual is an nth order coefficient. If the systematic error includes even higher-order components, the alignment accuracy will increase accordingly. However, if the mark position error is the n-th order expression shown in the expression (2),
Since the alignment accuracy is proportional to n ^−1/2 , the change in the alignment accuracy decreases as n increases. Therefore, it is efficient to set n optimally. Next, a method for selecting an alignment detector and an alignment mark according to the present invention will be described with reference to FIGS. FIG. 1 is a flowchart for implementing the present invention, FIG. 4 is a plan view of a wafer to be subjected to an exposure process,
FIG. 5 is an enlarged plan view of a chip formation region formed on the wafer.

According to the present invention, in an exposure apparatus used for semiconductor manufacturing, a plurality of alignment mark positions on a wafer are detected, a systematic error is determined from the detected alignment mark positions, and a systematic error is removed from the alignment mark positions. It is characterized in that the alignment accuracy is obtained from the residual amount. In this embodiment, a plurality of alignment marks are selected for a wafer. The wafer 2 shown in FIG. 4 has a plurality of chip forming regions 20.
In the chip formation region 20 shown in FIG. 5, a mark 21 having a uniform pattern is formed in any region, and the mark formation region is appropriately selected and the mark 21 is used as the alignment mark 6. Optimum values are selected for the number of chip forming regions 20 to be selected and the arrangement in the wafer. Using a plurality of alignment detectors having different position detection principles for the wafer having the plurality of types of alignment marks, an optimal alignment detector and an optimal alignment mark for the wafer are selected by the following procedure. Thereafter, an exposure apparatus is applied to this wafer and subsequent wafers, and at this time, the selected alignment detector and alignment mark are used for alignment processing.

Usually, the same processing is performed for each lot (about 24 to 25 wafers). Then, select the alignment detector and the alignment mark at the first sheet,
For the second and subsequent sheets, the alignment detector and the alignment mark determined and selected on the first sheet are used. The figure is a flow chart until an alignment detector and an alignment mark are selected. First, a predetermined alignment detector is specified from a plurality of alignment detectors, and a predetermined alignment mark is specified from a plurality of alignment marks formed on the first wafer (a). The alignment is executed using the specified alignment detector, and the alignment mark position X (x, y) is measured (b).
Next, the arithmetic unit 10 (see FIG. 9) uses the equation (1) to calculate the linear error coefficient A (αx, αy, Mx, My, θc, θo).
) Is obtained (c). Next, a random component S (Sx, Sy) is obtained from the actually measured alignment mark position X by using the above equation (1) (d).

Next, it is determined whether or not alignment is to be performed with another alignment detector and another alignment mark formed on the wafer (e), and alignment is performed with another alignment detector and another alignment mark (a). Return to When the alignment is completed using all the alignment detectors and alignment marks prepared at the end, the alignment detector and the alignment mark having the smallest random component S are selected and used in the subsequent wafer exposure process (f). In the actual exposure, when entering the exposure step, the present invention is applied using one or more wafers in advance, and an optimal alignment detector and alignment mark are selected. Next, referring to FIG. 6, an alignment mark having an optimum shape for the alignment detector is selected from alignment marks having different shapes formed and arranged on the wafer by the exposure apparatus of the present invention. The present invention, when exposing a wafer, detects a plurality of alignment mark positions on the wafer, obtains a systematic error from the detected alignment mark position, by the residual amount excluding the systematic error from the alignment mark position It seeks alignment accuracy.

The wafer 2 shown in FIG. 4 has a plurality of chip forming regions 20 and is provided with a plurality of chip forming regions 20 shown in FIG.
In 0, a mark 21 having a uniform pattern is formed in any region. Then, a chip formation region is appropriately selected, and the mark 21 is used as the alignment mark 6. Optimum values are selected for the number of chip forming regions 20 to be selected and the arrangement in the wafer. Here, for a wafer provided with a plurality of alignment marks having different shapes, a plurality of alignment detectors having different position detection principles are used to select an optimal alignment mark for the wafer according to the flowchart shown in FIG. In the figure, the first mark 61
And a second mark 62. In this case, the position of the alignment mark is detected using a predetermined alignment detector, the residual amount obtained by removing the systematic error from the alignment mark position is obtained for each alignment mark shape, and the alignment mark having the smallest residual amount is determined. Choose the best one. Thereafter, an exposure apparatus is applied to this wafer and subsequent wafers, and at this time, the predetermined alignment detector and the alignment mark having the selected shape are used for alignment processing.

Next, referring to FIG. 7A, an optimal number of alignment marks for an alignment detector is selected from a plurality of marks formed on a wafer using the exposure apparatus of the present invention. The present invention, when exposing a wafer, detects a plurality of alignment mark positions on the wafer, obtains a systematic error from the detected alignment mark position, by the residual amount excluding the systematic error from the alignment mark position It seeks alignment accuracy. When determining the alignment accuracy from the detection of the alignment mark position, the position can be detected using the marks of all chip formation areas formed on the wafer as alignment marks, but alignment is performed from all the marks formed on all wafers. Finding accuracy is time-consuming and inefficient. In addition, when the number of marks is small, the alignment accuracy is reduced. In general, when the number of alignment marks is small, the alignment accuracy is low. As the number of mark alignment marks increases, the accuracy improves, but as the number increases, the degree of improvement in accuracy decreases.

Accordingly, in this case, the position of the alignment mark is detected using a predetermined alignment detector, and the number of alignment marks is changed to obtain the residual amount excluding the systematic error from the alignment mark position. The number of alignment marks smaller than a predetermined value is selected as the optimum one. In this embodiment, for example, 8 to 9 alignment marks are selected. Next, referring to FIG. 7B, an alignment mark at a wafer position optimal for an alignment detector is selected from a plurality of marks formed on a wafer by using the exposure apparatus of the present invention. For example, it may be better to select an alignment mark near the center due to process distortion. Therefore, when obtaining the alignment accuracy from the detection of the alignment mark position, the wafer is divided into several regions 63 and 64, the alignment mark position of each region is detected using a predetermined alignment detector, and the alignment mark position of each region is detected. The residual amount excluding the systematic error from is obtained, and the alignment mark in the region where the residual amount is the smallest is selected as the optimal one. Although the present invention has been described using a light exposure apparatus, the present invention can be applied to an electron beam exposure apparatus, an X-ray exposure apparatus, and any position measuring apparatus. Further, in the present invention, the principle of alignment detection is not particularly limited, and the present invention can be applied to any alignment apparatus that measures the position of a semiconductor wafer by measuring the position of an alignment mark and a pattern.

[0025]

As described above, according to the present invention, it is possible to select an alignment detector, an alignment mark, and a shape of an alignment mark which are optimal for an arbitrary wafer process.
It is not necessary to perform the exposure to evaluate the overlay accuracy, and it becomes possible only by calculating the measured alignment mark position.

[Brief description of the drawings]

FIG. 1 is a flowchart showing an embodiment of the present invention.

FIG. 2 is a plan view illustrating a linear error on a wafer surface.

FIG. 3 is a plan view illustrating a random error on a wafer surface.

FIG. 4 is a plan view of a wafer having a chip formation region.

FIG. 5 is an enlarged plan view of a chip formation region of a wafer.

FIG. 6 is an enlarged plan view of a chip formation region of a wafer.

FIG. 7 is a plan view showing an alignment mark forming region of the wafer.

FIG. 8 is a perspective view of an exposure apparatus provided with the present invention and a conventional alignment detector.

9 is a schematic block diagram illustrating a signal processing system of the exposure apparatus in FIG.

FIG. 10 is a plan view of a wafer on which alignment marks of the present invention and conventional alignment marks are arranged.

FIG. 11 is a schematic block diagram of the present invention and a conventional alignment detector.

FIG. 12 is a schematic block diagram of the present invention and a conventional alignment detector.

FIG. 13 is a schematic block diagram of the present invention and a conventional alignment detector.

FIG. 14 is a plan view of an alignment mark of the present invention and a conventional alignment mark, and a characteristic diagram showing an output signal waveform of the alignment mark.

FIG. 15 is a plan view of the alignment mark according to the present invention and the related art, and a characteristic diagram showing an output signal waveform of the alignment mark.

FIG. 16 is a cross-sectional view of a wafer having an alignment mark according to the present invention and the related art, and a characteristic diagram showing an output signal waveform of the alignment mark.

FIG. 17 is a cross-sectional view of a wafer having an alignment mark according to the present invention and the related art, and a characteristic diagram showing an output signal waveform of the alignment mark.

[Explanation of symbols]

1 Projection lens 2 Wafer 3
Alignment detector, 4 ... laser mirror, 5
... Laser interferometer optical path, 6 ... Alignment mark, 7 ... Alignment signal processing circuit, 8 ...
・ Laser interferometer, 9 ・ ・ ・ Stage drive system, 10 ・
..... Calculator, 11 ... Wafer stage, 12
... photoresist, 20 ... chip formation area,
21 ... mark, 61 ... first mark, 6
2 ... second mark, 63, 64 ... alignment mark formation area

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H01L 21/027 G03F 9/00 G05D 3/12

Claims (4)

(57) [Claims] 1. An alignment detector for aligning an alignment mark position on a semiconductor wafer to a predetermined position; an alignment signal processing unit for processing an alignment output signal output from the alignment detector; A wafer stage driven by a stage driving unit, a stage position measuring unit that measures the position of the wafer stage, an output signal obtained from the alignment signal processing unit, and an output signal obtained from the stage position measuring unit. And an arithmetic unit for performing an arithmetic operation for controlling the position of the wafer stage by comparing the positions of the plurality of alignment marks on the semiconductor wafer to determine their position errors, and the position errors of the detected alignment mark positions . From the systematic error,
Means for obtaining an alignment accuracy by a residual amount obtained by removing a system error from a position error . 2. A plurality of alignment detectors each having a different position detection principle for aligning an alignment mark position on a semiconductor wafer to a desired position, and an alignment signal processing for processing an alignment output signal output from the alignment detector. A wafer stage on which the semiconductor wafer is mounted and driven by a stage driving unit; a stage position measuring unit that measures the position of the wafer stage; an output signal obtained from the alignment signal processing unit; and the stage position. An arithmetic unit that performs an arithmetic operation to control the position of the wafer stage by comparing the output signal obtained from the measurement unit, and using each of the alignment detectors, detects a plurality of alignment mark positions on the semiconductor wafer. That much
The alignment error is determined and the detected alignment mark position is determined.
Means for obtaining a systematic error from the position error of the position error and obtaining alignment accuracy by a residual amount obtained by removing the systematic error from the position error; and selecting an alignment detector having the smallest residual amount from the plurality of alignment detectors. Means for performing alignment using the selected alignment detector. 3. An alignment mark having a different shape is arranged on the surface of the semiconductor wafer, a plurality of alignment mark positions on the semiconductor wafer are detected by the alignment detector to obtain a position error, and the detected alignment mark position is determined . Determine the systematic error from the position error of
3. The aligning apparatus for an exposure apparatus according to claim 1, further comprising means for selecting an alignment mark having a shape having the smallest residual amount obtained by removing a systematic error from a position error . 4. A step of aligning an alignment mark position on a semiconductor wafer to a predetermined position using an alignment detector, and a step of processing an alignment output signal output from the alignment detector by an alignment signal processing unit. Driving a wafer stage on which the semiconductor wafer is mounted by a stage driving unit; measuring a position of the wafer stage using a stage position measuring unit; and an output signal obtained from the alignment signal processing unit and Controlling the position of the stage by comparing the output signal obtained from the stage position measurement unit with an operation unit, and detecting a plurality of alignment mark positions on the semiconductor wafer to obtain a position error; position error has been the alignment mark position Seeking Luo systematic error, the position
Obtaining an alignment accuracy by a residual amount obtained by removing a systematic error from the error.