JPH02297683A - Microcomputer - Google Patents

Abstract

PURPOSE:To improve accuracy for A/D conversion by holding the output of an output buffer, which goes to be a noise source when an A/D converter is operated, constant. CONSTITUTION:A signal outputted from a NOR circuit 15 is inverted by an inverter 12 and signal line 25 goes to be ''1'' level. Then, the signal is inputted to an OR circuit 17 and a clock signal phi1 to be outputted form the OR circuit 17 is held at the ''1'' level. A signal of a ''0'' level inverted by an inverter 10 is inputted to an AND circuit 18 and a clock signal phi2 to be inputted to a CPU 3 is held at the ''0'' level. Accordingly, the clock signal is not supplied to the CPU 3 and the CPU 3 stops operation. Samely, the other peripheral circuit 5 stops the operation. However, since the clock signals phi1 and phi2 are supplied from clock drivers 19 and 20 to an A/D converter 4, the A/D conversion is executed. Thus, the noise is suppressed and the accuracy is improved for the A/D conversion.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a microcomputer with a built-in A/D converter.

[Conventional technology]

A microcombination system including a conventional A/D converter will be explained with reference to FIG.

First, the constituent elements will be explained.

Oscillator 1 generates a clock, and branching circuit 2 splits the signal into clock signals φ1 and φ2. The two clock terminals of the frequency dividing circuit 20 are connected to clock drivers 29 and 30, and the output sides of the clock drivers 29 and 30 are connected to an A/D converter 4, a central processing unit (CPU) 46, and other peripheral circuits 5. connected to the clock terminal of the CPU46
is connected to the A/D converter 4.

Next, the operation will be explained.

In the conventional one-chip microcontroller, the A/D controller (-ta 4.
The CPU 46 and the peripheral circuit 5 operate in synchronization with clock signals φ1 and φ2 generated by the oscillator 1 and divided by the frequency dividing circuit 2. During analog-to-digital conversion (A/D conversion), the CPU 46 sends a conversion start signal to the A/D converter 4 to start A/D conversion. A/D at the end of A/D conversion
Converter 4 sends an interrupt signal indicating the end of conversion.
1” level and that the A/D conversion is completed.
Let 6 know. The CPU 46 also operates when the A/D converter is operating.
and other peripheral circuits 5 are operating.

[The problem that the invention aims to solve]

In a microcomputer including the conventional A/D converter described above, the CPU and other circuits continue to operate during A/D conversion, so for example, the output connected to the boat is (When the output value of the tsufa transitions from the ``1'' level to the ``0°0° level'' from the lO'' level to the l'1'' level, the G
Current flows through the NDK shopping channel, causing changes in the power supply voltage level and GND pressure level, resulting in noise. This noise affects the A/D converter and impairs the precision of the A/D conversion. a first clock driver, a second clock driver, a circuit for prohibiting the supply of a basic clock signal,
The output of the first clock driver, which has a memory circuit and receives the basic clock signal as input, is connected to an analog-to-digital converter, and the second clock driver is connected to the central processing unit, and the output of the first clock driver is connected to the analog-to-digital converter. The conversion start signal and the analog-to-digital conversion end signal of the analog-to-digital converter are connected to the storage circuit, and the output of the storage circuit is connected to a circuit for inhibiting the supply of a clock signal, inhibiting the supply of the basic clock signal. The circuit for has a circuit connected to a second clock driver.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 shows one embodiment of the present invention.

First, the constituent elements will be explained.

An oscillator 1 generates a clock, and a frequency divider circuit 2 divides the frequency of the clock signal. CPU3 has clock drivers 8 and 9
It has two clock terminals connected to and a conversion start signal terminal connected to latch 6, an fc conversion end signal terminal connected to AND circuit 14, and a conversion mode signal terminal connected to AND circuit 13. The A/D converter 4 is connected to clock drivers 19 and 20 and has two clock terminals. Other peripheral circuit 5 has two clock terminals. The conversion start signal terminal of the CPU 3 is connected to the data input terminal (Di terminal) of the latch 6, the clock input terminal (G terminal) of the latch 6 is connected to the output side of the clock driver 19, and the input side of the clock driver 19 is connected to the It is connected to the clock input terminal of the circuit 2. The output terminal (Q terminal) of the latch 6 is connected to the D terminal of the latch 7 and the AND circuit 13, the Q terminal of the latch 7 is connected to the conversion start signal terminal of the inverter 11 and the A/D converter 4, and the G terminal clock driver The output side of the clock driver 200A is connected to the clock -2 terminal of the branch circuit 2. The input side of the AND circuit 130 is connected to the Q terminal of the latch 6, the conversion mode signal terminal of the CPU 3, and the inverter 11, and the output side is connected to the input side of the NOR circuit 150. The output side of the NOR circuit 15 is connected to the inverter 12 and N
It is connected to the input side of the OR circuit 16. AND circuit 1
4 has its input side connected to the clock driver 19 and the conversion end signal terminal of the A/D converter 4, and its output side connected to the input side of the NOR circuit 16 and the conversion end signal terminal of the CPU 3. Clock terminals φ1 and φ2 of A/D converter 4
are connected to clock drivers 19 and 20. NO
The output side of the R circuit 16 is connected to the input side of the NOR circuit 15. The input side of the OR circuit 17 is connected to the inverter 12 and the φ1 terminal of the branch circuit 2, and the output side is connected to the clock terminal of the CPU 3 and the clock terminals of other peripheral circuits 5 via the clock driver 8.

The input side of the AND circuit 18 is connected to the φ2 terminal of the frequency dividing circuit 2 and the inverter 10, and the output side is connected to the clock terminals of the CPU 3 and other peripheral circuits 5 via the clock driver 9. Inverter 100 input side is inverter 12
It is connected to the.

Next, the operation will be explained. The operation will be explained using timing diagrams of each signal 21-26. A timing diagram is shown in FIG. The timing diagram shows time on the horizontal axis.

Broken line portions indicate time omissions.

A clock signal generated by an oscillator 1 is frequency-divided into φ1 and φ2 by a frequency divider circuit 2. Each unit performs a predetermined operation according to clock signals φ1 and φ2. At time 0 T1, where the A/D converter operation start time is T1, the ``1'' level is output from the A/D conversion start signal terminal of the CPU 3 and the signal line 23
is in the “1” level state, and the latch 6 reads the value of the input terminal at the timing of the clock φl input to the G terminal, so the Q terminal of the latch 6 outputs the “1” level. At this time, the clock φ2 is “1” level. There is an O'' level.
“Since the level signal is input to the latch 70G terminal, it is stored 1c before time T1 and is a ratio signal. @0° level Q
Output from the terminal.

This is inverted by the inverter IIK, and the "1" level is input to the AND circuit 13. Since the conversion mode signal 47 from the CPU 3 is at the "1" level, all inputs to the AND circuit 130 are at the "1" level, and the output gives the signal @24 the "1" level.

Since the 11'' level is inputted to the NOR circuit 15 from the AND circuit 13, the output becomes @O'' level regardless of other inputs. NOR circuit 15 and NOR circuit 16 constitute a latch circuit, and NOR circuit 16 or NOR circuit 1
As long as no signal is input to the input side of 5, the output value is held constant. The isa signal output from the NOR circuit 15 is inverted by the inverter 12, and the signal @25 becomes "1" level and is input to the OR circuit 17. The clock signal φ1 outputted from the OR circuit 17 is held at the 'l' level.
Since a 0'' level signal is input, the clock signal φ2 input to the CPO3 is held at the 0'' level.Therefore, since no clock signal is supplied to the CPU3, the clock signal φ2 is input to the CPO3.
U3 stops operating. Similarly, other peripheral circuits 5 also stop operating.

However, the A/D converter 4 has a clock driver 19.
Since clock signals φ1 and φ2 are supplied from 20, A/D conversion is performed.

Let the A/D converter end time be T2. When T2 is reached, the signal indicating that A/D conversion has been completed (1" level) becomes A/D.
Input to D converter 4!9AND[5][14.

Since the clock signal φ1 is at @l" level, the AND circuit 14
The output of is "1" level. '''1 to NOR circuit 16
NOR times M15 and NOR00M to be leveled “1”
16! The latch circuit constructed by the above is reset and the output of the NOR circuit 15 becomes ``1'' level. This is inverted via the inverter 12 and becomes the "0" level. This 10"
The level is input to the OR circuit 17, and the inverter l
A @1'' level signal is input to the AND circuit through the gate 0.The outputs of the OR circuit 17 and the AND circuit 18 are output according to the levels of the clock signals φ1 and φ2, and
Since the clock signal is transmitted, the CPU 3 starts operating. Similarly, other peripheral circuits 5 also start operating.

Note that when the conversion mode signal 47 is at the 0" level, the output of the AND circuit 13 is always at the "θ" level, so the A/D
Even during the conversion, the CPU 3 and other peripheral circuits 5 operate.

Figures 3 and 4 are diagrams showing a second embodiment of the present invention.

The second embodiment shows a circuit using a CPU having a halt mode. What is halt mode?C
This is a mode in which the PU operating clock is stopped.

First, the constituent elements will be explained.

The CPU 27 includes an interrupt controller 40 that has a function of masking interrupt signals other than the conversion end signal during A/D conversion, and a halt mode designation bit 3 of the standby control register 38 to implement the halt mode.
D terminal K of the halt mode designation bit 39.
An OR circuit 32 is connected, and a G terminal KOR circuit 37 is also connected. The pulse generation circuit 31 includes a ninth AND circuit 33 that generates a clock input to a halt mode designation bit 39 of the CPU 27, an inverter 34, and a latch 35.
It has a built-in latch 36 and two clock terminals (φ1 terminal and φ2 terminal). The A/D converter 28 is an A/D converter 28.
An interrupt controller 4 of the CPU 27 sends an A/D conversion end signal 45, which is an interrupt signal indicating that D conversion is to be completed.
It has a terminal that sends to 0. Other components are the same as the conventional example shown in FIG.

Next, the operation will be explained. The operation will be explained using timing diagrams for each signal line 41-45.

A timing diagram is shown in FIG. The timing diagram shows time on the horizontal axis. Broken line portions indicate time omissions.

Normally, when the CPU 27 is busy in the halt mode, the halt signal 49 and the standby control register write signal 48 are output to the OR circuit 32 or the OR circuit 37, respectively.
is input to halt mode designation bit 39 via C
The PU 27 enters the halt mode and stops operating. To release the halt mode, input an interrupt signal to the CPU. From this point K, the CPU starts operating again.

The A/D conversion start time is assumed to be T3. CPU2 at time T3
7 sends a conversion start signal to the A/D converter 28 and pulse generation circuit 31, and the A/D conversion start signal 41 becomes "1".
At the same time, this signal is sent to the D terminal of the halt mode designation bit 39 of the standby control register 38 via the OR circuit 32 within the CPU 27 unit. The signal is input to the D terminal of the latch 35. The clock signal φ2 is input to the G terminal of the latch 35, and the intermediate signal A42 output from the Q terminal is held at the @l'' level. At this time, the clock signal φ1 input to the latch 36
is at the "O'" level, so the voltage from the latch 36 to the inverter 3 is
The output to 4 is at the 10'' level, which is the state before time T3.
” level and is input to the AND circuit (intermediate signal B4
3).

Therefore, the pulse signal 44 which is the output of the AND circuit 33 has a "1" level, is transmitted to the CPU 27, and is inputted to the G terminal of the halt mode designation bit 39 via the OR circuit 37. Therefore, the D terminal and G terminal of the halt mode designation bit 39 each receive a "1" level input,
Output a halt signal from the Q terminal and CPU2 from the K
7 goes into halt mode. During A/D conversion, the interrupt controller 40 masks all signals other than the A/D conversion end signal, which is an interrupt signal indicating that the A/D conversion has ended. Therefore, the interrupt signal from other peripheral circuits 5 is
Even if it is sent to U27, the interrupt will not be accepted. CPU
27 enters halt mode, so it stops operating and the CPU
Since the output value of the output buffer connected to 27 does not change, the noise changes drastically. This is because the output buffer is the main source of noise, and most output buffers are connected to the CPU port, and the output value of the output buffer changes because a write operation is performed to the port latch by the CPU instruction. This is because the generation of noise can be suppressed and the accuracy of A/D conversion can be sufficiently improved by stopping the operation of the CPU. A/D converter 2
8 and other peripheral circuits 5 are operated by inputting a clock signal, but since these circuits operate with a small current, the noise generated is small and the influence on A/D conversion is also small. After the A/D conversion is completed, a conversion completion signal 45 is transmitted as an interrupt signal from the A/D converter 28 to the interrupt controller 40 of the CPU 27 via the signal line 45. This becomes a halt mode release signal, and the CPU 27
The hold code is released and the CPU 27 starts operating.

〔Effect of the invention〕

As explained above, the present invention suppresses the generation of noise that adversely affects A/D conversion by keeping the output value of the output buffer, which is a noise source during A/D converter operation, constant. This has the effect of improving the accuracy of.

[Brief Description of the Drawings] Fig. 1 is a block diagram showing one embodiment of the present invention, Fig. 2 is a timing diagram of each signal line in Fig. 1, and Fig. 3 is a block diagram showing another embodiment. , Figure 4 shows the CPU and A/D in Figure 3.
FIG. 5 is a detailed block diagram of the converter, FIG. 5 is a timing diagram of each signal line in FIG. 4, and FIG. 6 is a block diagram showing a conventional microcomputer. 1... Oscillator, 2... Frequency divider circuit, 3-
・27. , 46... central processing unit, 4,
28... A/D converter, 5... Other peripheral circuits, 6, 7, 35° 36... Latch,
8.9.19.20.29.30...Clock driver, 10.11,12.34...Inverter, 15.16...NOR circuit, 17,32
゜37...OR circuit, 21...clock signal, 22...clock signal, 23...
... A/D conversion start signal, 24... intermediate signal,
25...Clock prohibition signal, 26...
A/D conversion end signal, 27... Conversion mode signal, 31... Pulse generation circuit, 38...
Standby control register, 39... Halt mode designation bit, 40... Interrupt controller, 41... A/D conversion start signal, 4
2...Intermediate signal A143...Intermediate signal B, 44...Pulse signal, 45...A
/D conversion end signal, 48...standby control register signal, 49...halt signal. Susumu Naika, Patent Attorney

Claims (1)

[Claims] In a microcomputer with a built-in analog-to-digital converter that starts analog-to-digital conversion in response to a command from the central processing unit and outputs an interrupt signal to the central processing unit after the analog-to-digital conversion is completed, the first clock a driver, a second clock driver, a circuit for prohibiting the supply of a basic clock signal,
The output of the first clock driver, which has a memory circuit and receives the basic clock signal as input, is connected to an analog-to-digital converter, and the second clock driver is connected to the central processing unit, and the output of the first clock driver is connected to the analog-to-digital converter. The conversion start signal and the analog-to-digital conversion end signal of the analog-to-digital converter are connected to the storage circuit, and the output of the storage circuit is connected to a circuit for prohibiting the supply of a clock signal, and prohibits the supply of the basic clock signal. A microcomputer, characterized in that the circuit for is connected to a second clock driver.