JP3151824B2 - Bus control circuit and microprocessor - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a bus control circuit, and more particularly to a bus control circuit for controlling a bus cycle of a microprocessor.

[Conventional technology]

FIG. 3 shows a time chart of the conventional bus control circuit.

Referring to FIG. 3, a conventional bus control circuit uses a bus cycle control signal (hereinafter referred to as RD) for extending a bus cycle in accordance with a system clock CLKS inside a microprocessor.
YI).

In FIG. 3, RDYI is sampled at the leading edge C of the system clock CLKS at the end of the state T2 of the bus cycle. When RDYI is at the "0" level, that is, active, the bus cycle shifts to the next state T1, but when RDYI is at the "1" level, that is, inactive, the bus cycle is restarted at the next rising edge D of the system clock CLKS.
RDYI was being sampled.

[Problems to be solved by the invention]

In the above-described conventional bus control circuit, the bus cycle control signal is sampled by the system clock inside the microprocessor, so that the pulse interval of the system clock is a control unit for extending the bus cycle.

Accordingly, there is a disadvantage that a large invalid time is generated between the reception of the bus cycle control signal and the start of sampling between the pulses of the system clock, and as a result, the throughput of the microprocessor is reduced.

[Means for solving the problem]

A bus control circuit according to the present invention includes: a frequency dividing circuit that divides an input clock signal having a frequency higher than a clock frequency of a clock inside a microprocessor and converts the frequency into the clock frequency; A bus state control circuit for setting a bus state for inputting a bus cycle control signal for extending the bus state, and a bus cycle control signal for extending a leading edge of the clock at the end of the bus state and at the time of activating a wait signal to be described later. A sampling circuit that samples at the leading edge of the clock signal; a frequency division control logic circuit that receives an output of the sampling circuit and controls a frequency division operation or stop of the frequency division circuit; and an operation of the frequency division circuit stops. The wait is for outputting a wait signal indicating that the bus state is being extended. Signal output means.

〔Example〕

 Next, the present invention will be described with reference to the drawings.

 FIG. 1 is a circuit diagram showing one embodiment of the present invention.

Referring to FIG. 1, a bus control circuit according to the present invention includes a sampling circuit 1, a frequency division control logic 2, a frequency division circuit 3
And a bus state control circuit 4 and inverters 5 to 10 for matching the logical values of the input / output signals.

The sampling circuit 1 includes an AND gate 11, an OR gate 12, a NAND gate 13, and a D flip-flop 14.

 The frequency division control logic 2 is an OR gate.

The frequency dividing circuit 3 has three stages of JK flip-flops 31 to 33 for dividing an input clock signal output from the frequency dividing control circuit 2.
, An OR circuit 34, and four N-channel MOS transistors N31 to N33.

 Next, the operation of the present embodiment will be described.

FIG. 2 is a time chart of the circuit of this embodiment shown in FIG.

Here, it is assumed that the frequency of the input clock CLKIN is eight times the frequency of the system clock CLKS inside the microprocessor.

Further, the bus cycle control signal RDYI is
The sampling circuit 1 samples the signal from KIN.

Further, the basic bus cycle has two states of T1 and T2, and is set by the bus state control circuit 4 using the system clock CLKS.

First, sampling of the bus cycle control signal RDYI
At the end of the state T2, the operation is performed at a point A on the leading edge of the system clock CLKS. Therefore, the sampling pulse S1 at this time is the AND of the input clock CLKIN and the system clock CLKS obtained by dividing the frequency of the input clock CLKIN by 8 by the frequency dividing circuit 3.

As in the conventional example, when RDYI is at the "0" level, that is, when it is active, the bus cycle shifts to the next state T1.

When the sampling result indicates that RDYI is at the "1" level, that is, inactive, the D flip-flop 14 of the sampling circuit 1 is inverted to the "0" level, and a wait signal indicating that the bus cycle has been extended to the outside. Output WTI. At the same time, the output "0" of the D flip-flop 14 is applied to the frequency division control logic 2, which is a NAND gate, and blocks the input clock CLKIN, so that the frequency division operation of the frequency division circuit 3 is stopped and the wait period TW is started.

As shown in FIG. 2, the clock CLK1 obtained by dividing the input clock CLKIN by two, the clock CLK2 obtained by dividing the input clock CLKIN by two, and the system clock CLKS obtained by dividing the input clock CLKIN by eight are respectively at the “1” level during the wait period TW. Stopped at. Meanwhile, the input clock CLKIN continues to sample the bus cycle control signal RDYI as the sampling pulse S2.

When RDYI changes to the “0” level, that is, the active state, the D flip-flop 14 of the sampling circuit 1
Re-inverts to the "1" level, the wait signal WT1 becomes inactive and is applied to the dividing control logic 2, which is a NAND gate, to pass the input clock signal CLKIN again. The frequency division operation is restarted.

As is apparent from the above description, the sampling of the bus cycle control signal RDYI is performed at the point A at the leading edge of the system clock CLKS at the end of the state T2 and the wait signal WT.
This is performed at the leading edge of the input clock CLKIN when I is active, that is, at the point B.

When viewed from outside the microprocessor, the wait signal WTI is output to indicate the wait state because the number of system clocks does not change due to a change in the bus cycle and cannot be distinguished.

The embodiments of the present invention have been described above, but the present invention is not limited to the above embodiments, and various modifications can be made.

〔The invention's effect〕

As described above, according to the present invention, the bus cycle is controlled by a clock signal having a frequency higher than the system clock frequency of the microprocessor, so that there is an effect that the extension control unit of the bus cycle can be shortened.

Accordingly, the invalid time from the reception of the bus cycle control signal to the start of sampling is shortened, and as a result, there is an effect that the throughput of the microprocessor can be improved.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing an embodiment of the present invention, and FIG.
FIG. 3 is an operation time chart of the circuit shown in the figure, and FIG. 3 is a time chart of the conventional bus control circuit. 1 ... sampling circuit, 2 ... frequency control logic, 3
... frequency divider circuit, 4 ... bus state control circuit, 5-10 ...
... Inverter, 11 AND gate, 12 OR gate, 13 NAND gate, 14 D flip-flop,
31-33: JK flip-flop, 34: NOR gate.

Claims (2)

(57) [Claims] A dividing circuit for dividing an input clock signal having a frequency higher than a clock frequency of a clock inside the microprocessor and converting the frequency into the clock frequency; and a bus for designating a state of a bus inside the microprocessor. A bus state control circuit for setting a state; a bus cycle control signal for extending the bus state; a bus leading edge of the clock at the end of the bus state; A sampling circuit that samples at a leading edge of the rising edge; a frequency division control logic circuit that receives an output of the sampling circuit and controls a frequency division operation or stop of the frequency division circuit; Wait signal output means for outputting a wait signal indicating that the bus state is being extended A bus control circuit comprising: 2. The bus control circuit according to claim 1, further comprising a built-in bus control circuit according to claim 1, wherein an output of said frequency dividing circuit is used as said internal clock.