JPH02296364A - Forming method for wiring - Google Patents

Abstract

PURPOSE:To form a high density gate wiring without restriction of pattern resolution capability of a projection aligner, by forming a pattern turing to the center of a pair of gate electrodes, on the side wall part of a circuit pattern formed by projection alignment, and forming a desired gate wiring on the side wall part of the pattern. CONSTITUTION:After an insulating layer 15 is formed on the surface of first patterns 12, 13 formed on the surface of a semiconductor substrate 20, said insulating layer 15 is etched back, and the insulating layer 15 left only on the approximate near side surface of the first patterns 12, 13 is formed as a second pattern 15. After the first patterns 12, 13 are eliminated and conducting layers 17, 18 are formed on the surfaces of the second pattern 15 and the semiconductor substrate 20, said conducting layers 17, 18 are etched back; only the conducting layers 17, 18 on the vicinity side part of the second pattern 15 are left; the second pattern 15 is eliminated, thereby forming a gate wiring 21 of the conducting layers 17, 18. As a result, a high density gate wiring 21 having two times density of the first patterns 12, 13 can be formed. Thereby a high density gate wiring can be formed without restriction of pattern resolution capability of a projection aligner.

Description

DETAILED DESCRIPTION OF THE INVENTION <Industrial Application Field> The present invention relates to a wiring forming method for increasing the density of gate wiring of an element realizing a high-density memory device such as a 32 megabit mask ROM.

<Prior Art> Hereinafter, a conventional method for forming a gate wiring of an IO3 transistor will be described with reference to the drawings. FIG. 2 is an explanatory cross-sectional view of a semiconductor device at each step for explaining a conventional method of forming a gate wiring of an hOS transistor.

First, as shown in FIG. 2(a), the Si substrate 10 is oxidized to form a silicon oxide film 1 on the surface of the Si substrate 10. As shown in FIG. Next, as shown in FIG. 2(b), after sequentially depositing a polysilicon film 2 containing impurities such as P and B and a silicide film 3 which is a high melting point metal, a photoresist 4 is deposited on the silicide film 3. Apply to. Thereafter, a photoresist turn is formed by projection exposure, and using the formed circuit pattern of the photoresist 4 as a mask, anisotropic etching is performed by a method such as reactive ion etching, as shown in FIG. 2(C). As shown, the circuit pattern is transferred to form a gate wiring 7 in which a polysilicon film 2 and a silicide film 3 are laminated.

Next, the photoresist 4 is removed and a silicon oxide film 5 is deposited as shown in FIG. 2(d). By etching back this silicon oxide film 5 by anisotropic etching such as reactive ion etching to the thickness of the silicon oxide film 5, silicon is etched only on the sides of the gate wiring 7, as shown in FIG. 2(e). The oxide film 5 is left. In order to prevent the formation of parasitic transistors, data 1 to wiring 7 are
Impurities such as B and P are implanted into the Si substrate 10 in between, as shown by the arrows. Then, as shown in FIG. 2(f),
The impurity diffusion region 8 for preventing parasitic transistor operation is made of Si.
Formed on the substrate IO. Finally, as shown in the figure, a silicon oxide film 6 is deposited to insulate the gate wiring 7 and the upper layer wiring.

<Problems to be Solved by the Invention> As is clear from the above, according to the conventional gate wiring formation method, the gate wiring is formed by directly transferring the circuit pattern transferred by projection exposure. densification is limited by the pattern resolution capability of the projection exposure machine. Therefore, even in the formation of a mask 11OH, in which a high circuit density can be achieved by increasing the density of only the gate wiring, there is a problem that the increase in density is limited by the pattern resolution capability of the projection exposure machine.

The present invention was devised in view of the above circumstances, and provides a wiring forming method that can realize high-density wiring without being limited by the pattern resolution ability of a projection exposure machine. The purpose is to

Means for Solving the Problems> In order to solve the above problems, the wiring forming method of the present invention includes the following steps:
After forming an insulating layer on the surface of the semiconductor substrate and the surface of the first pattern formed on this surface, this insulating layer is etched banked, and the insulating layer left almost only on the side surfaces of the first pattern is used as a second insulating layer.
After removing the first pattern and forming a conductive layer on the surface of the second pattern and the surface of the semiconductor substrate, this conductive layer is etched back to form a conductive layer on almost the sides of the second pattern. After leaving only the second pattern, the second pattern is removed to form wiring using the conductive layer.

Further, after removing the second pattern, ions can be implanted into the substrate between the wirings in order to prevent parasitic devices from being formed between the wirings.

Furthermore, when etching back the conductive layer, circuit transfer using a resist pattern can be used in combination to form high-density wiring and low-density wiring at the same time.

After forming an insulating layer on the surface of the semiconductor substrate and the surface of the first pattern formed on this surface, this insulating layer is etched back and the insulating layer left almost only on the side surfaces of the first pattern is used as the second insulating layer.
After removing the first pattern and forming a conductive layer on the surface of the second pattern and the surface of the semiconductor substrate, this conductive layer is etched back to form a conductive layer on almost the sides of the second pattern. Since only the second pattern is left and the second pattern is removed to form wiring using the conductive layer, high-density wiring having twice the density of the first pattern is formed. After removing the second pattern, ions can be implanted into the semiconductor substrate between the wirings, so that an impurity diffusion region for preventing parasitic transistor operation can be easily formed.

Furthermore, when etching back the conductive layer, a low-density pattern corresponding to the resist pattern is formed using circuit transfer using the resist pattern.

<Example> The present invention provides that by performing an etch-back process using anisotropic etching such as reactive ion etching twice, a gate wiring with a density twice as high as that of a circuit pattern formed by projection exposure can be formed. is used. That is, a pattern forming the center of a pair of gate electrodes is formed on the sidewall portion of a circuit pattern formed by projection exposure, and then a desired gate wiring is formed on the sidewall portion of this pattern.

Hereinafter, one embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a drawing for explaining one embodiment of the present invention, and FIGS. 1(a) to (j) are cross-sectional explanatory views of a semiconductor device at each step of wiring formation. B) and (2) are plan explanatory views of the semiconductor device in steps before and after the second etch-back.

First, as shown in FIG. 1(a), a silicon oxide film 11 is formed on the surface of a Si substrate 20, and then as shown in FIG.
As shown in FIG.
3 are sequentially deposited. Then, a photoresist 14 is applied on the silicon oxide film 13.

Next, a fine circuit pattern of about 0.5 μm is transferred onto the photoresist 14 by projection exposure and developed, thereby forming a fine circuit pattern of about 0.5 μm on the photoresist 14. The circuit pattern of the photoresist 14 thus formed is etched using a directional etching method such as reactive ion etching, and the polysilicon film 12 and silicon oxide are etched as shown in FIG. 1(C). A circuit pattern (first pattern) consisting of a laminated layer with the film 13 is formed. Next, after removing the photoresist 14, as shown in FIG. 1(d), a silicon nitride film 15, which is an insulating layer, is deposited. This silicon nitride film 15 is etched by anisotropic etching such as reactive ion etching as shown in FIG. 1(e).
The silicon nitride film 15 is selectively left on the sidewalls of the pattern of the silicon oxide film 13 by performing an etch bank to a film thickness of 5 (first etch back). Furthermore, Fig. 1 (f
), only the silicon oxide film 13 is selectively removed using a wet enchantment containing IIF or the like, and then only the polysilicon film 12 is selectively removed using phosphoric acid or the like to form a protruding silicon nitride film 15 (second pattern). After that, the exposed silicon oxide film 11 is removed by IP, and the exposed surface of the Si substrate 20 is oxidized again to form a silicon oxide film 16 on this surface.

Thereafter, as shown in FIG. 1(8), a conductive polysilicon film 17 doped with impurities such as P and B, and a silicide film 18 made of a high melting point metal are sequentially deposited. These polysilicon film 17 and silicide film 18 are etched back by anisotropic etching such as reactive ion etching (second etch back), as shown in FIG. The polysilicon film 17 and silicide film 18 are left only on the side wall portions, and the remaining polysilicon film 17 and silicide film 18 form the gate electrode of the MOS l-transistor.

At this time, for circuit parts that do not require high-density gate wiring (low-density gate wiring parts), such as peripheral circuits of memory circuits, before the second etch-back, a photoresist is projected and exposed using an etching mask. By forming the gate wiring in advance, it is possible to form the low-density gate wiring at the same time as the high-density gate wiring at the second esodepacking.

For example, as shown in the plan view of part of the wiring in FIG. 1(k), a region covered by a rectangular resist mask 30 is formed. In this area, as in the case of patterning with a normal resist mask, a resist mask 30 is applied to the area covered with the resist mask 30 during the second etch pack.
Since the 0 pattern is transferred, a wiring 31 having a width corresponding to the shape of the resist mask 30 is formed as shown in FIG. 1 (I!). In addition, 15 in FIG. 1(k) is a silicon nitride film shown in FIG. 1(f), and FIG. 1(ffi)
18 is a silicide film shown in FIG. 1 (01).

Next, as shown in FIG. 1(i), by removing the silicon nitride film 15 using phosphoric acid or the like, a gate wiring 21 with a silicide film 18 laminated on the polysilicon film 17 is formed.
is formed. After this, the Si substrate 2 between the gate wirings 21
In order to prevent the transistors formed in the St substrate 20 from operating as parasitic transistors, impurity ions are implanted into the Si substrate 20 between the gate wirings 21 as shown by the arrow. As shown in Figure (j), an impurity diffusion region 22 for preventing the operation of a parasitic transistor is formed in the Si substrate 20 between the gate wirings 21. Finally, as shown in FIG. 1(j), a silicon oxide film 19 is formed for the purpose of insulating the gate wiring 21 and the upper layer wiring.
Deposit.

Through the above steps, two parts of the projection-exposed circuit pattern are formed.
Gate wiring can be formed at twice the density.

<Effects of the Invention> As explained above, in the wiring forming method of the present invention, after forming an insulating layer on the side surface of the first pattern formed on the surface of a semiconductor substrate, the first pattern is removed and the remaining insulating layer is removed. A conductive layer is formed on the side surface of the second pattern, and then the second pattern is removed to form wiring using the conductive layer.

Therefore, according to the wiring forming method of the present invention, the first pattern, that is, the gate wiring having twice the density of the gate wiring formed by projection exposure can be formed without being limited by the pattern resolution ability of the projection exposure machine. It becomes possible to do so. Therefore, the wiring forming method of the present invention is extremely effective for increasing the density of memory devices that require gate wiring under the width plate, such as a 32 megabit mask RO)I.

Further, since impurities can be easily injected between the wirings after removing the second pattern, an impurity diffusion region for preventing parasitic transistor operation can be easily formed on the surface of the semiconductor substrate.

Furthermore, when performing the second etch-back, low-density gate wiring can be formed simultaneously with high-density gate wiring by patterning using normal projection exposure.

[Brief explanation of drawings]

FIG. 1 is a drawing for explaining one embodiment of the present invention, and FIGS. 1(a) to (j) are cross-sectional explanatory views of a semiconductor device at each step of wiring formation. I() and (i) are plan explanatory views of the semiconductor device in the steps before and after the second etch-back. FIG. 12... Polysilicon film, 13... Silicon oxide film, 15... Silicon nitride film, 17... Polysilicon film, 18... Silicide film, 20... Semiconductor. Substrate. Patent applicant Sharp Corporation

Claims (1)

[Claims] (1) After forming an insulating layer on the surface of the semiconductor substrate and the surface of the first pattern formed on this surface, this insulating layer is etched back and the insulating layer left only on almost the side surfaces of the first pattern is used as the second insulating layer. After removing the first pattern and forming a conductive layer on the surface of the second pattern and the surface of the substrate, this conductive layer is etched back to form a second pattern.
1. A wiring forming method, comprising: leaving only the conductive layer on substantially the sides of the pattern, and then removing the second pattern to form a wiring using the conductive layer.