JPH02295358A - Picture processor - Google Patents

Abstract

PURPOSE:To satisfactorily discriminate a halftone area by providing a means to detect a minimum value signal out of additive three primary color signals from input picture data and to discriminate the halftone area of an input picture based on this minimum value signal. CONSTITUTION:The means is provided to detect the minimum value signal out of the additive three primary color signals from the input picture data and to discriminate the halftone area of the input picture based on this minimum value signal. Namely, the halftone area is detected by using the minimum value of color resolving signals R, G and B. Accordingly, since the minimum value of the color resolving signals R, G and B is used as a dot detecting signal, a halftone signal can be securely detected without affected by a color. Thus, picture part processing (high gradient processing) can be executed even concerning the halftone of the color and the picture quality of the output picture is improved.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an image processing device that identifies a halftone region from an input image.

[Conventional technology]

In recent years, digital color copying machines that obtain digital color hard copies by color-separating a color original, reading each pixel, digitally processing the read image data, and outputting it to a color printer have become widespread. This type of device has the advantage of being able to process image data digitally, so it is possible to move the image output position (
Fig. 72(a)), extracting a desired image area (Fig. 72(b)), converting only a certain color within the desired area (Fig. 72(C)), and storing data in memory. It has become possible to perform various image processing such as inserting written characters and images into a reflective original (FIG. 72(d)), and its application in the field of so-called color copying is expanding.

Therefore, by combining various functions, it has become possible to easily apply it to color proposals, advertising posters, promotional materials, design drawings, etc.

On the other hand, for color reflective originals, the letters look more like letters.
There is a growing demand for images to look more like real images, and in response to this, image area separation is used to separate text and image areas.
High-resolution processing is applied to the text portion, particularly black characters are printed in a single black color, while high-gradation processing is applied to the image portion.

With this image area separation, the NTSC luminance signal Y Y=0.3R+0.6G+O. lIB...
(1) (R (red), G (green), B (blue)
) was used.

[Problem to be solved by the invention]

However, in the above-mentioned conventional technique, since the luminance signal Y is a signal that has no correlation with chromaticity, it has a drawback that it is weak in extracting colored halftone signals.

That is, for example, since the coefficient of B in the above equation (1) is small, a signal with a strong bluish tint contributes less to the luminance signal Y. Therefore, an erroneous determination occurs in the determination of a colored halftone area.

SUMMARY OF THE INVENTION Therefore, it is an object of the present invention to provide an image processing apparatus that can prevent such erroneous determinations and can satisfactorily discriminate halftone areas from an input image.

[Means and operations for solving the problems] In order to solve the above problems, the image processing device of the present invention includes means for detecting a minimum value signal among three additive primary color signals from input image data;
It is characterized by comprising means for determining a halftone region of the input image based on the minimum value signal that is the output of the detection means.

In the above configuration, the discrimination means discriminates a halftone region of the input image based on the minimum value signal detected by the detection means.

(Margin below) 〔Example〕 Hereinafter, the present invention will be explained in detail with reference to the drawings.

FIG. 1 shows an example of a schematic internal configuration of a digital color image processing system according to the present invention. As shown in the figure, this system includes a digital color image reading device (hereinafter referred to as color league) 1 at the top and a digital color image printing device (hereinafter referred to as color printer) 2 at the bottom. This color reader l has color separation means and C
A photoelectric conversion element such as a CD reads the color image information of the original for each color and converts it into an electrical digital image signal. Further, the color printer 2 is an electrophotographic laser beam color printer that reproduces a color image in each color according to the digital image signal, and records the image by transferring it to recording paper multiple times in the form of digital dots.

First, an overview of the color reader I will be explained.

3 is a document, 4 is a platen glass on which the document is placed, and 5 is a lens for condensing the reflected light image from the document exposed and scanned by the halogen exposure lamp 10 and inputting the image to the 1-magnification full-power color sensor 6. It is a door array lens, 5, 6,
7. 10 as a document scanning unit 11 performs exposure scanning in the direction of arrow AI.

The color separation image signals read line by line during exposure scanning are amplified to a predetermined voltage by the sensor output signal amplification circuit 7, and then input to a video processing unit, which will be described later, via a signal line 501, where they are subjected to signal processing. Details will be described later. 501 is a coaxial cable for ensuring faithful transmission of signals. A signal 502 is a signal line that supplies drive pulses for the same-magnification full-strength color sensor 6, and all necessary drive pulses are generated within the video processing unit 12. 8
．． Reference numeral 9 denotes a white plate and a black plate for white level correction and black level correction of the image signal, which will be described later.By irradiating with the halogen exposure lamp 10, a signal level of a predetermined density can be obtained, and the white plate of the video signal can be obtained. Used for level correction and black level correction. 13 is a control unit having a microcomputer, which is connected to the bus 508
Display on the operation panel 20, key manual control, control of the video processing unit 12, position sensor S
The position of the document scanning unit 11 is determined by the signal line 5 using l and S2.
09, 510, and a stepping motor l4 for moving the scanning body 11 via the signal line 503.
Stepping motor drive circuit control to pulse drive,
All of the functions of the color reader part 1, such as ON/OFF control and light amount control of the halogen exposure lamp IO by the exposure lamp driver via the signal line 504, and control of the digitizer 16, internal keys, and display unit via the signal line 505. is under control. The color image signal read by the above-mentioned exposure scanning unit l1 during original exposure scanning is input to the video processing unit l2 via the amplifier circuit 7 and the signal line 501, and is subjected to various processes described later in this unit l2. , the printer part 2 via the interface circuit 56
will be sent to.

Next, an outline of the color printer 2 will be explained. 711 is a scanner, a laser output unit that converts the image signal from the color reader l into an optical signal, and a polyhedron (for example, an octahedron).
polygon mirror 712, a motor (not shown) for rotating this mirror 712, and an f/θ lens (imaging lens)
713 etc. 714 is a reflecting mirror that changes the optical path of the laser beam, and 715 is a photosensitive drum. The laser beam emitted from the laser output section is reflected by a polygon mirror 712, passes through a lens 713 and a mirror 714, and linearly scans (raster scan) the surface of a photosensitive drum 715, forming a latent image corresponding to the original image. do.

In addition, 711 is a primary charger, 718 is a full exposure lamp,
723 is a cleaner section that collects residual toner that has not been transferred; 724 is a pre-transfer charger; these members are arranged around the photosensitive drum 715.

726 is a developer unit that develops the electrostatic latent image formed on the surface of the photosensitive drum 715 by laser exposure; 731Y, 731M, 731C, and 731Bk are developing sleeves that directly develop the photosensitive drum 715;
0Y, 730M, 730C, and 7308k are toner hoverers that hold spare toner, and 732 is a screw that transports the developer, and these sleeves 731Y~
7318k,} A developing unit 726 is constituted by the inner hoppers 730Y to 7308k and the screw 732, and these members are arranged around the rotation axis P of the developing unit. For example, when forming a yellow toner image, yellow toner development is performed at the position shown in this figure, and when forming a magenta toner image, the developing device unit 72
6 is rotated around the axis P in the figure, and the developing sleeve 731M in the magenta developing device is disposed at a position in contact with the photoreceptor 715. Cyan and black development work in the same way.

Further, 716 is a transfer drum that transfers the toner image formed on the photosensitive drum 715 onto paper, 7l9 is an actuator plate for detecting the moving position of the transfer drum 716, and 720 is adjacent to this actuator plate 719. 725 is a transfer drum cleaner, 727 is a paper press roller, 728 is a static eliminator, and 729 is a transfer charger. These members 71
9, 720, 725, 727, and 729 are arranged around the transfer roller 716.

On the other hand, 735 and 736 are paper feed cassettes that store paper (paper sheets), and 737 and 738 are cassettes 735 and 736.
paper feed rollers for feeding paper from 739, 740,
Reference numeral 741 denotes a timing roller that takes the timing of paper feeding and conveyance, and the paper fed and conveyed via these is guided by a paper guide 749 and wrapped around the transfer drum 716 while the leading edge is carried by a gripper (to be described later) to form an image. Shift to the formation process.

Further, 550 is a drum rotation motor, and the photosensitive drum 7
15 and the transfer drum 716 are rotated in synchronism, 750 is a peeling claw that removes the paper from the transfer drum 716 after image formation is completed, 742 is a conveyor belt that conveys the removed paper, and 743 is conveyed by the conveyor belt 742. The image fixing unit 743 is an image fixing unit that fixes the paper that has been processed.

The image processing circuit according to the present invention will be described in detail with reference to FIG. 2 and subsequent figures. This circuit exposes a full-color original to an illumination source such as a halogen lamp or fluorescent lamp (not shown), captures a reflected color image with a color image sensor such as a COD, and sends the obtained analog image signal to an A/D converter. A color image copying device that processes and processes the digitized full-color image signal and outputs it to a thermal transfer color printer, inkjet color printer, laser beam color printer, etc. (not shown) to obtain a color image, or digitizes it in advance. It is applied to a color image output device, etc. that inputs the color image signal from a computer, other color image reading device, or color image transmitting device, performs processing such as composition, and outputs it to the color printer mentioned above. It is something.

The document is first irradiated by an exposure lamp (not shown), and the reflected light is separated into colors for each image and read by a color reading sensor 500a, and amplified to a predetermined level by an amplifier circuit 501a. 533a is a COD driver that supplies pulse signals for driving the color reading sensor, and the necessary pulse source is generated by a system control pulse generator 534a.

FIG. 3 shows the color reading sensor and drive pulses. Figure 3(a) shows the color reading sensor used in this example, which reads by dividing the main scanning direction into five (63
．． Assuming 5 μm as one pixel (4 dots/inch (hereinafter referred to as dpi)), 1024 pixels, that is, as shown in the figure
Since the pixels are divided into three by G, B, and R in the main scanning direction, the total number of effective pixels is 1024X3=3072. On the other hand, each of the chips 58 to 62 is formed on the same ceramic substrate, and the chips 1, 3, . 5th (58a
．． 60a, 62a) are on the same line LA, 2, 4
The number is 4 lines apart from LA (63.5 μm x 4 = 254
micrometers) on the line LB, and scans in the direction of the arrow AL when reading the document.

1, 3 out of each 5 CCDs. The 5th one is for the drive pulse group ODRV118a, and the 2.4th one is for the EDRV119a.
are driven independently and synchronously.

OOIA, 002A, OR included in ODRVI18a
EOIA, EO2A included in S and EDRV119a,
ERS is a charge transfer clock and a charge reset panorez in each sensor, respectively. 1, 3. Due to mutual interference and noise limitations between the 5th and 2.4th signals, they are generated in perfect synchronization so that there is no jitter between them. Therefore, these pulses are generated by one reference oscillation source OSC558a (
(Fig. 2).

Figure 4(a) shows ODRV118a and EDRV119a.
FIG. 4(b) is a timing chart of the circuit block that generates the pulse generator 534a of FIG. 2, which is included in the system control pulse generator 534a of FIG. Clock K obtained by dividing the original clock CLKO generated by a single OSC558a
O135a is a clock that generates reference signals SYNC2 and SYNC3 that determine the timing of ODRV and EDRV (7) generation, and SYNC2 and SYNC3 are the settings of presettable counters 64a and 65a that are set by the signal line 22 connected to the CPU bus. The output timing is determined according to the value, and SYNC2 and SYNC3 are connected to the frequency divider 66.
a, 67a and drive pulse generators 68a, 69
Initialize a. In other words, H input to this block
Based on SYNC118, all with one oscillation source OSC5
Since it is generated by the CLKO output from 58a and the divided clocks that are all generated synchronously, the OD
The respective pulse groups of the RV 118a and the EDRV 119a are obtained as synchronous signals with no jitter at all, and signal disturbances due to interference between sensors can be prevented.

Here, the sensor drive vanoles ODRVI18a obtained in synchronization with each other are l, 3. Fifth sensor 58a
, 60a, 62a, the EDRVI 19a is supplied to the 2.4th sensor 59a, 61a, and each sensor 58a,
Video signals V1 to V5 are independently output from 59a, 60a, 61a, and 62a in synchronization with the drive pulse, and an independent amplifier circuit 501-1 is provided for each channel shown in FIG.
~501-5, V1, V3, and V5 are amplified to a predetermined voltage value through the coaxial cable 101a at the timing 003129a in FIG. 3(b). input to the circuit.

The color image signal obtained by dividing the original input into the video image processing circuit into five parts is processed by the sample hold circuit S/H502a in three colors of G (green), B (blue), and R (red). separated into

Therefore, after S/H, 3×5=15 signals are processed.

The analog color image signals sampled and held for each color R, G, and B by the S/H circuit 502a are as follows:
The next stage A/D conversion circuit 503a digitizes each channel from 1 to 5, and each channel from 1 to 5 is independently connected in parallel.
Output to the next stage.

Now, in this embodiment, as described above, 4 lines (63.
Since the document is read by five staggered sensors that have an interval of 5 μm x 4 = 2 5 4 μm in the sub-scanning direction and are divided into 5 areas in the main scan direction, channels 2 and 4 that are scanning in advance The reading positions for the remaining 1, 3, and 5 are shifted. Therefore, in order to connect this correctly, a deviation correction circuit 504 equipped with memory for multiple lines
The deviation is corrected by a.

Next, using FIG. 5(a), the black correction/white correction circuit 506
The black correction operation in a will be explained. As shown in FIG. 5(b), when the amount of light input to the sensor is small, the black level outputs of channels 1 to 5 vary greatly between chips and between pixels. If this is output as is and an image is output, streaks and unevenness will occur in the data portion of the image. Therefore, it is necessary to correct the output variation in the black portion, and this correction is performed using a circuit as shown in FIG. 5(a). Prior to the original reading operation, the original scanning unit is moved to the position of a black plate having uniform density that is placed in a non-image area at the tip of the original table, the halogen is turned on, and a black level image signal is input to this circuit.

Regarding the blue signal BIN, in order to store one line of this image data in the black level RAM78a,
Select A with the selector 82a (■), close the gate 80a (■), and open the gate 81a. That is, the data line is 151a
− + 152a + 153a, while RA
The address 155a of M78a is initialized with 2,
■ is output to the selector 83a so that the output 154a of the address counter 84a that counts VCLK is input, and the black level signal for 1 line is R A M 7
8a (hereinafter referred to as black reference value included mode).

When reading an image, the RAM 78a is in the data read mode, and the data lines 153a-+157a
Each line and each pixel are read out and input to the B input of the subtracter 79a through the path . That is, at this time gate 81
a is closed (■), and 80a is open (■). Moreover, the selector 86a becomes an A output. Therefore, the black correction circuit output 1 5
6a is for black level data DK (i), for example, in the case of a blue signal, BI N (i) - DK (i) = l
Obtained as 3ou■(i) (called black correction mode)
. Similarly, Green GI N + Red RIN is also 7.
Similar control is performed by 7aG and 77aR.

In addition, the control lines of each selector gate for this control
+ 01 ■. (2) is performed under CPU control by the latch 85a assigned as I/O of the CPU 22 (FIG. 2). Note that the selectors 82a, 83a, . 86a
By selecting B, the CPU 22 selects R A M
7 8 a can be accessed.

Next, white level correction (shading correction) in the black correction/white correction circuit 506a will be explained with reference to FIG. White level correction corrects variations in sensitivity of the illumination system, optical system, and sensor based on white data obtained when the document scanning unit is moved to the position of a uniform white plate and irradiated. The basic circuit configuration is shown in FIG. 6(a). The basic circuit configuration is shown in Figure 5 (
This is the same as a), but the only difference is that the black correction uses a subtracter 79a, whereas the white correction uses a multiplier 79'a, so a description of the same parts will be omitted.

COD (500a) for reading originals during color correction
) is at the uniform white plate reading position (home position), that is, before copying or reading, an exposure lamp (not shown) is turned on. The light is turned on, and image data of a uniform white level is stored in the correction RAM 78'a for one line. For example, if it has an A4 longitudinal width in the main scanning direction, it is 16 pei'/mm and 16 x 297 mm = 47
52 pixels, or at least the RAM capacity is 4752
As shown in FIG. 6(b), if the i-th pixel white board data Wi (i=1 to 4752) is
'a stores data for the white plate for each pixel, as shown in FIG. 6(C).

On the other hand, for Wi, the read value Di of the normal image of the i-th pixel is corrected data Do=DiXFFH/Wi
It should be. Therefore, from the CPU 22, the latch 85
Gate 80'a for 'a■',■',■',■'
, 81' a, and selector 82' a,
83'a and 86'a are output so that B is selected, and the RAM 78'a is made accessible to the CPU.

Next, in the procedure shown in FIG. 6(d), the CPU 22 sets FFH /Wo for the first pixel Wo, FF/W for W,
. . . are performed in sequence to replace the data. After completing the blue component of the color component image (Fig. 6(d))
pB) Similarly, the green component (Step G) and the red component (Step R) are performed sequentially, and then the game 80'a is opened so that Do=DiXFF H/Wi is output for the input original image data Di. (■'), 81'a is closed (■'), A is selected for selectors 83'a and 86'a, and coefficient data FF read from RAM 78'a}I/Wi is connected to signal line 153a→157a , and is multiplied by the original image data 151a input from one side and output.

As described above, the black level and white level are corrected based on various factors such as the black level sensitivity of the image input system, the dark current variation of the CCD, the sensitivity variation between each sensor, the optical system light amount variation, and the white level sensitivity. Image data B O that has been uniformly corrected for each color, both white and black, in the scanning direction.
UT 101+ G OLJT 102, RoU. l0
3 is obtained. The white and black level-corrected color separation image data obtained here are created by detecting pixels on the image having a specific color density or a specific color ratio according to instructions from an operation unit (not shown), and The data is sent to a color conversion circuit B that converts the data into another color density or color ratio instructed by the operation unit.

Color Conversion> FIG. 7 is a block diagram of color conversion (gradation color conversion and density color conversion). The circuit in FIG. 7 uses an 8-bit color separation signal R IN
+ GIN. A color detection unit 5b that determines an arbitrary color set in the register 6b by the CPU 20 for B IN (lb to 3b), color detection for multiple locations,
The area signal Ar4b for performing color conversion and the signal outputted by the color detection section indicating that it is a specific color (hereinafter referred to as a hit signal) are sent in the main scanning and sub-scanning directions (in the example shown in Fig. 7, only in the sub-scanning direction). ) Line memory 10 that performs processing to expand
b-1lb, OR gate 12b, color conversion enable signal 33b1 generated from expanded hit signal 34b and non-rectangular signal (including rectangle) BHi27b, enable signal 33b and input color separation data (RINI GINI B
IN lb-3b), line memories 13b-16b for synchronizing area signal Ar4, delay circuit 1
7b-20b1 enable signal 33b, synchronized color separation data (RIN, GIN.BIN'
2lb to 23b), area signals Ar' 24b and C
The PU 20 performs color conversion based on the color data after color conversion set in the register 26b.The color conversion unit 25b1 converts the color separation data (R.ouT, GoI.l
A, Bou, 28b-30b), ROLJT + G
Hit signal H output in synchronization with OUT + BOLJT. Consists of UT3lb.

Next, we will outline the algorithms for gradation color determination and gradation color conversion. Here, gradation color judgment and gradation color conversion mean color judgment and conversion of the same hue in order to save the density value and perform color conversion for colors of the same hue when performing color judgment and color conversion. It is to perform a transformation.

It is known that for the same color (certain hue), for example, a red signal R1, a green signal G1, and a blue signal B have the same ratio.

Therefore, data M1 of one of the colors to be converted (maximum value color, hereinafter referred to as principal color) is selected, and the ratio between it and the data of the other two colors is determined. For example, and the input data RL
For G+, Bl, M, X γ1 ≦R
1≦M,

Furthermore, for the data (R2, G2, B2) after color conversion, the ratio between the data M2 of the main color (in this case, the maximum value color) and the data of the other two colors is determined.

For example, when G2 is the main color, set M2==G2, and
For the primary color M of input data, if the data is a color conversion pixel, if it is not a color conversion pixel, (R + , G i ,
B I) is output.

As a result, all parts of the same hue with gradation are detected,
It becomes possible to output color conversion data according to gradation.

FIG. 8 is a block diagram showing an example of a color determination circuit. This part is a part that detects pixels to be color-converted.

In this figure, 50b is R, N bl, G, N b2
, B, Nb3 is a smoothing section that smooths the input data, and 5lb is one of the outputs of the smoothing section (primary color).
The selectors 52bR, 52b, 52b8 select the output of the selector 5lb and the fixed value R. + Selector for selecting one of GO+Bo, 54bR, 54bo, 54
b8 is an OR gate, 63b, 64b R, 64
b, , 64b8 are area signals ArlO, 64b8, respectively.
Selector 51k), 52b based on Ar20
H, 52b,, selector for setting the select signal to 52bB, 56bR, 56b,, 56
bB, 57bR, 57bo, and 57b8 are multipliers that calculate their respective upper and lower limits.

Further, each upper limit ratio register 58b R, 58b, , 58b 8 and lower limit ratio register 59b R, 59b 0, 59 set by the CPU 20
b B can each set data for color detection for a plurality of areas based on the area signal Ar30.

Here, ArlO, Ar20, and Ar30 are signals created based on Ar4b in Fig. 7, and each has the required number of stages of D.
Contains F/F. Also, 6lb is an AND gate, 62
b is an OR gate, and 67b is a register.

Next, we will explain the actual movement. R,Nbl,G,
One of the data R'G' and B' obtained by smoothing N b2, B and N b3, respectively, is sent to the CPU.
The selector 5l is activated by the select signal SI set by the selector 20.
Select with b to select the main color data. Here, C
The PU20 sets different data A and B in the registers 65b and 66b, and the selector 63b selects ArlO.
Depending on the signal, either A or B is selected and input to the selector 5lb as the S1 signal.

In this way, prepare two registers, 65b and 66b,
By inputting different data to A and H of the selector 63b and selecting one of them using the area signal AriO, separate color detection can be performed for a plurality of areas. This area signal ArlO may be a signal for not only a rectangular area but also a non-rectangular area.

In the next selectors 52bR, 52bo, 52b8, CP
R set by U20. , Go, Bo or selector 5lb
Any of the primary color data selected in is sent to the decoder 53b.
are selected by a select signal generated from the outputs 53ba to 53bc and the fixed color mode signal S2. In addition, selectors 64bR, 64b, , 64b8
By selecting either A or B in accordance with the area signal Ar20, as in the case of the selector 63b, different colors can be detected for a plurality of areas. Here, Ro, Go, and Bo are selected when the main color is in conventional color conversion (fixed color mode) and gradation color determination, and the main color data is selected when it is a color other than the main color in gradation color conversion. .

Note that the operator can freely select between fixed color determination and gradation color determination from the operation section. Alternatively, it is also possible to change it by software using color data (color data before color conversion) input from an input device such as a digitizer.

These selectors 52bR, 52b, 52b
8, upper limit ratio registers 58bR, 58bG, 58bF3, and lower limit ratio registers 59bR, 59bG, 59bB set by the CPU 20, R'
The upper and lower limits of G' and B' are determined by the multiplier 5.
6bR, 56bo, 56b8 and 57bR, 57
b, , 57b8 and set as the upper and lower limit values in the window comparators 60bR, 60b, , 60b8.

Window comparator 60bR, 60bo,
At 60b8, it is determined by AND gate 6lb whether the data of the main color falls within a certain range and the two colors other than the main color fall within a certain range. The register 67b can set "BI" regardless of the judgment signal by the enable signal 68b of the judgment section. In this case, the color to be converted exists in the part where "l" is set.

The above configuration enables fixed color determination or gradation color determination for a plurality of areas.

FIG. 9 is a block diagram of an example of a color conversion circuit.

This circuit selects the color-converted signal or the original signal based on the output 7b of the color determining section 5b.

In FIG. 9, the color conversion unit 25b includes a selector lllb and registers 1 1 2bB + +1!2 that set the respective ratios of the converted colors to the principal color data (maximum value in this case).
bR2, ll2b,,, Il2b,2, l
l2bB,,ll2b8. , multiplier 113bR, 1
13bo, 113b8, selector 114bR, l1
4bo, l14b8, selector 115bR, 115b,
, 115b8, AND gate 32b1 Ar50, Ar60 generated based on the area signal Ar' 24 in FIG.
, Ar70 selector lllb, multiplier 113bR, 1l3bol.
113b8, selector 114bR, 114b,,ll4
Selector 117b, l12bR, 11 set to b8
2bo, 112b8, 116bR, 116b,
, 116b8, and a delay circuit 118b.

Next, we will explain the actual movement.

The selector 11lb receives input signals R, N2lb, G
, N' 22b, B , one of N' 23b
One (main color)? The selection is made according to the selection signal S5. Here, the signal S5 is the area signal A r40 for the two data set by the CPU 20.
This occurs by selecting either B. In this way, color conversion processing for multiple areas becomes possible.

The signal selected by the selector 11lb is sent to the multiplier 113.
Multiplication with the register value set by the CPU 20 is performed in bR, ll3b, , 113b8.

Here too, the area signal Ar5Q has two register values 112
bR, -112bR■, 112b,, -112
selector l12bR.bo2, 112bB, .1l2b8■ respectively. By selecting from 112bo and 112b, different color conversion processing can be performed for a plurality of areas.

Next, selectors 114bR, 114bo, l14
The selector 116bR,
Either one of the fixed values selected in 116bG and 116bB is selected by mode signal S6. Is this also a mode? No. S6 receives the area signal Ar in the same manner as S5.
The one selected by 60 is used.

Finally, selectors l15bR, 115bo, and 115b8 use the select signal SB to select RINGIN I.
BIN (RIN I GIN I BIN delayed and timing adjusted) and selector 114bR, 11
4bo, l14bB output is selected, and R
Output as OU■+GOLJT+BOUT.

Also, the hit signal H OIJT is also R O U T +GO
U■+ Output in synchronization with BOUT.

Here, the selector signal SB is a delay product obtained by ANDing the color determination result 34b and the color conversion enable signal BHi34b. If a non-rectangular enable signal such as the dotted line in FIG. 10 is input as the BHi signal, color conversion processing can be performed on a non-rectangular area. In this case, the area signal is an area like the one-dot chain line, that is, the top left (Fig. 10a), the top right (Fig. 10 b), the bottom left (C), and the bottom left determined from the dotted lines. (Fig. 10, d). Further, the non-rectangular area signal BHi is input from an input device such as a digitizer.

When performing color conversion using this non-rectangular enable signal,
Since the enabled area can be specified along the boundary of the area to be converted, the threshold for color detection can be expanded compared to conventional color conversion using rectangles. Therefore, the detection ability is further improved, and an output image subjected to gradation color conversion with high accuracy can be obtained.

From the above, color conversion with brightness according to the main color of the color judgment unit 5b (for example, when converting red to blue, light red is converted to light blue and dark red is converted to dark blue) or fixed value color conversion You can freely perform any of the following for multiple areas.

Furthermore, as will be described later, the hit signal H. Mosaic processing based on UT only for specific color areas (non-rectangular or rectangular),
Texturing processing, trimming processing, masking processing, processing, etc. can be performed.

Then, as shown in FIG. 2, the output 103 of the color conversion circuit B,
104 and 105 are a logarithmic conversion circuit C1 for converting image data proportional to reflectance into density data; and is sent to an external device interface M for communicating data with external devices via cables 135, 136, and 137.

Next, the color image data proportional to the input light amount is
The signal is input to a logarithmic conversion circuit C (FIG. 2) which performs processing to match the luminosity characteristics of the human eye.

Here, white = 00H, black = FFH are converted as much as possible, and the image sources input to the image reading sensor are, for example, a normal reflective original, a transparent original such as a film projector, and even the same transparent original as a negative film or positive. Since the input gamma characteristics differ depending on the film or the sensitivity of the film and the exposure state, the difference shown in FIG. 11(a).
As shown in (b), there are a plurality of LUTs (look-up tables) for logarithmic conversion, which are used depending on the purpose. Switching is done using the signal line f go, I! gl, I!
g2, and as the I/O boat of the CPU22,
This is performed by inputting an instruction from an operation unit or the like (FIG. 2). Here, the data output for each B, G, and R corresponds to the density value of the output image, and the data output for each B (blue), G
(green). Since each R (red) signal corresponds to the toner amount of Y (yellow), M (magenta), and C (cyan), the subsequent image data is associated with yellow, magenta, and cyan.

Next, each color component image data from the original image obtained by logarithmic transformation, that is, the yellow component. The color correction circuit D performs color correction on the magenta and cyan components as described below. As shown in Fig. 13, the spectral characteristics of the color separation filters arranged for each pixel in the color reading sensor have unnecessary transmission areas such as the shaded areas, and on the other hand, for example, the color transferred to the transfer paper Toner (Y, M, C)
It is also well known that the fluorophore also has unnecessary absorption components as shown in Figure 14. Therefore, each color component image data Yi, M
Masking correction is well known in which color correction is performed by calculating a linear equation for each color with respect to i and Ci. Furthermore, by Yi, Mi, Ci, Min (Yi, Mi, Ci) (Yi, M
(minimum value of i, Ci), set this as black and then add black toner (smearing);
Undercolor removal (UCR) operations are also often performed in which the amount of each coloring material added is reduced depending on the added black component. In Figure 12(a),
The circuit configuration of a color correction circuit D that performs masking, smearing, and UCR is shown. The characteristics of this configuration are: ■ It has two masking matrices, and can be switched to high distance with "1/0" of one signal line. ■ One signal line "I" with and without UCR. /O" can be switched at high speed. (2) It has two circuits for determining the amount of smear, and can be switched at high speed with "l/0".

First, prior to image reading, a desired first matrix coefficient M1 and a desired second matrix coefficient M2 are set via a bus connected to the CPU 22. In this example, M1 is stored in registers 87d to 95d, and M2 is stored in registers 96d to 104.
It is set to d.

Also, llld~122d, 135d, 131d, 13
6d is a selector, which selects A when the S terminal is "1" and selects B when the S terminal is "O". Therefore, when selecting matrix M1, switching signal MAREA364="
When matrix M2 is selected, it is set to "0".

Further, 123d is a selector and a selection signal C. ,C
, (366d). 367d) in Figure 12 (
Outputs a, b, and c are obtained based on the truth table of b). Selection signal C. r C I and C2 correspond to color signals to be output, for example, in the order of Y, M, C, Bk (
c2, c,, co) = (01 o, o),
(o, o, t), (0, l, O), (
1, 0, O), and further as a monochrome signal (0,
1), a desired color-corrected color signal is obtained. Now (Co.CII C2) = (0, 0
．． 0) and MAREA="l", the outputs (a, b, c) of the selector 123d contain the contents of the registers 87d, 88d, 89d, and therefore (ay+,
-byl, 1 Cc. ) is output. On the other hand, Min (Yi, Mi,
Ci) = black component signal 374d calculated as k
is subjected to the linear transformation Y==ax-b (a, b are constants) at 137d, and subtractors 124d, 125d, 1
It is input to the B input of 26d. Each subtractor 124d-12
6d, Y=Yi − (ak− b
), M = M i − (ak − b
), C = C i - (ak-b) are calculated, and are sent to a multiplier 127d for masking operation via signal lines 377d, 378d, and 379d.
It is input to 128d and 129d.

Multipliers 127d, 128d, and 129d each have (an, 1bMe.Cc.) at their A inputs.
, B input has the above-mentioned (Y i − (ak −
b), M i - (ak - b)
, Ci one (ak-b)) = (Yi, Mi,
As is clear from the figure, since Cil is input,
Output D. U1 has the condition of C2=0 (Y or M
Or C) YOIJT? iX (aye) 10M
iX (-bM+) +CiX (-Cc.) is obtained, and yellow image data subjected to masking color correction and undercolor removal processing is obtained. Similarly, M■ U7 =Yix(-ayz)+MiX(-bM2
)+CiX(-CC2)COLIT=YIX( a
Y3) + MIX ( bM3) + CIX ( CC
3) is D. Output to U1. Color selection is done according to the order of output to the color printer (Co, C+, C2
) is controlled by the CPU 22 according to the table in FIG. 12(b). Registers 105d to 107d, 108
d to 110d are registers for forming a monochrome image, and based on the same principle as the above-mentioned masking color correction, MONO
=k, Yi+I! It is obtained by weighted addition for each color using I Mi+rrz Ci.

Also, when outputting Bk, C2 (368) input as a switching signal to the selector 131d causes C2 to be 1%.Therefore, in the primary converter 133d, it undergoes a primary conversion such that Y=cx-d, and is output from the selector 131d. Also,
BkMJ110 is a black component signal output to the outline of a black character based on the output of a character image area separation circuit (2) to be described later. Color switching signal C.

C, , C2' 366 to 368 are the CPU bus 22
MARE
A364 is output from the area signal generation circuit 364.

The gate circuits 150d to 153d output a signal C when DHi is "1" based on a non-rectangular area signal DHil22 read from a binary memory circuit (bitmap memory) L537, which will be described later. ,C,,C2 −“l, l,
This is a circuit that controls so that data for a mono image is automatically output.

Character image area separation circuit Next, the character image area separation circuit I uses the read image data to determine whether the image data is a character or an image, and whether it is chromatic or achromatic. This is a circuit that determines whether The flow of the process will be explained using FIG. 15.

Red (R) 103, green (G) 104, and blue (
B) 105 is the minimum value detection circuit M, N (R, G, B) 1
011 and maximum value detection circuit Max (R, G,
B) Input to 1021. In each block, the maximum value and minimum value are selected from the three types of input luminance signals R, G, and H. A subtraction circuit 1041 calculates the difference between the selected signals. If the difference is large, that is, the input R, G, . If B is not uniform, the signal is not an achromatic color that indicates black and white, but is a chromatic color that is biased toward some color. Naturally, if this value is small, it means that the R, G, and B signals are at approximately the same level, and it can be seen that the signal is an achromatic signal and not a signal that is biased towards any color. This difference signal is output to the delay circuit Q as a gray signal GR124.

Further, the comparator 112I compares this difference with a threshold value arbitrarily set in the register 1111 by the CPU, and outputs the comparison result to the delay circuit Q as a gray determination signal GRBil26. These GR125, GRBi
After the signal of l26 is matched in phase with other signals in a delay circuit Q, it is input to a character image correction circuit E, which will be described later, and is used as a processing determination signal.

The minimum value signal obtained by M I N (R, G, B) lOII is also input to the edge emphasizing circuit 103I.The edge emphasizing circuit performs the following calculation using front and rear pixel data in the main scanning direction. Edge enhancement is performed.

Dour: Image data Di after edge enhancement
: i-th pixel data Note that edge enhancement is not necessarily limited to the above method, and other known techniques may be used. The image signal edge-enhanced in the main scanning direction is then
And the average value calculation within the 3×3 window is performed using a 5×5 average of 109I and a 3×3 average of 1101. Line memories 1051-1081 are delay memories in the sub-scanning direction for performing averaging processing. The 5×5 average value calculated in 109I is then combined with an offset value independently set in an offset section connected to CPUBUS (not shown) and adders 115I, 119I,
It is added at 1241. The added 5×5 average value is input to limiter 1 113I, limiter 2 118I, and limiter 3 123I. Each limiter is connected to a CPU bus (not shown), and is configured so that the limiter value can be set independently.
If the average value is greater than the set limiter value, the output is clipped at the limiter value. The output signal from each limiter is
Comparator l 1161, comparator 2 respectively
1211, converter 3 is input to 1261. First, in the converter 1 1161, the output signal of the limiter 1 113I is compared with the output from the 3×3 average 110I. Compared Comparators 1 1
The output of 16I should be matched in phase with the output signal from halftone area discrimination circuit 122I, which will be described later.
is input. This binarized signal is binarized using an average value to prevent distortion and skipping due to MTF at a certain density or higher, and the halftone dots of the halftone image can also be binarized. A 3×3 low-pass filter is used to cut high frequency components of the halftone image so that they are not detected. Next, the output signal of comparator 2 (121T) is processed so that it can be discriminated by the halftone area discriminating circuit 122I in the subsequent stage.
Detecting high frequency components of an image (2 with through image data)
Valuation is being carried out. In the halftone area discrimination circuit 122I,
Since the halftone dot image is composed of a collection of dots, detection is performed by confirming the dots from the direction of the edge and counting the number of dots around the edge. A detailed explanation of the halftone area determination circuit 1221 will be omitted since it is not the gist of this patent.

The results determined by the halftone dot area discriminating circuit and the signal from the delay circuit 117 are used in an OR gate 1291.
After removing the erroneous judgment, the erroneous judgment is removed by the erroneous judgment removal circuit 130I, and then outputted to the AND gate 132I.

In this false judgment removal circuit 1301, taking advantage of the characteristics that characters and the like are thin and images have a wide area, first, the image area of the binarized signal is narrowed, and an isolated image area is taken. Specifically, for the center pixel Xij, the surrounding area is 1 mm.
When even one pixel other than the image exists within the corner area, the center pixel is determined to be outside the image. After removing the image area of the isolated point in this way, thickening processing is performed to restore the thin image area to its original size. Similarly, the output of the halftone dot discriminating circuit 122I is directly input to the erroneous judgment removal circuit 131I, where thinning processing and thickening processing are performed. Here, the mask size for the thinning process is the same as the mask size for the fattening process, or by making the mask size for the fattening process larger, the determination results when fattening are made to cross each other. Specifically, both the false judgment removal circuits 130I and 1311 are thinned using a 17 x 17 pixel mask, further thinned using a 5 x 5 mask, and then thickened using a 34 x 34 pixel mask. It is being said. The output signal SCRN signal 127 from the misjudgment removal circuit 1311 is a discrimination signal for smoothing only the halftone dot determination section in a character image correction circuit E, which will be described later, to prevent moiré in the read image.

Next, the output signal from the converter 3 1261 must be processed to sharpen the characters in the subsequent stage (the outline of the input image signal is extracted). As an extraction method, the output of the binarized comparator 3 1261 is thinned and thickened in 5×5 blocks, and the difference area between the fattened signal and the thinned signal is used as the contour. . The contour signal extracted by such a method is passed through a delay circuit 128I in order to match the phase with the mask signal output from the false judgment removal circuit 130I, and then an AND gate 132■ determines that the contour signal is a mask signal and is an image. The contour signal in the part where the characters are printed is masked, and only the contour signal in the original character part is output. The output from AND gate 1321 is then output to contour regenerating section 133I.

Contour Regeneration Unit> The contour regeneration unit 133I processes pixels that are not determined to be character contour parts to become character contour parts based on the information of surrounding pixels, and as a result, converts MjArl24 into a character image correction circuit. The data is sent to E and the processing described below is performed.

Specifically, as shown in Figure 16, bold letters ((a) in the same figure)
, the character determination unit determines the dotted line part in (b) as a character and performs the processing described below.
Regarding C)), the character part becomes as shown in the dotted line part in FIG. 10(d), and if the processing described below is performed, it may become unsightly due to misjudgment. In order to prevent this, processing is performed to treat parts that are not determined as characters based on surrounding information.

Specifically, by making the diagonal line part the character part, the character part becomes as shown in the dotted line part (e) in the same figure, which reduces misjudgments even for characters that are so thin that they are difficult to detect, leading to improved image quality. .

FIG. 17 is a diagram showing how surrounding information is used to regenerate a pixel of interest into a character portion.

(a) to (d) are 3 x 3 blocks, with the pixel of interest as the center, and both vertical, horizontal, and diagonal text portions (S, S2 are both "l")
When , the pixel of interest is set as a character portion regardless of the information of the pixel of interest. On the other hand, (e) to (h) are 5x5 blocks, with one pixel centered around the pixel of interest, and both the vertical, horizontal, and diagonal directions are character parts (S, S2 are "l"), regardless of the information of the pixel of interest. is the character part. Like this 2
The structure of tiered blocks (multiple types of blocks) makes it possible to handle a wide range of errors.

FIGS. 18 and 19 are circuits for realizing the process shown in FIG. 17. The circuits shown in FIGS. 18 and 19 include line memories l 64i to 167i, DF/Fs 104i to 126is for obtaining information around the pixel of interest, and FIG. 17(a) to
AND gates 1461 to 153 to realize (h)
i and OR game} 154i.

Figure 17 (
Information on Sl and S2 in a) to (h) is extracted. Furthermore, registers 146i to 153i correspond to the processes of (a) to (h), respectively.
6 2 i can independently control enable and disable.

AND circuit 146i=153i and FIG. 17(a) ~(
The correspondence relationship in h) is as follows.

Figure 20 shows line memory 1 6 4 i Nl 6
7i is a timing chart of W1 (ENI) and RE (EN2). This means that ENI and EN2 appear at the same timing when the size is the same, or when it is enlarged (for example, 200% to 30%).
0%), WE is written once in two thinned lines.

This expands the size of FIGS. 17(a) to (h).

This is because when enlarging, the information that comes in here comes as an image enlarged only in the sub-scanning direction, so by increasing the size of (a) to (h), processing can be done with the same size image even when enlarging. Is going.

Character Image Correction Circuit> The character image correction circuit E performs the following processing on black characters, color characters, halftone images, and halftone images, respectively, based on the determination signal generated by the character image area separation circuit I described above.

[Processing 1] Processing regarding black characters (1-1) Signal Bk obtained by black-mark extraction as video
Using Mjll2 (1-2) Y, M, C data are multivalued achromatic chromaticity signals G
Subtraction is performed according to R125 or the set value. On the other hand, B
The k data is a multivalued achromatic chromaticity signal GR125. If << is added according to the set value (1-3) Edge emphasis is performed (1-4) Black characters are printed out at 400 lines (400 dpi) (1- Perform 53 color residual removal processing [Processing 2] Processing related to colored characters (2-1) Perform edge emphasis (2-2) Color characters are 400 lines (400 dpi)
[Processing 3] Processing related to halftone images (3-1) Smoothing to prevent moiré (main scanning 2
[Processing 4] Processing related to halftone images (4-13 Smoothing (2 pixels each in the main scanning direction) or Through can be selected.

Next, a circuit that performs the above processing will be explained.

FIG. 21 is a block diagram of the character image correction section E.

The circuit of FIG. 21 uses the video input signal 111 or BkM
A selector 6e that selects 112, an AND gate 6e' that generates a signal that controls the selector, a block 16e that performs a residual color removal process to be described later, an AND gate 16e that generates an enable signal for the same process, and a GR signal 125.
and a multiplier 9e that multiplies the I/O port setting value 10e.
', a selector lie that selects the multiplication result lOe or the set value 7e of the I/O port, a multiplier 15e that multiplies the output 13e of the selector 6e and the output 14e of lie, XOR
Game} 20e, AND game} 22e, adder/subtractor 2
4e, Line memory 2 that delays 1 line data
6e, 28e, edge emphasis block 30e, smoothing block 31e, selector 33e for selecting through data or smoothing data, delay circuit 32e for synchronizing control signals of the selector, selecting result of edge emphasis or smoothing. A selector 42e, a delay circuit 36e for synchronizing control signals of the selector, an OR gate 39e, an AND gate 41e. Inverter circuit 44 for outputting a 400-line (dpi) signal ('L' output) to the character determination section
e, an AND circuit 46e, an OR circuit 48e, and a delay circuit 43e for synchronizing the video output 113 and the LCHG 49e. Further, the character image correction section E is connected to the CPU bus 22 via the I/O port 1e.

Below is [1] Color residual removal processing that removes the color signal remaining around the edge of the black text area, and a certain percentage is subtracted from the Y, M, and C data of the black text area determination section, and a certain percentage is subtracted from the Bk data. [2] Edge enhancement for the text part, smoothing for the halftone judgment part, and part where through data is selected for other gradation images, [3] L for the text part.
The process is divided into three parts, each of which is a part where the CHG signal is set to "L" (printed at 400 dpi), and each part will be explained.

[1] Remaining color removal processing and addition/subtraction processing Here, processing is performed for the area where both the signal GRBil26 indicating that it is an achromatic color and the signal MjAR124 indicating that it is a text area are active, that is, the edge area of the black character and its surrounding area, The Y, M, and C components protruding from the edges of black characters are removed, and the edges are filled in. ing.

Next, a detailed explanation of the operation will be given.

This process is subject to character part determination (MjARl24="1
”), this is performed only when the text is black (GRBil26="1") and the color mode is set (DHil22="0").
(“1”) and color characters (GRBi="0").

When scanning a document for recording color Y, M, or C, selector 6e selects video input 111 (I/
O-6 (set to 0'' in 5e). Data to be subtracted from video 8e is generated in 5e, 20e, 22e, and 17e.

For example, if "0" is set in I/O-3}2e, selector output data 13e and I/O-1
Multiplication by the value set in 7e is performed in multiplier 15e. Here, data 18e is generated that is O-1 times as large as data 13e. By setting 1 to registers 9e and 25e, the two's complement data of 18e becomes 17e, 20e, 2
Generated in 2e. Finally, the addition 23e of 8e and 23e in the adder/subtractor 24e is a two's complement, so it is actually 17e-
8e is subtracted and output from 25e.

When "1" is set in I/O-312e, B data is selected by selector lie.

At this time, the value set at I/O-210e is set at 9e for the multi-value achromatic signal GR125 (a signal that takes a large value if it is close to an achromatic color) generated by the character image area separation circuit I. The multiplied value is used as the multiplier of 13e. When this mode is used, the coefficients can be changed independently for each of the colors Y, M, and C, and the amount of subtraction can be changed depending on the achromatic degree.

When scanning recording color Bk, selector 6e selects BkMj1.
12 is selected (“1” in I/O-65e
set). 15e, 20e, 22e,
At 17e, data to be added to video 17e is generated. The difference from the above Y, M, and C cases is I/O-4
, 9 By setting "0" to e, this results in 2
3e=8e, Ci=O, 17e+8e becomes 25e
It is output from How to generate coefficient 14e is Y, M, C
It's the same as time. Also, I/O-312el:'l
In the mode where " is set, the coefficient changes according to the achromatic degree. Specifically, when the achromatic degree is large, the addition amount is thick, and when it is small, it is small.

This process is illustrated in FIG. 22. (a) and (c) are enlarged views of the shaded portion of the black letter N.

For Y, M, and C data, subtraction from the video is performed when the character signal part is "1" (Figure (b)), and for Bk data, the character signal part is "1". is added to the video ((d) in the same figure). In this figure, 13e=1
8e, that is, the Y, M, and C data of the character portion are 0, and the Bk data is twice that of the video.

Through this processing, the outline of black characters is printed in almost a single black color, but the Y, M, and C data outside the outline signal (see Figure 22 (b)
) The * mark shown in ) remains around the letters as residual color, making it unsightly.

The color removal process removes the remaining color.

This processing extends to the area of the text area,
In addition, for pixels where the video data 13e is smaller than the conversion value set by the CPU, that is, outside the text area, where there is a possibility of color remaining, the process takes the minimum value of 3 or 5 pixels before and after. be.

Next, the explanation will be supplemented using a circuit.

Figure 23 shows a character area expansion circuit that works to expand the character area.
ND gate 69e, 71e, 73e, 75e,
It is composed of an OR gate 77e.

All I/O ports 70e, 72e, 74e, 76e
When MjA r124 is set to "l", the signals expanded by two pixels in the front and rear in the main scanning direction are sent to the I/O ports 70e, 75e"0", 71e, 73.
When e is "1", the signal expanded one pixel forward and backward in the main scanning direction is S.
Output from ig2 18e.

Next, the remaining color removal processing circuit 16e will be explained.

FIG. 24 is a circuit diagram of residual color removal processing.

In FIG. 24, 57e is a 3-pixel min select circuit that selects the minimum value of a total of 3 pixels, including the pixel of interest and 1 pixels before and after it, for the input signal 13e, and 58e is the input signal 13
For e, select the maximum value of a total of five pixels, including the pixel of interest and two pixels before and after it. A 5-pixel min select circuit 55e is a comparator that compares the magnitude of the input signal 13e and the I/O-18 (54e), and outputs l when 54e is greater. 61e, 62e are selectors, 53e, 5
3'e is an OR gate, and 63e is a NAND gate.

In the above configuration, the selector 60e selects 3 pixels min or 5 pixels min based on the value of I/O-19 from the CPU bus. With 5 pixels min, the effect of color residual removal is greater. This can be selected by manual setting by the operator or automatic setting by the CPU.

The selector 62e is configured so that the output of the NAND gate 63e is “0”.
'', that is, the comparator 55e determines that the video data 13e is smaller than the register value 54e, and it is within the range of expanding the character part signal, and if 17'e is 1, the A side is selected, otherwise the video data 13e is determined to be smaller than the register value 54e. B side is selected. (However, at this time, registers 52e and 64e are 11"
When the B side is selected (the register 52'e is 'o'),
Through data is output as 8e.

The EICON 50e can be used in place of the converter 55e, for example, when a signal obtained by binarizing a luminance signal is input.

FIG. 25 shows the area where the above two processes have been applied. 25(a) is the black character N, and FIG. 25(b) is the area determined as a character in the Y, M, C data, which is the density data of the shaded area, that is, the character determination part (Kaoru 2,
%3, cloudy 6, +7) becomes O by subtraction processing, -
%l, +4 becomes bitter 1 ← SO, cloud 4 ← Kaoru 5 by the color residual removal process, and as a result becomes 0, and FIG. 25 (C) is obtained.

On the other hand, for B and data as shown in Figure 25(d),
Only the addition process is performed in the character determination section (Kan 8, Ku 9, Kumo 10, Kumo 11), resulting in an output with a black ring as shown in FIG. 25.

Note that no changes are made to the colored characters, as shown in FIG. 25(f).

[2] Edge Emphasis or Smoothing Process Here, processing is performed to output edge emphasis for the character determination section, smoothing for the halftone dot section, and outputting through for the others.

Since character part -+MjARI24 is "1", 25e
, 27e, 29e generated from the 3 line signals.
The output of the x3 edge enhancement 30e is selected by the selector 42e and output from 43e. Note that the edge enhancement here is obtained from a matrix and calculation formula as shown in FIG.

Halftone part → SCRN35e is "l", M j A R 2
Since 1e is "0", the smoothing 31e applied to 27e is the selector 33e, 42
It is output at e. Note that smoothing is the 27th
As shown in the figure, when the pixel of interest is vN (vN +V N
+1)/2 as vN data, that is, smoothing of two main scanning pixels. This prevents moiré that may occur in the halftone dot area.

Other→Other portions refers to processing for areas that are neither character portions (character outlines) nor halftone dot portions, specifically, midtone portions. At this time, MjAR124 and SCRN35e
Both are “0”, so 27eΦ. The data is output as is from the video output 43e.

When the characters are colored characters, the above two processes are not performed even in the character determination section.

In the embodiment, an example was shown in which color residual removal was performed only in the main scanning direction, but color residual removal processing may be performed in both the main scanning and sub-scanning directions.

[3] Text section 400 lines (dpi) output processing video output 1
13, LCHG140 is output from 48e. Specifically, the inverted signal of MjAR 124 is output in synchronization with signal 43e. LCHG=0 for the character portion, and 200/400-“1” for other portions.

As a result, the character part determination part, specifically the character outline part, is 4
00 line (dpi), and the others are printed at 200 line (dpi).

Next, the character image synthesis circuit F will be explained.

FIG. 28(a) is a block diagram of a circuit for processing and modifying images using binary signals in this apparatus. The color image data 138 inputted from the image data input section is inputted to the V input of the 3tol selector 45.

The other two inputs A and B of the 3tol selector 45f contain lower parts (A, . . . ) of the data read out from the memory 43f.
B n) Of 555f, A has All, B has B,
is latched by VCLK117 in latch 44f and input. Therefore, the output Y of the selector 45f has the selection power X. , X,, Jl, J2
Either V, A, or B is output based on (11
4).

In this embodiment, data Xn is the top two data in memory.
This bit is a mode signal that determines processing and modification. 139 is a code signal output from the area signal generation circuit.
It is controlled to switch in synchronization with 117, and the memory 43f
is entered as the address of

That is, for example, (X
lO, A10・B to) = (01+ A IO+
As shown in FIG. 29(b), in synchronization with the scanning of line l in the main scanning direction, "IO" is written from point P to point Q in the code signal 139, and "IO" is written from point Q to point R in the code signal 139. 0'', data XIl=(
0. 1) is read out, and at the same time, data (A+o.B+o) is latched and output to (A., B.). The truth table of the 3tol selector 45f is shown in Figure 28 (C
) as shown in <, (X +, X o) = (0.
1) is case (B), and if Jl is “1”, then A
input to Y, therefore Y has a constant A IQ, and J1 is “
0'' means that ■the input is set to Y, and therefore the input color image data is output as is to the output 114.In this way, for example, for a color image of an apple as shown in FIG. 29(b), The so-called tweezers character synthesis of the character part with the value (AI.) is realized.Similarly, (
XI. When X o) = (1.0) and a signal like Jl in FIG. 29(C) is input to the binary input, FIF047f to 49f1 and circuit 46f (details in FIG. 28(b)) A signal as shown in Figure 12 is generated, and if the truth table in Figure 28(C) is followed, the characters will be output as cross marks in the apple image as shown in the figure (outline or outline). bag letters).

Similarly, in FIG. 28(D), the rectangular area inside the apple is (
The inner characters are output with a density of (AI,). In the same figure (A), (Xl, xo) =
(0, O), i.e. for any Jl,
Depending on the binary signal, there is also control in which nothing is done in response to a change in J2.

The signal with expanded width input to J2 is shown in Fig. 28(b).
According to , the size is expanded by 3×3 pixels, but it is easy to increase the size even further by adding a hardware circuit.

Also, CO and CI (366, 367) output from the I/O port 501 in FIG. 2 in association with the output colors (Y, M, C, Bk) to be printed are stored in the memory 4.
It is input to the lower 2 bits of the address of 3f, and therefore "0, 0", corresponding to the output of Y, M, C, Bk.
It changes as “0. 1”, “1, O”, and “1. 1”, so for example, when outputting yellow (Y), it changes as 0, 4,
8,12. 16...Address, magenta (M) is 1
, 5, 9, 13, l7... address, cyan (C
) is 2, 6, 10, 14. 18... Address, black (Bk) is 3, 7, 11, 15. 1
9...An address is selected. Therefore, according to the operation instructions on the operation panel, which will be described later, the area and the address corresponding to the area code signal 139 that determines the corresponding memory address within the area, for example,
A3, A4) = (αl, α2, α3, α4), (Bl
, B2, B3, B4) = (βl, β2, β3,
β4) is written in advance, and when the Jl signal changes as shown in FIG. 29(D), the section where Jl is “Lo” is (
The color is determined by mixing Y, M, C, Bk) = (αl, α2, α3, α4), and when Jl is “Hi”, (Y,
M, C, Bk) The color is determined by combining (βl, β2, β3, β4). In other words, the output color can be arbitrarily determined based on the memory contents. On the other hand, on the operation panel described below,
Y, M, C, and Bk are each adjusted or set in percent (%). That is, since each gradation has 8 bits, the numerical value is 00 to 255, so a 1% fluctuation is a digital value of 2.55.

The setting value is (Y, M, C, Bk) = (Y%, m%, C%
, k%), the values to be set (i.e., the values written to memory) are (2.55Y, 2.55Y), respectively.
m, 2.55c, 2.55k), and in reality, the rounded integer is written into a predetermined memory. Furthermore, if the adjustment mechanism is used to adjust in %, an addition of 2.55Δ will be added to the variation of Δ% (concentration
All you have to do is write the value obtained by subtracting (thinning) or subtracting (thinning) into memory.

In the truth table of FIG. 28(C), the i column is an input/output table for characters, image gradation, and resolution switching signal LCHG149, and A or B outputs Y depending on X,, Xo, Jl, and J2. When it is output to Y, it is output as "0", and when it is output to Y, the input is output as is. LCHG149 is a signal for switching the print density during printing, for example, when LCHG="0", for example, 400 dpi, L
When CHG="1", print at 200 dpi. Therefore, when A or B is selected, LCHG = 0 means that the inner area of the synthesized characters is printed at 400 dpi, and the area other than the characters is printed at 200 dpi, and the characters maintain high resolution and are sharp. The halftone part maintains high gradation,
It is controlled to output smoothly. This is why, as described above, the LCHG 140 outputs the output from the character image correction circuit E based on MJAR, which is the output from the character/image separation circuit I.

Image processing and editing circuit> Next, image signal 1 after receiving color balance adjustment at P
15 and the gradation resolution switching signal LCHG141 are input to the image processing and editing circuit G. A rough schematic diagram of the image editing processing circuit G is shown in FIG.

Input image signal l15, gradation resolution switching signal LC
The HG 141 is first input to the texture processing section 101g. The texture processing section is roughly divided into a memory section 103g that stores texture patterns, memories RD and WR that control them, an address control section 104g, and an arithmetic circuit 105g that performs modulation processing on input image data according to the stored pattern. has been done. The image data processed by the texture processing section 101g is then subjected to scaling, mosaic, and taber processing section 1.
02g. The variable magnification, mosaic, and taper processing section 102g has double buffer memory 105g, 10
6g and a processing/control unit 107g, various processes are independently performed and output by the CPU.

Here, the texture processing unit 101g and the scaling, mosaic, and taper processing unit 102g perform texture processing on independent areas using GHth (119) and GHi2 (149), which are enable signals for each process sent from the switching circuit N. , and is configured to perform mosaic processing.

Furthermore, the gradation resolution switching signal LCHG signal 141 input together with the image data 155 is processed in various processes while matching the phase with the image signal.

The image processing/editing circuit G will be explained in detail below.

<Texture processing section> Texture processing is a process of cyclically reading out a pattern written in memory and applying modulation to the video. For example, the image shown in FIG. The output image shown in FIG. 2(c) is generated by modulating the image in a pattern such as that shown in FIG.

FIG. 32 is a diagram illustrating the texture processing circuit.

Below, modulation data 2 to texture memory 113g
18g writing section and 113g texture memory
216g of data and 215g of image data (
Texture processing) will be explained separately.

[Data writing section to texture memory 113g] When writing data, masking, undercolor removal, and smearing are performed, and data is input from 201g. This data is selected by selector 202g. On the other hand, selector 208
At g, data 220g is selected and memory 113g is selected.
is input to the WE and the enable signal of the driver 203g. The memory address is generated by a vertical counter 212g that counts up in synchronization with the horizontal synchronization signal HSYNC and a horizontal counter 211g that counts up in synchronization with the image clock and VCK.
is selected and input to the address of the memory 113g. In this way, the density pattern of the input image is stored in the memory 113.
written to g. Typically, this pattern is located and written by an input device, such as a digitizer.

[Writing data by CPU] CPU data is selected by the selector 202g.

On the other hand, A is selected by the selector 208g, and the memory 11
3g and the enable signal of the driver 203g. As the memory address, A is selected by the selector 210g and inputted to the address of the memory 113g. thus,
An arbitrary density pattern is written into memory.

[Calculation unit for texture memory 113g data 216g and image data 215g] This calculation is realized by a calculation unit 215g. This arithmetic unit here consists of a multiplier. Data 216g and 201 only where enable signal 128g is active
An operation with g is performed, and when the disable is enabled, the signal 201 becomes a through state.

Also, 300g and 301g are XOR and OR gates, respectively, and register 304 is a part that generates an enable signal using MJ signal 308g, that is, a character synthesis signal.
g When "0" is set in the register 1305g, texture processing is applied to areas other than those containing composite character signals.On the other hand, registers 304g "0" and 305g are "0".
When set in the register, texture processing is applied only to the part where the composite character signal is included.

302g is a portion that generates an enable signal using a GHil signal 307g, that is, a non-rectangular signal. When the register 306g is "0", texture processing is performed only where the GHil signal is enabled. At this time enable 12
If 8 is kept active, non-rectangular texture processing is performed that is not affected by non-rectangular signals, that is, synchronized with HSNC.If enable signal GHil and enable 128 are made the same, texture processing is performed that is synchronized with non-rectangular signals. Become.

For example, if a 3 lb bit signal is used for GHil, texture processing can be performed only on a certain color.

The LCHG, N signal 141g is a gradation resolution switching signal, which is delayed by the amount of delay in the arithmetic unit 215g, and then output to LCHG.
. ,,350g.

Mosaic, scaling, and taper processing unit> Next, the general operation of the mosaic, scaling, and taper processing unit Gl2 of the image processing/editing circuit G will be described using FIG. 33.

Image data 1 26g and LCHG signal 350g input to the mosaic, scaling, and taper processing section 102g are as follows:
First, it is input to the mosaic processing unit 401g. The mosaic processing unit 401g uses the Mj signal 145 output from the character synthesis circuit F and the area signal GHi 214 from the switching circuit N.
9. After the mosaic clock MCLK from the mosaic processing control unit 402g determines whether or not to perform mosaic processing, the size of the mosaic in the main scanning direction, and the composition of characters, 1t
It is input to the o2 selector-403g. Here, the main scanning direction size for mosaic processing is the mosaic clock MCL.
It is made variable by controlling K. Control of the mosaic clock MCLK will be explained in detail later.

1 to2 selector-403g, HSYNC118
The input image signal and LCHG signal are output to either Yl or Y2 by the line memory select signal LMSEL whose frequency is divided by the D flip-flop 406G.

1 Output from Yl of to2 selector-403g is output from line memory A404g and 2t01 selector-407
Connected to A of g. In addition, the output from Y2 is line memory 8405g and 2t01 selector-407.
Connected to B of g. When an image is sent from selector 403g to line memory A, line memory A
404g is in write mode and line memory 8
405g is in read mode. Similarly, when an image is sent to the line memory 8405g from the selector 403g, the line memory B is in the write mode and the line memory A 404g is in the read mode. In this way, the image data read out alternately from the line memory A 404g and the line memory 8405g is 2tol.
The selector 407g outputs continuous image data while switching based on the inverted signal of the LMSEL signal output from the D flip-flop 406g. The output image signal from the 2tol selector 407g is then sent to the enlargement processing section 414.
After a predetermined enlargement process is performed in g, the image is output.

Next, write/read control of these memories will be described. First, when writing or reading, line memory A
404g The address given to the 1-line memory B 405g is synchronized with HSYNC, which is the reference for one scan, and is synchronized with the image C
Up/down counters 409g, 41 to increment and decrement in synchronization with LK.
It is composed of 0g. A counter enable signal output from the line memory address control unit 413g,
The operation of the address counters (409g, 410g) is controlled by a control signal WENB for controlling a write address and a control signal RENB for controlling a read address generated from the scaling control section 415g. These controlled address signals are input to 2t01 selectors 407g and 408g, respectively.

The 2t01 selectors 407g and 408g provide a read address to the line memory A 404g and a write address to the line memory 8405g when the line memory A 404g is in the read mode, using the aforementioned line memory select signal LMSEL. When the line memory A 404g is in write mode, the opposite operation is performed.

Next, memory write pulses WEA and WEB to line memory A and line memory B are outputted from the variable magnification control section 415g. Memory write pulses WEA and WEB are used when reducing the input image and when the mosaic processing control unit 4
Mosaic processing is controlled by a mosaic length control signal MOZWE in the sub-scanning direction output from 02g.

Next, a detailed explanation of these operations will be given below.

Mosaic Processing> Mosaic processing is basically realized by repeatedly outputting one image data.

This mosaic processing operation will be explained using FIG. 34.

First, a mosaic processing control unit 402g independently performs main scanning and sub-scanning mosaic processing control.

First, set the variable corresponding to the desired mosaic size to CPU
The CPU sets the latch 501g (for main scanning) and the latch 502g (for sub-scanning) connected to US.

First, for mosaic processing in the main scanning direction, the same data is written continuously to multiple addresses in the line memory, and for mosaic processing in the sub-scanning direction, writing to the line memory is performed at a specified line within the mosaic processing area. This is done by thinning out each time.

(Main scanning direction mosaic processing) A variable corresponding to the mosaic width in the main scanning direction is set in the latch 501g by the CPU. The latch 501g is connected to the main scanning mosaic control counter 504g,
The setting value is loaded by the HSYNC signal and the ripple carry of the counter 504g.

The counter 504g loads the value set in the latch 501g for each HSYNC, counts a predetermined value, and outputs ripple carry to the NOR gate 502g and AND gate 509g.

Mosaic clock MCL from AND gate 509g
K is a signal obtained by multiplying the image clock CLK by the ripple carry from the counter 504g, and MCLK is output only when the ripple carry occurs.

MCLK output from AND gate 509g is then input to mosaic processing section 401g.

The mosaic processing unit 401g operates the flip-flop 510 regardless of the two D flip-flops 510g and Mj signals.
Output g. When the GHi2 signal 149 is 1 and the Mj signal is O, a signal from the flip-flop 511g controlled by the mosaic clock MCLK is output.

When the Mj signal is 1, the output is a flip-flop 510g
Output the signal from. With this control, it is possible to output a part of the mosaic-processed image in the main scanning direction without performing the mosaic process. In other words, it is possible to perform mosaic processing on only the image without performing mosaic processing on the characters that have been synthesized into an image by the preceding character synthesis circuit F as shown in FIG. The output from the selector 512g is input to the 2tol selector 403g shown in FIG. 33 mentioned above. As described above, mosaic processing in the main scanning direction is performed.

(Sub-scanning direction mosaic processing) Similarly to the main scanning direction, the sub-scanning direction is also controlled by a latch 502g connected to CPUBUS, a counter 505g, and a NOR gate 503g. Control counter during sub-scanning mosaic is ITOP signal 144, 51 1g, selector 512g, AND gate 514g, inverter 51
It is composed of 3g. Flip flop 510g,
In addition to the image signal, a gradation resolution switching signal LCHG is connected to the flip-flop 510g.
is the image clock CLK, flipflop 511
g holds the image data inputted by the mosaic processing clock MCLK and the LCHG signal. In other words,
When the gradation resolution switching signal LCHG corresponding to one pixel is in phase, it is sent to the flipflops 510g and 511.
G is held during each cycle of CL, K, and MCLK. Each retained image signal and LCH
The G signal is input to the 2tol selector-512g. Mosaic area signal GHi2 and binary character signal Mj
The output is switched depending on the signal. Selector-512
g generates a ripple carry pulse by counting HSYNC118. The ripple carry pulse is sent to the OR gate 508g as the mosaic area signal GH.
The inverted signal GHi2 of i2149 and the character signal Mj are input. Sub-scanning mosaic control signal MOZWE415g
The NAND gate 515g controls a write pulse generated by a line memory write pulse generation circuit (not shown). The line memory write pulse generation circuit is a circuit whose output clock rate is variable, such as a rate multi-briar which is generally used for variable magnification control. In this embodiment, detailed explanation will be omitted since it differs from the gist of the invention.

The WR pulse controlled by the above MOZWE signal then becomes H
The switching pulse changes from l to 2 selector to W by the switching signal LMSEL signal, which changes the switching pulse every SYNCl18.
WR pulses are alternately output to EA and WEB. With the above control, the mosaic area signal GHi2 signal 149 is “
Even in the case of 1", when the Mj signal becomes "1", writing to the memory is performed, so it is possible to output a part of the mosaic processed image in the sub-scanning direction without mosaic processing. 35(a) is a diagram showing the distribution of density values for each pixel for recorded colors in which mosaic processing is actually performed.In the mosaic processing of FIG.
Each pixel in a 3×3 pixel block is set as a representative pixel value. In this process, the mosaic process is not performed on the character A1, that is, the pixels in the shaded area, based on the character signal Mj. In other words, when a composite character and a mosaic processing area overlap, priority can be given to the character.

Therefore, even when mosaic processing is performed, an image can be formed so that only the characters can be read. Note that the mosaic area is not limited to a rectangular shape, and mosaic processing can also be performed on a non-rectangular area.

(Italics, Taber Processing) Next, the italics processing will be described first with reference to FIGS. 33 and 36.

FIG. 36 shows the inside of the line memory address control section 413g in FIG. 33. This line memory address control unit 413g has write and read counters 409g, 4
10g enable signal is controlled, and by controlling an address counter which portion of one main scanning line is written to or read from the line memory, movement, diagonalization, etc. are possible. First, using Figure 36,
The enable control signal generation circuit will be explained.

The counter 701g outputs O at I{SYNC, and then counts the image clock 117 which is the clock of the counter 701g. counter 70
The output Q of 1g is equal to the comparators 706g, 708g,
It is input in 709g and 710g. Comparator 7
The A input side of each comparator other than 09g is connected to an independent latch (not shown) connected to the CPUBUS, and an arbitrary set value and a counter 701 are connected to each other.
When the output of g matches, a pulse is output. The output of the equilateral comparator 706g is the J-K flip-flop 7.
The comparator 707g is connected to the J of 08g and the K input, and from the time the comparator 706g outputs a pulse until the comparator 707g outputs a pulse,
JK flip-flop 708g is configured to output 1. This output is used as a write address counter control signal, and the write address counter is activated only in the period where it is 1, and generates an address for the line memory. Similarly, the read address counter control signal controls the read address counter. Here, the input signal to A of the comparator 709g is connected to a selector 703g in order to make the input value to the comparator different depending on whether italicization processing is performed or not. Here, when the italic processing is not performed, the value set in the latch connected to CPUBUS (not shown) is input to the A input of selector 703g, and the A input is similarly output by the select signal output from the latch (not shown). It is output from the selector 703g. The subsequent operation is performed by the comparators 706g and 70 described above.
The operation is similar to 7g. Next, when performing italics, the value input to A of selector 703g is also input to selector 702g as a preset value. When the select signals of selectors 702g and 703g select the B input, the output of selector 702g is sent to adder 704.
At g, addition is performed with a value set in a latch, also not shown. Here this value is l due to the oblique angle
Indicates the amount of change for each line, and if the desired angle is θ, then ta
It is determined by nθ. The addition result is input to a flipflop 708g clocked by HSYNC18, and the value is held for one main scan. flipflop 705g
The output of is connected to the B input of selector 702g and the B input of selector 703g. By repeating this addition operation, the output value from the selector to the comparator 709g changes at a constant rate for each scan, so that the start of the read address counter can be varied from HSYNC at a constant rate. As a result, the reading from the line memories A404g and B405g is shifted with respect to HSYNC, and italic processing becomes possible. In addition, the amount of change mentioned above is
It can be either positive or negative. If it is positive, the readout will shift in the direction away from HSYNC, and if it is negative, it will shift in the direction toward HSYNC. In addition, selector 702g,
By changing the select signal 703'g in synchronization with HSYNC, partial italics are possible.

Regarding enlargement processing methods, generally O-order, 1st-order, SINC
There are methods such as interpolation, but since they are different from the gist of the present invention,
Explanation will be omitted. Taper processing is made possible by changing the magnification in the main scanning direction in synchronization with HSYNC for each scanning line while performing diagonal processing.

In addition, in these processes, the input gradation resolution switching signal is processed while matching the phase with the image signal, and the output image data 114 and the output gradation resolution switching signal LCHG are processed.
142 is output to the edge emphasis circuit.

The conceptual diagram of the italic processing and taper processing explained above is shown in the 35th page.
Shown in Figures (b) and (C).

FIG. 37(a) is a block diagram showing details of a mask bitmap memory 573L and its control for restricting an area of arbitrary shape. This memory has a shape as shown in FIG. 37(e), for example, and is used for the aforementioned color conversion, image cropping (non-rectangular trimming), and image filling (
It is used as an ON (process)/OFF (non-process) switching signal for various image processing/editing such as non-rectangular painting).

That is, in FIG. 2, BHil23, DHi122,
FHi121, GHi119, PHil45, AHil
It is supplied by 48 signal lines.

As shown in Figure 38, the mask is constructed such that 4 x 4 pixels constitute one block, and one bit of the bitmap memory corresponds to the ■ block, so for example, l 6
For an image with a pixel density of p e l / m m, 297
For mmX420mm (A3 size), (29
7X420X16X16)÷1642Mbit, that is, for example, IMBIT dynamic RAM,
It can be configured with 2 chips.

The signal 132 input to the PIFO 559L in FIG. 37(a) is a data input line for mask generation as described above. For example, the output 421 of the binarization circuit 532 in FIG. When input, first 4×
In order to count the number of "1"s in the block 4, buffers 559L, 560L, 561L for 1 bit x 4 lines are used.
, 562L. FIFO559L~562L
As shown in the figure (output of 559L is input to 56OL,
The output of 560L is connected to the input of 561L, and so on, and the output of each FIFO is a 4-bit parallel niratch 563L.
~565L, VCLKi: is latched (37th
(See timing chart in figure (d)).

FIFO output 615L, and latches 563L, 56
4L, 565L each output 616L, 617L, 6
18L is added by adders 566L, 567L, and 568L (signal 602L), and the CPU 22 compares the value with the value (for example, "12") set via the I/O port 25L in the comparator 569L. . That is, here, it is determined whether the number of 1's in the 4×4 block is greater than a predetermined number.

In FIG. 37(d), the number of "l"s in block N is "l4" and the number of 1's in block (N+1) is "4", so the output of converter 569L in FIG. 37(a) 603L is larger than "12" when the signal 602L is "14", so when the signal 602L is "14", it is smaller than "12", so "
Therefore, the latch pulse 6 in FIG. 37(d)
05L, the latch 570L latches one 4×4 block once, and the Q output of the latch 570 is stored in the memory 573.
This is the DIN input of L, that is, the mask creation data.

580L is an H address counter that generates the address in the main scanning direction of the mask memory, and 1 in a 4×4 block.
Since the address is assigned, the pixel clock VCLK
Counting up is performed using a clock obtained by dividing 608 into 4 by a frequency divider 577L. Similarly, 575L is an address counter that generates an address in the sub-scanning direction of the mask memory, and for the same reason, it is counted up by a clock obtained by dividing the synchronization signal HSYNC of each line by 4 by a frequency divider 574L. (2) The address operation is controlled in synchronization with the counting (addition) operation of the "bi" within the 4x4 block.

In addition, ■ Output of the lower 2 bits of the address counter, 610
L, 611L is NOR gate 572L ''cNOR
is taken, the signal 606L that gates the 4-frequency clock 607L is connected, and the AND gate 571L is used to latch only once per 4×4 block, as shown in timing chart FIG. 37(C). , latch signal 60
5L and 《can be done. 616L is the CPU bus 22 (
2), 613L is an address bus, and a signal 615L is a data path included in the CPU 22.
This is the light pulse WR from . During WR (write) operation from the CPU 22 to the memory 573L, the write pulse becomes "LO" and the gates 578L, 576L, 58
1L is opened, the address bus and data path from the CPU 22 are connected to the memory 573L, and predetermined data is written randomly, and WR (write) and R are sequentially written by the H address counter and ■address counter.
When performing a D read, the gates 576'L, 582L are opened by the control lines of the gates 576'L, 582L connected to the I/O port 25, and sequential addresses are supplied to the memory 573L.

For example, the output 421 of the binarized output 532 or the CPU
22, if a mask as shown in FIG. 39 is formed, images can be cut out, synthesized, etc. based on the area within the bold line frame.

Further, the bitmap memory shown in FIG. 37(a) can be read by thinning out or interpolation in both the H direction and the ■ direction.

That is, as shown in FIG. 40 details of the H or ■ address counters (580L, 575L) in FIG. 37, for example, when reducing, the B input of the selector 634L should be selected. be done.

635L is a decimation circuit (rate multilayer) for the input clock 614L, and FIG. 41 (timing diagram)
As shown in the figure, for example, CLK is thinned out so that it is output once every three times (setting is based on I/O port 641L)
(637L). On the other hand, 630L is set to, for example, "2", and only when the thinned out output 637L is output, the output 638L of address counter 632L and the value set in 63OL (for example, "2") are added, and the result is loaded into the counter. Therefore, as shown in Figure 41,
1→2→3→5→6→7→9, and so on, the clock advances by "+2" every three clocks, resulting in a reduction of 80%. On the other hand, when expanded, M
Since ULSEL="l" and the A input 614L is selected, as shown in the timing chart of FIG.
Address count is 1 → 2 → 3 → 3 → 4 → 5 → 6 → 6 →
...and so on.

Figure 40 shows the H address counter 580L of Figure 37, ■
This is the details of the address counter 575L, and since the hardware circuit is the same, the explanation will be limited to FIG. 37 only.

As a result, as shown in Fig. 42, enlargement 2 and reduction l are generated for the non-rectangular area l that is immediately input, so once the non-rectangular area is input, no new input work is required. Furthermore, one mask plane can be used to change the magnification according to various magnifications.

Next, the binarization circuit (532 in FIG. 2) and the high-density binary memory circuit K will be explained. In FIG. 43(a), the binarization circuit 532 outputs the video signal 1 of the output of the character image correction circuit E.
13 with a threshold value 141k to obtain a binary signal, the threshold value is set by the CPU bus 22 in conjunction with the operation unit. In other words, the threshold value is the amplitude value of the input data -
256, the memory of the operation unit in FIG. 43(C) is set to M(
When the scale is set to the midpoint), it is "128", and as the scale moves in the ten directions, it changes by -30" from the midpoint, and as it moves in one direction, it changes by "+30". Therefore, "Weak → -2 → - 1 → M → +1 → +2 → Strong", the threshold value is "218 → 188 → 158 → 128 → 98 → 68 → 3
It is controlled to change to 8''.

In addition, as shown in FIG. 43(a), CPUBUS
From 22, two threshold values are set, and the selector 35
At k, it is switched by the switching signal 151 and set as a threshold value in the converter 32k. For the switching signal 151, a different threshold value is set only in a specific area set by the Digitiger 58. For example, the threshold value is relatively low for a monochromatic area of a document, and the threshold value is relatively low for a mixed color area. By setting it high, it is possible to always obtain a uniform binary signal regardless of the color of the original.

The memory circuit K is a memory that stores the signal in which the binarized signal 421 is output to 130 for one page of images, and since this device handles images at A3 and 400 (dpi), approximately 3 It has 2 Mbit.

Details of the memory circuit K will be explained in FIG. 43(b).

The input data D and N130 are gated by the enable signal HE528 when writing to the memory, and are further controlled by the CPU 20 when writing to the ■0 port 23k? /R
When the l output is "Hi", it is input to the memory part 37k. At the same time, a synchronizing signal HSYNCI18 in the main scanning (horizontal scanning) direction is counted from the synchronizing signal ITOP144 in the vertical direction of the image to generate a vertical address. (2) Count the image transfer clock VCLKl17 from the address counter 35k1HSYNCI18, and count the addresses in the horizontal direction. By H address counter,
An address corresponding to storage of image data is generated. Memory WP input (write timing signal) at this time 55
A clock having the same phase as the clock VCLKl17 is inputted as a strobe to the memory 1k, and the input data Di is sequentially stored in the memory part 37k (timing diagram, FIG. 44). When reading data from the memory 37k, the control signal W/Rl is set to "Lo" and the output data D is read in exactly the same manner. U■ is read out. However, since data writing and reading are both performed by the HE528, for example, as shown in Figure 44 (when the HE528 is
When it goes to "Hi" at the input timing of 2 and goes to "Lo" at the input timing of Dm, the memory 37k
Only the images from D2 to Drn are input to D.
No data is written after o, D, and Dm++, and data "0" is written instead. The same goes for reading,
Data is “0” except for the section where HE is “Hi”
will be read out. HE is output from an area signal generation circuit 17, which will be described later. That is, for example, when a text document as shown in FIG. 45A is placed on the document table, if HE is generated as shown in FIG. 45 when writing a binary signal, A
' A binary image can be loaded into memory using only the character part. Similarly, unnecessary characters can also be erased and written into the memory.

Furthermore, since the address counters 35k and 36k that read data from the memory 37k have the same configuration as in FIG. 40 and operate at the same timing as in FIG. 41, the binary data read from the memory 37k is It becomes possible to change the magnification. Therefore, when synthesizing the binary character image shown in (B) of the same figure, which has been previously stored in this memory as shown in Fig. 46, with the image of (A), both of them are reduced as shown in (C). or create a sketch ((A) as shown in (D)).
It is possible to perform composition by enlarging only the character part to be composited without changing the size of the part ).

FIG. 47 shows the data stored at the equivalent of 100 dpi as described above.
Image processing blocks A, B, D, F for data from binary bitmap memory L for non-rectangular masks (Fig. 2) and 400 dpi binary memory K for characters and line images (Fig. 2)
, P, G, and the distribution of the binarized video image to the memories L, K. The mask data for limiting the non-rectangular area stored in the memory is sent, for example, to the color conversion circuit B mentioned above (BHi 123), and for example, as shown in FIG.
) Color conversion is applied only to the inside of the shape. 47th
In the figure, In is an I/O port connected to the CPU bus 22, 8n to 13n are 2 to 1 selectors, and when the switching input S = "9", the A input is set, and when S = "0", the B input is set to Y. is configured to print. Therefore, for example, in order to send the output of the 100 dpi mask memory L to the color conversion circuit B as described above, in the selector 9n,
, that is, 28n="i" and 2In manual power="l" in AND gate 3n. Similarly, other signals can be arbitrarily controlled by 16n to 31n. I
/O boat nl output, 30n, 31n is binarization circuit 5
When 30n2 is a control signal for storing the output of 32 (Fig. 2) in binary memory L or K, 2
Value 421 goes to 100dpi memory L, 31n-“1
”, the data will be input to the 400 dpi memory K.

By the way, when AHi148-“1”, the image data sent from the external device is combined and BHil23="l".
“, color conversion is performed as described above, and DHil22=
When it is "1", monochrome image data is calculated and output from the color correction circuit. Below FHi 121, PHi14
5, GHil 119 and GHi2 149 are each
Used for character composition, color balance changes, texture processing, and mosaic processing.

In this way, it has two binary memories, 100 dpi memory L and 400 dpi memory K, and stores character information in high-density 4-bit memory.
By inputting area information (including rectangular and non-rectangular areas) into the 100 dpi memory L, it is possible to perform character synthesis in a predetermined area, especially in a non-rectangular area.

Also, by having a plurality of bitmap memories, it is possible to perform color mapping as shown in FIG. 62.

FIG. 49 is a diagram for explaining the area signal generation circuit J. The area refers to, for example, the shaded area in FIG. 49(e), which refers to the timing chart AREA in FIG. 49(e) for each line in the section in the sub-scanning direction A-B.
It is distinguished from other areas by signals such as . Each area is designated by digitizer 58 in FIG. Figure 49(a)-(d)
), the generation position, section length, and number of sections of this area signal are C
This shows a configuration that is programmable and can be obtained in large numbers by the PU 20. In this configuration, one area signal is generated by one bit of a CPU-accessible RAM, and for example, in order to obtain n area signals AREAO to AREAn, two RAMs each having an n-bit configuration are provided. (Figure 49(d.) 60j, 61j). Now, if the area signals AREAO and AREAn as shown in FIG. 49(b) are obtained, bit 0 of RAM address X1+X3 is set to "1", and all bits O of the remaining addresses are set to "0". On the other hand, RAM address 1, xIn
Set "bit" to x2 + Figure 49 (
c), data “1” at address Xi and X3
is read out. This read data is input to both the J and K terminals of the JK flip-flops 62j-0 to 62j-n as shown in FIG. CLK read
When input, output “0” → “1”, “1” → “O”
, an interval signal such as AREAO, and therefore an area signal, is generated. Furthermore, if data is set to "0" over all addresses, no area section is generated and no area is set. FIG. 47(d) shows this circuit configuration, with 60j,
June is the RAM mentioned above. In order to switch the area section at high speed, for example, while reading data from RAMA60j line by line, RAM60j
1j, the CPU 20 (FIG. 2) performs memory write operations for setting different areas, and alternately switches between section generation and memory write from the CPU. Therefore, when specifying the shaded area in FIG. 49(f), A. RAMA and RAMB are switched like B→A→B→A, and this is shown in (C3) in FIG. 49(d).
, C4, C5) = (o, l, 0), then
The counter output counted by VCLK117 is given as an address to RAMA 60j through selector 63j (Aa), gate 66j is opened, gate 68j is closed and read from RAMA 60j, and the total bit width, n bits, is sent to J-K flip-flop 62j. -0~62j-n
A R E A O according to the set value.
- A R E A n interval signal is generated. B
During this time, writing from the CPU to address bus A-B
us, data path D-Bus, and access signal R/
Performed by W. Conversely, when generating a section signal based on data set in RAMB61j (C 3 +
By setting C 4 1 CI5 ) = (l+0, l), the same operation can be performed and data can be written from the CPU to the RAM 60j.

58 is a digitizer for specifying an area;
The coordinates of the specified position are input from U20 via the I/O port. For example, in Figure 50, if you specify two points A and B, A (XI, Y2), B (X 2 * ” 1)
The coordinates of are input.

FIG. 51 shows an interface circuit M for bidirectional communication of image data with an external device connected to this image processing system. 1m is an I/O port connected to the CPU bus 22, and each data bus AO to Co, AI
- Signals 5m to 9m for controlling the directions of CI and D are output. 2m and 3m are pass buffers having an output dry state control signal E, and 3m can change its direction by inputting D. For 2m and 3m, when E input = “1”,
When the signal is output and is "0", the output is in a high impedance state. 10m is 3 systems of parallel human power A, B,
3t to select one from C by selection signals 6m and 7m
ol selector. In this circuit, basically 1,
(AO, BO, Co') → (AI, Bl, C
There is a bus flow of I), 2, (AI, Bl, CI)→D. Each is controlled by the CPU 20 as shown in the truth table of FIG. In this system, as shown in Figure 53, AI, A2
, A3 has a rectangular shape as shown in FIG. 53(A), and a non-rectangular shape as shown in FIG. 53(B). When inputting in a rectangular shape as shown in FIG. 53(A), a control signal is sent from the I/O boat 501 to set the switching input of the selector 503 in FIG. 2 to "1" so that A is selected. Outputs 147.

Corresponds to the area to be combined at the same time. Area signal generation circuit J
The rectangular area signal 129 is generated by writing predetermined data from the CPU to predetermined addresses in the RAMs 60j and 61j (FIG. 51), as described above.

In the area where the image input 128 from the external device is selected by the selector 507, not only the image data 128 but also the gradation and resolution switching signals 140 are switched at the same time. That is, in an area where an image from an external device is input, a character area signal is generated based on the MIAR 124 (FIG. 2), which is detected from the color separation signals of the image read from the document table. By stopping the gradation and resolution switching signals and forcibly setting them to "Hi," the image area from the inserted external device is outputted smoothly in high gradation.

In addition, as explained in FIG. 51, the bitmap mask signal AH4 from the binary memory L
When selected by signal 147 at 03, Fig. 53 (B)
Image synthesis from external devices such as

<Overview of operation section> FIG. 54 shows an overview of the main body operation section 1000 of this embodiment. Key l100 is a copy start key.

Key 1 101 is a reset key that returns all settings on the operation panel to the values when the power was turned on. A key 1102 is a clear stop key, which is used to reset input values such as specifying the number of copies and to cancel a copy operation.

A group of keys 1103 is a numeric keypad and is used to input numerical values such as the number of copies and magnification input. Key l104 is a document size detection key. A key 1105 is a center movement designation key. Key l106 is an ACS function (black original recognition) key. When ACS is ON, a monochrome black original will be copied in monochrome black. A key 1107 is a remote key, and is a key for passing control to a connected device. Key 1108 is a preheat key.

A liquid crystal screen 1109 displays various information.

The surface of the screen is a transparent touch panel, and when you press it with your finger, the coordinate values are captured.

In the standard state, the magnification, selected paper size, number of copies, and copy density are displayed. While setting various copy modes, the screens necessary for mode settings are displayed one after another. (The copy mode is set using the keys displayed on the screen.) Also displays the self-diagnosis display screen on the guide screen.

A key 1110 is a zoom key, and is an enter key for entering a mode for specifying the magnification of magnification. A key 1111 is a zoom program key, and is an enter key to a mode in which a magnification ratio is calculated from the original size and copy size. A key 1112 is an enlarged continuous shooting key, and is an enter key for entering enlarged continuous shooting mode.

A key 1113 is a key for setting inset composition.

A key 1114 is a key set for character composition. key 1
115 is a key for setting color balance. key l
Reference numeral 116 is a key for setting a color mode such as single color, negative/positive inversion, etc. Key 1117 is a user's color key, and can set any color mode. key 111
8 is a paint key that allows you to set the paint mode. A key 1119 is a key for setting a color conversion mode.

Key l120 is a key for setting the contour mode. Key 1121 is used to set the mirror image mode. Keys 1124 and 1123 specify trimming and masking.

．． It is possible to specify an area using the key 1122 and set the internal processing differently from other parts. key 112
9 is an enter key for entering a mode for performing operations such as reading texture images. Key 1128 is an enter key for entering a mosaic mode such as changing the mosaic size.

Key 1127 is an enter key to a mode that adjusts the edge sharpness of the output image. The key 1126 is a key for setting an image repeat mode in which a specified image is repeatedly output.

The key l125 is a key for applying italic/taper processing, etc. to an image. Key 1135 is a key for changing the movement mode. A key 1134 is used to make settings such as continuous page copying and arbitrary division, and a key 1133 is used to make settings related to the projector. Key 1132 is an enter key to a mode for controlling optional connected equipment. The key 1131 is a recall key that allows you to recall the settings up to three times ago. Key 1130 is an asterisk key.

Keys 1136 to 1l39 are mode memory recall keys.
Used when recalling a registered mode memory. Keys 1140 to 1143 are program memory call keys, which are used to call up registered operation programs.

<Color conversion operation procedure> The procedure of color conversion operation will be explained using FIG. 55.

First, when the color conversion key 1119 on the main body operation section is pressed, the display section 1109 is displayed as PO50.

Place the original on the digitizer and use the pen to specify the color before conversion. When the input is completed, the screen of P051 appears. Here, use the touch keys 1050 and 1051 to adjust the width of the color before conversion, and after completing the settings, press the touch key 1052.
Press. The screen changes to P052, and the touch key 1053 and touch key 1054 are used to select whether to add shading to the converted color.

If you select shading, the color after conversion will have gradation to match the shading of the color before conversion. That is, the above-mentioned gradation color conversion is performed. On the other hand, if you select no shading, the specified color will be converted to the same density. When you select whether or not to have shading, the screen of PO53 appears, and you can select the type of color after conversion. When 1055 is selected in P053, P
The operator can specify any color to O54. Further, when the color adjustment key is pressed, the screen moves to PO55, and color adjustment can be performed in 1% increments for each of Y, M, C, and Bk.

Also, if you press 1 056 on PO53, it will move to PO56.
Specify the desired color of the document on the digitizer using the point pen. Next, the color shading can be adjusted using PO57.

Furthermore, if 1057 is pressed at P053, the screen moves to P058, where a predetermined registered color can be selected by number.

<Procedure for specifying the trimming area> Below, using Figures 56 and 57, trimming (
The same goes for masking, and how to specify areas.
The same procedure applies to partial processing, etc. ) Explain the procedure for specifying an area.

If you press the trimming key 1124 on the main body operation unit 1000 and enter two diagonal points of the rectangle using the digitizer when the display unit 1109 becomes Pool, the screen of P002 will appear, and you can continue to input the rectangular area. can. In addition, if you specify multiple areas, press the area key 1001 before P001, then press the area key 1002 to select POO2.
You can confirm each designated area in the X-Y coordinates as shown in the following.

On the other hand, in this embodiment, it is possible to specify a non-rectangular area using the bitmap memory. While the Pool screen is being displayed, touch key l003 is pressed to move to P003. Select the shape here. For circles, ellipses, R rectangles, etc., when the necessary coordinate values are input, the shapes are expanded into the bitmap memory by calculation. In the case of free shapes, coordinate values are input continuously by tracing the desired shape with a point pen using a digitizer, and the values are processed and recorded on a bitmap.

Each non-rectangular area specification will be explained below.

(Circular area designation) When key l004 is pressed at P003, the display section 1109 will display P.
Moving to OO4, a circular area can be specified.

The circular area designation will be explained below using the flowchart of FIG. 58. In S101, the center point is input from the digitizer 58 in FIG. 2 (POO4).

Next, the display unit 1109 moves to POO5 and inputs one point on the circumference of a circle having the radius to be specified from the digitizer 58 in S103. In S105, the CPU 20 calculates the coordinate values of the input coordinate values on the bitmap memory L (100 dpi binary memory) shown in FIG.

Further, in S107, coordinate values of another point on the circumference are calculated.

Next, a bank of the bitmap memory L is selected at 8109, and the above calculation result is input to the bitmap memory L via the CPU bus 22 at Sill. Figure 37(a)
The data is written from CPU DATA 616L to bitmap memory from 604L via driver 578L. Address control is the same as described above, so it will be omitted. This is repeated for all points on the circumference (Sl 13) to complete the circular area designation.

In addition, instead of inputting information while calculating it in the CPU 20 as described above, template information for the two inputted information points is stored in the ROMII in advance, and by specifying these two points with a digitizer, the information can be input directly without calculation. It is also possible to write to the bitmap memory L.

(Oval area designation) When the key 1005 is pressed in P003, the process moves to POO7. The process will be explained below using the flowchart shown in FIG.

First, in S202, the diagonal 2 of the largest rectangular area inscribed in the ellipse
A point is designated by the digitizer 58. Below, for the circumferential part, do 8206 in the same way as in the case of specifying the circular area above.
The data is written to the bitmap memory L in the steps from ~S212.

Next, the straight line portion is written into the memory in steps 5214 to S220, and the area designation is completed. As in the case of the circular shape, it is also possible to store the template information in the ROM 21 in advance.

(R rectangular area designation) The method of designation is the same as in the case of an ellipse for memory writing, so the explanation will be omitted.

Incidentally, although the cases of a circle, an ellipse, and an R rectangle have been explained above as examples, it goes without saying that other non-rectangular areas can also be specified based on the same template information.

In POO6, POO8, POIO, and P102, by pressing the clear key (1009 to 1012) after inputting each shape, it is possible to partially erase the bitmap memory.

Therefore, even if a mistake is made in the designation, only the two points can be quickly cleared and the two points can be designated again.

It is also possible to specify multiple areas in succession. When multiple areas are specified, priority is given to processing of the area specified later when processing each of the overlapping areas. However, the one specified first may be given priority.

FIG. 57 shows an output example obtained by trimming with an ellipse using the above settings.

Operational Procedures for Character Synthesis> The operation and setting procedures for character synthesis will be described below with reference to FIGS. 60, 61, and 62. When you press the character synthesis key 1114 on the main body operation section, the liquid crystal display section 1109 displays P.
It will be displayed like O20. A character original 120l to be synthesized is placed on the above-mentioned original table, and when the touch key 120 is pressed, the character original is read, binarized, and the image information is stored in the above-mentioned bitmap memory FIG. 2. The specific means of processing has been described above, so duplication will be avoided. At this time, to specify the range of the image to be stored, press the touch key 1021 in PO20 to go to the screen of PO21, place the text original 1201 on the digitizer 58, and use the point pen of the digitizer to mark the range with two points. specify.

When the specification is completed, the display section changes to P022, and the user selects whether to read within the specified range (trimming) or to read outside the specified range (masking) using touch key 1023 and touch key 1024. Furthermore, depending on the text document, it may be difficult to extract the character portion of the text document during the above-mentioned binarization process. In this case, the touch key 1022 in PO20 moves to the screen of P023, and the slice level for the binarization process can be adjusted using the touch keys 1025 and 1026.J In this way, the slice level can be adjusted. Since it can be adjusted manually, appropriate binarization processing can be performed depending on the color, thickness, etc. of the characters in the document.

Furthermore, press touch key l027, PO24'PO2
By specifying an area with 5', it is possible to partially change the slice level with PO26'.

In this way, by specifying an area and changing the slice level only for that part, even if there is, for example, yellow text in a part of the black text document, separate appropriate slice levels can be set for each of the black and yellow text. By doing so, it is possible to perform good binarization processing on the entire character.

When the reading of the character original is completed, the display section l109 becomes as shown in FIG. 61 PO24.

To select color blank processing, touch key l0 in P024
Press 27 to move to the PO25 screen, and select the color of the characters to be combined from the displayed colors.

You can also partially change the color of the text. In that case, press touch key 1029 to move to the P027 screen, specify the area, and then select the text color on the P030 screen. . Furthermore, it is also possible to add color border processing to the edges of the characters to be synthesized, in which case P03
Move to the screen of P032 with touch key 1031 in 0,
Select a color for the border. At this time, you can adjust the color by
This is the same as in the case of color conversion above. Furthermore, touch key 103
Press 3 to adjust the border width on the PO41 screen.

Next, a case in which color number processing is added to a rectangular area containing characters to be synthesized (hereinafter referred to as square processing) will be described. P02
Press the touch key 1 028 in 4 to move to the screen P034 and specify the area. The processing will be performed within the range specified here. When the area designation is completed, the character color is selected in P037, the touch key 1032 is pressed, the screen moves to P039, and the color of the square is selected.

In the above color selection, for example, on the screen P025, by pressing the color adjustment key of the touch key 1030, the screen moves to the screen PO26, where it is possible to change the tone of the selected color.

Character synthesis is performed according to the procedure described above. FIG. 62 shows an example of the output when the settings are actually made.

In addition to specifying a rectangular area, the area specification can also specify a non-rectangular area as described above.

<Texture processing setting procedure> Next, texture processing will be explained using FIG. 63.

When the texture key 1129 on the main body operation section tooo is pressed, the display section 1109 displays something like P060.

When applying texture processing, touch key 1060 is pressed to highlight this key. When reading an image pattern for texture processing into the above-mentioned texture image memory (Fig. 32, 113g), press the touch key 106.
Press 1. At this time, if the pattern is already in the image memory, as in P062, if it is not displayed, P
O61 will be displayed. By placing the document with the image to be read on the document table and pressing the touch key 1062,
Image data is stored in the texture image memory.

At this time, in order to read any part of the document, the user presses the touch key 1063 and specifies it using the digitizer 58 on the PO63 screen. The specified reading range is 16mm x 1
This can be done by inputting a single point at the center of 6 mm using a pen.

Reading of a texture pattern by specifying one point as described above can be performed as follows.

Without reading the pattern, press the touch key 1060, set the texture processing, and press the copy start key l.
If an attempt is made to escape from the P064 screen using lOO, other mode keys (1110-1143), touch key 1064, etc., the display section issues a warning as shown at P065.

Further, the length and width of this range can be specified by the operator.

<Mosaic processing setting procedure> FIG. 64 is a diagram explaining the procedure of mosaic processing setting.

When the mosaic key 1128 on the main body operation section is pressed, the display section displays P100. To apply mosaic processing to a document, touch key 1400 is pressed to highlight this key.

Furthermore, when performing mosaic processing, the mosaic size is changed by pressing the touch key 1401 on the PIOI screen. The mosaic size can be changed independently in both the vertical (Y) direction and the horizontal (X) direction.

(About blue mode operation procedure) FIG. 65 is a diagram illustrating the operation procedure in the screen mode.

When the hard key 1l30 on the main body operation section 1000 is pressed, the screen mode is entered, and the display section 1109 is displayed like Pi 10. The touch key 1500 enters a color registration mode for registering color information used in paint user colors, color conversion, color text, and the like. A touch key 1501 turns on/off a function for correcting image defects caused by the printer.

Touch key 1502 is a key for entering mode memory registration mode. The touch key 1503 enters a mode for specifying the manual feed size. Touch key 1504 enters program memory registration mode. The touch key l505 is
This key is used to enter the mode for setting default color balance values.

(About color registration mode) When the touch key 1500 is pressed when PIIO is displayed, the color registration mode is entered. The display section looks like Pill, and the type of color to be registered is selected. To change the palette color, press the touch key 1506, select the color you want to change on the screen of P116, and change the values of each component of yellow, magenta, cyan, and black in 1% increments on the screen of PI 17. Can be adjusted.

Also, if you want to register any color on the document, touch key 1.
Press 507, select the registration number on the Pi18 screen,
Specify using the digitizer 58, set the original on the original table when the screen of P120 is displayed, press the touch key 1510,
Register.

(About manual feed size specification) As shown on page 112, manual feed size can be specified as either standard or non-standard size.

For irregular shapes, both the horizontal (X) direction and the vertical (Y) direction can be specified in units of 1 mm.

(Regarding mode memory registration) The set mode can be registered in the mode memory as shown on page 113.

(Regarding program memory registration) As shown in P114, a series of programs for specifying an area and performing predetermined processing can be registered.

(Regarding color balance registration) As shown in PI15, color balance can be registered for each of Y, M, C, and Bk.

<Regarding program memory operation procedure> The registration operation in the program memory and its usage procedure will be explained below with reference to FIGS. 66 and 67.

Program memory is a memory function that stores operating procedures related to settings and reproduces them. It is possible to connect the necessary modes and make settings that go beyond unnecessary screens. As an example, let's program memory the procedure for changing the magnification of a certain area of a document and repeating the image.

Press the fog mode key 1130 on the main body operation section, display the screen P080 on the liquid crystal display section, and press the program memory key of the touch key 1200. In this embodiment, four programs can be registered. Select the number to register on the PO81 screen. After this, move to program registration mode. In the program registration mode, for example, the screen shown in FIG. 68 1300 in the normal mode becomes as shown in l301. The skip key of the touch keys 1302 is designated when the user wants to skip the current screen. The clear key of the touch keys 1303 is used to cancel the current registration in the middle of program memory registration and restart the registration from the beginning.

The end key of touch key 1304 exits the program memory registration mode and registers in the memory of the first determined number.

First, press the trimming key 1124 in the main unit operation section,
Specify the area with the digitizer. The display unit is displaying P084, but if no further area settings are to be made at this point, touch key 1202 is pressed to designate skipping this screen. (The screen becomes P085) Next, when the zoom key 1110 on the main body operation section is pressed, the display section becomes PO86. Here, the magnification is set and when the touch key 1203 is pressed, the display changes to PO87. Finally, press the image repeat key 126 on the main body operation section, make settings regarding image repeat on the screen P088, and then register to number 1 in the program memory using the touch key 1 204.

To call up the program registered in the above procedure, press the program memory 1 call key 1140 on the main body operation section. The display section displays PO91 and waits for area input. If you input the area using a digitizer,
The display section displays P092, and then proceeds to the next PO93. After setting the magnification here, if the touch key 1210 is pressed, the display section changes to PO94 and image repeat can be set. When the touch key 1211 is pressed, the mode in which the program memory is used (referred to as trace mode) is exited.

Note that from the time the program memory is called until the program is terminated,
Each key (1110 to 1143) in the edit mode is disabled, and operations can be performed according to the registered program.

FIG. 69 shows the program memory registration algorithm. Screen turning in S301 means changing the display on the display unit using keys or touch keys.

If you press the touch key 1302 and specify to skip the currently displayed screen (S303), that information will be set on the recording table when the next screen appears (S303).
305). Then, in S307, a new screen number is set in the recording table. When the clear key is pressed, the record table is completely cleared (530.9, 5311),
In other cases, the process returns to S301 and moves to the next new screen. FIG. 71 shows the format of the recording table. FIG. 70 shows an algorithm representing the operation after calling the program memory.

If there is a screen turn in S401, it is determined whether the new screen is a standard screen (S403). If it is a standard screen, the process moves to S411 and sets the next screen number from the recording table; if it is not a standard image, the new screen number is compared with the scheduled screen number in the recording table (S405);
If they are equal, the process moves to S409, and if there is a skip flag, S411 is skipped and the process returns to S401. If they are not equal, a recovery process is performed (S407) and the screen is turned over.

As described above, according to this embodiment, a color-separated color image is digitally read for each color, and the read color image data is used to detect character areas, halftone areas, and halftone areas, Based on these three area signals, a discrimination signal for character area and image area is obtained, and high resolution processing is applied to the former.
In an image processing device that performs high gradation processing on the latter to obtain a single color image output, the intermediate tone region is processed using color separation signals R, G,
The above object of the present invention is achieved by a configuration in which detection is performed using the minimum value of B.

Specifically, color separation signals R, G,
Since the minimum value of B is used, the halftone signal can be reliably detected regardless of color.

According to this embodiment, the color separation data R is used as the halftone detection signal.
, G, and B, image part processing (high gradation processing) can be performed even for color intermediate tones, improving the image quality of the output image.

In particular, in this embodiment, R, G, and B are input from the reading means, and the R, G, and B signals are directly used to detect the maximum and minimum values and perform area separation processing, which saves time. There is no loss.

In addition, there is no conversion error that may occur when converting to Y, M, and C once and then performing the conversion based on this.

〔Effect of the invention〕

As explained above, according to the present invention, it is possible to accurately separate halftone areas during image area separation, resulting in high-quality reproduction. FIG. 1 is an overall view of an image processing apparatus according to an embodiment of the present invention, and FIG. A circuit diagram of image processing according to an embodiment of the present invention. FIG. 3 is a diagram showing a color reading sensor and drive pulses. FIG. 4 is a circuit diagram for generating ODRV 118a and EDRV 119a. FIG. 5 explains black correction operation. Figure 6 is a circuit diagram of shading correction, Figure 7 is a color conversion block diagram, Figure 8 is a color detection unit block diagram, Figure 9 is a block diagram of a color conversion circuit, and Figure 10 is a concrete example of color conversion. A diagram showing an example, Figure 11 is a diagram explaining logarithmic conversion, Figure 12 is a circuit diagram of a color correction circuit, Figure 13 is a diagram showing an unnecessary transmission area of a filter, Figure 14
The figure shows unnecessary absorption components of the filter, Figure 15 is a circuit diagram of a character image area separation circuit, Figure 16 is a diagram explaining the concept of contour regeneration, and Figure 17 explains the concept of contour regeneration. Figure 18 is a contour regeneration circuit diagram, Figure 19 is a contour regeneration circuit diagram, Figure 20 is a timing chart of ENI and EN2,
Figure 1 is a block diagram of the character image correction section, Figure 22 is an explanatory diagram of addition/subtraction processing, Figure 23 is a switching signal generation circuit diagram, Figure 24 is a circuit diagram of color residual removal processing, and Figure 25 is color residual removal processing. , Figure 26 is a diagram showing edge emphasis, Figure 27 is a diagram showing smoothing, Figure 28 is a diagram explaining processing and modification processing using binary signals, Figure 29 is a diagram explaining text, Figure 30 is a block diagram of the image editing circuit, Figure 31 is a diagram showing texture processing, Figure 32 is a circuit diagram of texture processing, Figure 33 is a diagram of mosaic, scaling, and tapering processing. A circuit diagram, FIG. 34 is a circuit diagram of mosaic processing, FIG. 35 is a diagram explaining mosaic processing, etc., FIG. 36 is a circuit diagram of the line memory address control section, FIG. 37 is an explanatory diagram of the mask bit memory, Fig. 38 is a diagram showing addresses, Fig. 39 is a diagram showing a specific example of a mask, Fig. 40 is a circuit diagram of an address counter, Fig. 41 is a timing chart for enlargement and reduction, and Fig. 42 is a diagram for enlargement and reduction. Figure 43 is an explanatory diagram of the binarization circuit, Figure 44 is a timing chart of the address counter, Figure 45 is a diagram showing a concrete example of bitmap memory writing, Figure 46 is a diagram showing a specific example of writing to a bitmap memory, and Figure 46 is a diagram showing a binary conversion circuit. , a diagram showing a specific example of image synthesis, FIG. 47 is a circuit diagram of distribution switching, FIG. 48 is a diagram showing a specific example of a nonlinear mask, FIG. 49 is a circuit diagram of a region signal generation circuit, and FIG. 50 is a digitizer 51 is an interface circuit diagram with external equipment, FIG. 52 is a selector truth table, FIG. 53 is a diagram showing examples of rectangular areas and non-rectangular areas, and FIG. 54
55 is a diagram explaining the procedure of color conversion operation, FIG. 56 is a diagram explaining the procedure of specifying the trimming area, FIG. 57 is a diagram explaining the procedure of specifying the trimming area, Figure 58 is a diagram showing the algorithm for specifying a circular area.
Figure 9 is a diagram showing the algorithm for specifying areas of ellipses and R rectangles, Figure 60 is an explanatory diagram of the operating procedure for character composition, Figure 61 is an explanatory diagram of the operating procedure for character composition, and Figure 62 is an illustration of the operation procedure for character composition. FIG. 63 is a diagram explaining the procedure of texture processing. FIG. 64 is a diagram explaining the procedure of mosaic processing. FIG. 65 is a diagram explaining the procedure of screen mode operation.
Figure 67 is a diagram explaining the program memory operation procedure. Figure 68 is a diagram explaining the program memory operation procedure. Figure 69 is a diagram explaining the program memory registration algorithm. Figure 70 is a diagram showing the algorithm of the operation after calling the program memory; Figure 71 is a diagram showing the format of the recording table;
FIG. 2 is a diagram showing image processing and editing.

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Claims (2)

[Claims] (1) It has means for detecting a minimum value signal of the three additive primary color signals from input image data, and means for determining a halftone region of the input image based on the minimum value signal that is the output of the detection means. An image processing device characterized by: (2) Claim (1) characterized in that the additive three primary color signals are R (red), G (green), and B (blue).
) image processing device.