JPH02295344A - Picture processor - Google Patents

Abstract

PURPOSE:To obtain the output of a picture where the working edition of a high level is executed with high picture quality by controlling a picture area discriminating signal based on an area discriminating signal to define a designated specified area as a boundary. CONSTITUTION:A designating means 58 is provided to designate the specified area to input picture data and to generate an area signal and control means F and G are provided to execute the working and edition on the specified area. Then, a picture area discriminating means I is provided to identify the character area of the input picture and the other area excepting for the the character area and a first control means E is provided to vary a printing condition based on the output signal of the image area discriminating means. Further, a second control means 52 is provided to control the image area discriminating signal based on the area discriminating signal which defines the designated specified area as the boundary. Thus, the working and edition of the picture can be executed to the specified area effectively together with image area separation.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an image processing device that digitally processes an input image and performs various image processing on the input image.

[Conventional technology]

In recent years, digital color copying machines that obtain digital color hard copies by color-separating a color original, reading each pixel, digitally processing the read image data, and outputting it to a color printer have become widespread. This type of device has the advantage of being able to process image data digitally, so it is possible to move the image output position (
Fig. 72(a)), extracting a desired image area (Fig. 72(b)), converting only a certain color within the desired area (Fig. 72(C)), and storing data in memory. It has become possible to perform various image processing such as inserting written characters and images into a reflective original (FIG. 72(d)), and its application in the field of so-called color copying is expanding.

Therefore, by combining various functions, it has become possible to easily apply it to color proposals, advertising posters, promotional materials, design drawings, etc.

On the other hand, for color reflective originals, the letters look more like letters.
There is a growing demand for images to look more like real images, and in response to this, image area separation is used to separate text and image areas.
High-resolution processing is applied to the text portion, particularly black characters are printed in a single black color, while high-gradation processing is applied to the image portion.

[Problem that the invention is trying to solve]

However, in the conventional example described above, in image processing that performs image area discrimination and outputs with different printing conditions based on the output signal of the image area discrimination, image processing and editing for a specific area,
For example, when painting is performed, different printing conditions affect the painted area, causing problems in image area discrimination.

SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide an image processing apparatus that can eliminate the above-mentioned drawbacks and perform highly accurate image processing and editing processing.

[Means and operations for solving the problems] In order to solve the above problems, the image processing apparatus of the present invention includes a designating means for designating a specific region with respect to input image data and generating a region signal;
A control means for processing and editing the image for the specific area, an image area discrimination means for distinguishing between character areas and non-character areas of the input image, and printing conditions based on the output signal of the image area discrimination means. and a second control means that controls the image area discrimination signal based on the area discrimination signal that bounds the designated specific area.

In the above configuration, the second control means controls the image area discrimination signal based on the area signal.

(Margin below) 〔Example〕 Hereinafter, the present invention will be explained in detail with reference to the drawings.

FIG. 1 shows an example of a schematic internal configuration of a digital color image processing system according to the present invention. As shown in the figure, this system has a digital color image reading device (hereinafter referred to as a color reader) 1 at the top and a digital color image printing device (hereinafter referred to as a color printer) 2 at the bottom. This color reader l has color separation means and C
A photoelectric conversion element such as a CD reads the color image information of the original for each color and converts it into an electrical digital image signal. The color printer 2 is an electrophotographic laser beam color printer that reproduces a single color image in each color according to the digital image signal, and records the image by transferring it to a recording paper multiple times in the form of digital dots.

First, an overview of the color reader I will be explained.

3 is a document, 4 is a platen glass on which the document is placed, and 5 is a lens for condensing the reflected light image from the document exposed and scanned by the halogen exposure lamp 10 and inputting the image to the 1-magnification full-power color sensor 6. It is a door array lens, 5, 6,
7. 10 as a document scanning unit 11 performs exposure scanning in the direction of arrow AI.

The color separation image signals read every line without exposure scanning are amplified to a predetermined voltage by the sensor output signal amplification circuit 7, and then inputted to a video processing unit to be described later via a signal line 501, where they are processed. . Details will be described later. 501 is a coaxial cable for ensuring faithful transmission of signals. A signal 502 is a signal line that supplies drive pulses for the same-magnification full-strength color sensor 6, and all necessary drive pulses are generated within the video processing unit l2. 8
, 9 are a white plate and a black plate for white level correction and black level correction of image signals, which will be described later.By irradiating them with a halogen exposure lamp 10, signal levels of predetermined densities can be obtained, respectively, and the video signal Used for white level correction and black level correction. l3 is a control unit with a microcomputer, which is connected to bus 508
Display on the operation panel 20, key manual control and control of the video processing unit 12, position sensor S
The position of the document scanning unit 1l is determined by the signal line 5 by l and S2.
09, 510, stepping motor drive circuit control for pulse-driving the stepping motor 14 for moving the scanning body 11 via a signal line 503, and halogen exposure lamp 10 by an exposure lamp driver via a signal line 504. It performs all controls of the color reader part 1, such as ON/OFF control, light amount control, and control of the digitizer 16, internal keys, and display section via the signal line 505. The color image signal read by the above-mentioned exposure scanning unit ll during exposure scanning of the original is sent to the video processing unit l2 via the amplifier circuit 7 and the signal line 501.
The data is inputted to the unit 12, subjected to various processes described below, and sent to the printer part 2 via the interface circuit 56.

Next, an outline of the color printer 2 will be explained. 711 is a scanner, a laser output unit that converts the image signal from the color reader 1 into an optical signal, and a polyhedron (for example, an octahedron).
polygon mirror 712, a motor (not shown) for rotating this mirror 712, and an f/θ lens (imaging lens)
713 etc. 714 is a reflecting mirror that changes the optical path of the laser beam, and 715 is a photosensitive drum. The laser beam emitted from the laser output section is reflected by a polygon mirror 712, passes through a lens 713 and a mirror 714, and linearly scans (raster scan) the surface of a photosensitive drum 715, forming a latent image corresponding to the original image. do.

In addition, 711 is a primary charger, 718 is a full exposure lamp,
723 is a cleaner section that collects residual toner that has not been transferred; 724 is a pre-transfer charger; these members are arranged around the photosensitive drum 715.

726 is a developing unit that develops the electrostatic latent image formed on the surface of the photosensitive drum 715 by laser exposure, and 731Y, 731M, 731C, and 7318k are developing sleeves that directly develop the photosensitive drum 715;
0Y, 730M, 730C, and 7308k are toner hoppers for holding spare toner; 732 is a screw for transporting developer; and these sleeves 73
1Y~7318k, l-nahoppa=730Y~730
8k and screw 732 to connect the developer unit 72.
6, and these members are arranged around the rotation axis P of the developing unit. For example, when forming a yellow toner image, yellow toner development is performed at the position shown in this figure, and when forming a magenta toner image, the developing unit 726 is rotated around the axis P in the figure and exposed to light. body 715
The developing sleeve 731 in the magenta developing device is in contact with the
Place M. Black development works in the same way.

Further, 716 is a transfer drum that transfers the toner image formed on the photosensitive drum 715 onto paper, 7l9 is an actuator plate for detecting the moving position of the transfer drum 716, and 720 is adjacent to this actuator plate 719. 725 is a transfer drum cleaner, 727 is a paper press roller, 728 is a static eliminator, and 729 is a transfer charger. These members 71
9, 720, 725, 727, and 729 are arranged around the transfer roller 716.

On the other hand, 735 and 736 are paper feed cassettes that store paper (paper sheets), and 737 and 738 are cassettes 735 and 738, respectively.
Paper feed rollers that feed paper from 736, 739, 74
0 and 741 are timing rollers that take the timing of paper feeding and conveyance, and the paper fed and conveyed via these is guided to a paper guide 749 and wrapped around the transfer drum 716 while its leading edge is carried by a gripper (to be described later). , transition to the image formation process.

Further, 550 is a drum rotation motor, and the photosensitive drum 7
15 and a transfer drum 716 are rotated in synchronization. 750 is a peeling claw that removes the paper from the transfer drum 716 after the image forming process is completed, 742 is a conveyor belt that conveys the removed paper, and 743 is a conveyor belt that is conveyed by the conveyor belt 742. The image fixing unit 743 is an image fixing unit that fixes the paper that has been received.

The image processing circuit according to the present invention will be described in detail with reference to FIG. 2 and subsequent figures. This circuit exposes a full-color original with an illumination source such as a halogen lamp or fluorescent lamp (not shown), captures a reflected color image with a color image sensor such as a CCD, and sends the obtained analog image signal to an A/D converter. A color image copying device that processes and processes the digitized full-color image signal and outputs it to a thermal transfer color printer, inkjet color printer, laser beam color printer, etc. (not shown) to obtain a color image, or a color image copying device that obtains a color image by processing the digitized full-color image signal It is applied to color image output devices that input color image signals from computers, other color image reading devices, color image transmitting devices, etc., perform processing such as compositing, and output them to the color printer mentioned above. be.

The document is first irradiated by an exposure lamp (not shown), and the reflected light is separated into colors for each image and read by a color reading sensor 500a, and amplified to a predetermined level by an amplifier circuit 501a. 533a is a CCD driver that supplies pulse signals for driving the color reading sensor, and the necessary pulse source is generated by a system control pulse generator 534a.

FIG. 3 shows the color reading sensor and drive pulses. Figure 3(a) shows the color reading sensor used in this example, which reads by dividing the main scanning direction into five (63
．． Assuming 5 μm as one pixel (4 dots/inch (hereinafter referred to as dpi)), there are 1024 pixels, as shown in the figure! Since the pixels are divided into three by G, B, and R in the main scanning direction, the total number of effective pixels is 1024X3=3072. On the other hand, each of the chips 58 to 62 is formed on the same ceramic substrate, and the chips 58 to 62 are formed on the same ceramic substrate. 3. 5th (5
8a, 60a, 62a) are on the same line LA, 2
, the fourth is 4 lines away from LA (63.5 p m
4=254 μm) on the line LB, and scans in the direction of the arrow AL when reading the document.

1, 3 out of each 5 COD. The 5th is the drive pulse group ODRV118a, the 2nd and 4th are the EDRVl19a
are driven independently and synchronously.

OOIA, 002A, OR included in ODRVI18a
EOIA, EO2A, included in S and EDRVI19a,
ERS is a charge transfer clock and a charge reset pulse within each sensor, respectively; 1, 3. fifth and second,
Due to mutual interference with the fourth and noise limitations, they are generated in perfect synchronization so that there is no jitter between them. Therefore, these pulses are generated by one reference oscillation source OSC558a (second
Figure).

FIG. 4(a) shows a circuit block that generates ODRVll8a and EDRV119a, and FIG. 4(b) shows a timing chart, which are included in the system control pulse generator 534a of FIG. 2. Clock KO obtained by dividing the original clock CLKO generated by a single OSC558a
135a is a clock that generates reference signals SYNC2 and SYNC3 that determine the timing of generation of ODRV and EDRV (7), and SYNC2 and SYNC3 are settings for resettable counters 64a and 65a that are set by the signal line 22 connected to the CPU bus. The output timing is determined according to the value, and SYNC2 and SYNC3 are connected to the frequency divider 66a.
, 67a and drive pulse generators 68a, 69
Initialize a. In other words, H input to this block
Based on SYNC118, all with one oscillation source OSC5
Since it is generated by the CLKO output from 58a and the branch clocks that are all generated synchronously, the OD
The respective pulse groups of the RV 118a and the EDRV] 19a are obtained as synchronous signals with no jitter at all, and signal disturbances due to interference between sensors can be prevented.

Here, the sensor drive vanorless ODRV18a obtained in synchronization with each other are 1, 3. Fifth sensor 58a
, 60a, 62a, the EDRV 119a is supplied to the second and fourth sensors 59a, 6]a, and each sensor 58a,
Video signals Vl-V5 are independently outputted from 59a, 60a, 61a, and 62a in synchronization with the drive pulse, and a predetermined signal is output by independent amplifier circuits 501-1 to 501-5 for each channel shown in FIG. It is amplified to a voltage value and passed through the coaxial cable l01a to OOS12 in Fig. 3(b).
Timing of 9a - 7'Vl, V3, V5 are EOS13
At timing 4a, signals V2 and V4 are sent out and input to the video image processing circuit.

The color image signal obtained by dividing the original input into the video image processing circuit into five parts is processed by the sample hold circuit S/H502a in three colors of G (green), B (blue), and R (red). separated into

Therefore, after S/H, 3×5=15 signals are processed.

The analog color image signals sampled and held for each color R, G, and B by the S/H circuit 502a are as follows:
The next stage A/D conversion circuit 503a digitizes each channel from 1 to 5, and each channel from 1 to 5 is independently connected in parallel.
Output to the next stage.

Now, in this embodiment, as described above, 4 lines (63.
5 μm x 4 = 254 μm) in the sub-scanning direction,
In addition, since the document is read using five staggered sensors divided into five areas in the main scanning direction, the reading positions of channels 2 and 4, which are being scanned in advance, and the remaining channels 1 and 3.5 are shifted. Therefore, in order to connect this correctly, a shift correction circuit 504a equipped with memory for multiple lines is used to
We are correcting that discrepancy.

Next, using FIG. 5(a), the black correction/white correction circuit 506
The black correction operation in a will be explained. As shown in FIG. 5(b), when the amount of light input to the sensor is small, the black level outputs of channels 1 to 5 vary greatly between chips and between pixels. If this is output as is and an image is output, streaks and unevenness will occur in the data portion of the image. Therefore, it is necessary to correct the output variation in the black portion, and this correction is performed using a circuit as shown in FIG. 5(a). Prior to the original reading operation, the original scanning unit is moved to the position of a black plate having uniform density that is placed in a non-image area at the tip of the original table, the halogen is turned on, and a black level image signal is input to this circuit.

Regarding the blue signal BIN, one line of this image data should be stored in the black level RAM78a.
Select A with the selector 82a (■), close the gate 80a (■), and open the gate 81a. That is, the data line is 151a
− + 152a + 153a, while RA
The address counter 84 of M78a is initialized with HSYNC and counts VCLK.
■ is output to the selector 83a so that the output 154a of a is input, and the black level signal for one line is R A
M78a (hereinafter referred to as black reference value import mode).

When reading an image, the RAM 78a is in a data read mode, and each line and each pixel is read out and inputted to the B input of the subtracter 79a via the data lines 153a-157a. That is, at this time, the gate 81a
is closed (■), and 80a is open (■). Also, selector 8
6a has eight outputs. Therefore, the black correction circuit output 1 56
a is for black level data DK (i), for example, in the case of a blue signal B I N (1) DK (+) BOIJ
(referred to as black correction mode). Similarly, Green GIN + Red RIN is 77aG, 7
Similar control is performed by 7aR.

In addition, the control lines of each selector gate of this control
, ■, ■, ■ are performed under CPU control by latch 85a assigned as I/O of CPU 22 (FIG. 2). Note that the selectors 82a, 83a, 86a are
RAM 7 by the CPU 22 by selecting
8a becomes accessible.

Next, white level correction (shading correction) in the black correction/white correction circuit 506a will be explained with reference to FIG. White level correction corrects variations in sensitivity of the illumination system, optical system, and sensor based on white data obtained when the document scanning unit is moved to the position of a uniform white plate and irradiated. The basic circuit configuration is shown in FIG. 6(a). The basic circuit configuration is shown in Figure 5 (
This is the same as a), but the only difference is that the subtracter 79a performs the correction in the black correction, whereas the multiplier 79'a is used in the white correction, so a description of the same parts will be omitted.

CCD (500a
) is at the reading position (home position) of a uniform white plate, that is, before a copying or reading operation, an exposure lamp (not shown) is turned on and the uniform white level image data is corrected by one line R A M78' Store in a. For example, if it has an A4 longitudinal width in the main scanning direction, 16pej7/mm is 16X 2 9 7
m m = 4 7 5 2 pixels, that is, the RAM capacity is at least 4752 bytes, and as shown in FIG.
2), data for the white plate for each pixel is stored in the RAM 78'a as shown in FIG. 6(C).

On the other hand, for Wi, the read value Di of the normal image of the i-th pixel is corrected data Do = Di XFFH
/Wi. Then, the CPU 22 sends the latches 85'a■',■'. Kate 80 for ■′,■′
'a, 81' Open a and select selector 82'
a, 83' a, 86' A is output so that B is selected, and RAM 7g'a is made accessible to the CPU.

Next, in the procedure shown in FIG. 6(d), the CPU 22 performs FFH/Wo for the first pixel WO, FF/W for W, .
The data is replaced by sequential calculations. When the blue component of the color component image is completed (Figure 6(d) Step B)
Similarly, green component (StepG), red component (St
epR), and then the original image data D that is input.
For i, D o = D r X F F H /
Gate 80'a is open so that W+ is output (■')
, 81' a is closed (■'), selector 83' a,
86'a is selected as A, and the coefficient data FFH/Wi read from the RAM 78'a is connected to the signal line 153a-"1.
Original image data 151 input from one side through 57a
The product is multiplied by a and output.

As described above, the black level and white level are corrected based on various factors such as the black level sensitivity of the image input system, the dark current variation of the CCD, the sensitivity variation between each sensor, the optical system light amount variation, and the white level sensitivity. Image data BQ (
JT 101, G QLJ7 102, Ro,,1
03 is obtained. The white and black level-corrected color separation image data obtained here are created by detecting pixels on the image having a specific color density or a specific color ratio according to instructions from an operation unit (not shown), and The data is sent to a color conversion circuit B that converts the data into another color density or color ratio instructed by the operation unit.

Color Conversion> FIG. 7 is a block diagram of color conversion (gradation color conversion and density color conversion). The circuit in Figure 7 is an 8-bit color separation signal RIN.
+ GIN + BIN (1b to 3b); a color detection section 5b for determining an arbitrary color set in the register 6b by the CPU 20; and an area signal Ar4b for performing color detection and color conversion for a plurality of locations. A line memory lob that performs processing to spread a signal indicating that it is a specific color (hereinafter referred to as a hit signal) outputted by the color detection unit in the main scanning and sub-scanning directions (in the example shown in Fig. 7, only the sub-scanning direction).
-1lb, OR gate 12b, expanded hit signal 3
4b and non-rectangular signals (including rectangular signals) Color conversion enable signal 33b generated from BHi 27b, enable signal 33b and input color separation data (R INI G IN.B
IN lb-3b), line memories 13b-16b for synchronizing area signal Ar4, delay circuit 1
7b~20b1 enable signal 33b, synchronized color separation data (RIN + GIN + B
IN' 2lb to 23b), area signal Ar' 24
b and the CPU 20, a color conversion section 25b performs color conversion based on the color data after color conversion set in the register 26b;
I G OLIT I B out 28b~3
0b), ROtjT + G OutT r BO (
Hit signal H output in synchronization with JT. Consists of u■3lb.

Next, we will outline the algorithms for gradation color determination and gradation color conversion. Here, gradation color judgment and gradation color conversion mean color judgment and conversion of the same hue in order to save the density value and perform color conversion for colors of the same hue when performing color judgment and color conversion. It is to perform a transformation.

It is known that for the same color (certain hue), for example, a red signal R, a green signal G, and a blue signal B have the same ratio.

Therefore, data M of one of the colors to be converted (maximum value color, hereinafter referred to as principal color) is selected, and the ratio between it and the data of the other two colors is determined. For example, and the input data Rl
+ For Gl, Bl, M, X γ1 ≦
Ri≦M, X γ2 However, α1, β1l γ1≦
1 A pixel for which α2・β2・γ2 ≧1 is determined to be a pixel to be subjected to color conversion.

Furthermore, the data after color conversion (R 2 + 62 1 B
2) is also the main color (maximum value color here) in the data
The ratio between the data M2 and the data of the other two colors is calculated.

For example, when G2 is the main color, it is set as M2-62, and for the main color M1 of input data, if the data is a color conversion pixel, and if it is not a color conversion pixel, then (R+, G+, Bl )
Output.

As a result, all parts of the same hue with gradation are detected,
It becomes possible to output color conversion data according to gradation.

FIG. 8 is a block diagram showing an example of a color determination circuit. This part is a part that detects pixels to be color-converted.

In this figure, 50b is R, N bl, G, N b2
, B, N b3 is a smoothing unit that smooths the input data, and 5lb is a selector that selects one of the outputs (primary color) of the smoothing unit.Selectors 52bR, 52bo, and 52b8 are the output of the selector 5lb and a fixed value R. . Selector for setting, 56bR, 56
bo, 56bB and 57bRl 57b0, 57b8 are multipliers that calculate the respective upper and lower limits.

Further, each upper limit ratio register 58bR. 58b. ．． 58bIll1 lower limit ratio registers 59bR, 59bo, 59b can each set data for color detection for a plurality of areas based on the area signal A'30.

Here, ArlO, Ar20, Ar30 are the seventh
These are signals created based on Figure Ar4b, each containing the required number of stages of DF/F. Also, 6lb is an AND gate, 6
2b is an OR gate, and 67b is a register.

Next, we will explain the actual movement. R,N bl,G,N
One of the data R', G', B' obtained by smoothing b2, B, N b3, respectively, is sent to the CPU2.
The selector 5lb is set by the select signal S1 set to 0.
Select to select the main color data. Here, C.P.
U20 sets different data A and B in registers 65b and 66b, respectively, and selector 63b selects either A or B according to the ArlO signal and inputs it to selector 5lb as an S1 signal.

In this way, prepare two registers, 65b and 66b,
By inputting different data to A and B of the selector 63b and selecting one of them using the area signal ArlO, it is possible to perform separate color detection for a plurality of areas. This area signal ArlO may be a signal for not only a rectangular area but also a non-rectangular area.

In the next selectors 52bR, 52bo, 52b8,
R set by the CPU 20. Either +GO+BO or the main color data selected by the selector 5lb is selected by a selection signal generated by the outputs 53ba to 53bc of the decoder 53b and the fixed color mode signal S2. In addition, the selectors 64bR, 64bo,
By selecting either A or B according to the area signal Ar20, the sensor 64bB can detect different colors in a plurality of areas, as in the case of the selector 63b. Here, Ro, Go, and Bo are selected when the main color is in conventional color conversion (fixed color mode) and gradation color determination, and the main color data is selected when it is a color other than the main color in gradation color conversion. .

Note that the operator can freely select between fixed color determination and gradation color determination from the operation section. Alternatively, it is also possible to change it by software using color data (color data before color conversion) input from an input device such as a digitizer.

These selectors 52bR, 52bo, 52b
The upper limit and lower limit values of R'G' and B' are calculated by the multiplier from the output of 56bR, 56bo, 56b8 and 57bR,
57b, , 57b8 and set as upper and lower limit values in window comparators 60bR, 60b, , 60b8.

Window comparator 60bR, 60bo, 60b8
The AND gate 6lb determines whether the data of the main color falls within a certain range and the two colors other than the main color fall within a certain range. The register 67b can set "1" regardless of the determination signal by the enable signal 68b of the determination section. In that case, the color to be converted exists in the portion marked with "1".

The above configuration enables fixed color determination or gradation color determination for a plurality of areas.

FIG. 9 is a block diagram of an example of a color conversion circuit.

? The circuit selects the color-converted signal or the original signal based on the output 7b of the color determining section 5b.

In FIG. 9, the color conversion unit 25b includes a selector lllb, registers 112bR1+112bR2, which set the respective ratios of the converted colors to the principal color data (maximum value here),
112b,,,112ho2,112b8,,ll2b
8■, multiplier 113bR, 113b,, ll3
bB, selector l14bR, l14b0, 114b8,
Selector 115bR, 115b,,l15b,,AND
CP by Ar50, Ar60, Ar70 generated based on the gate 32b1 area signal Ar'24 in FIG.
Selectors 117b, 112bR, 112b, , which set the data set by U20 to selector Illb, multipliers 113bR, 113b, 113b8, and selectors 114bR, 114b, 114bB,
l12bB, 116bR, 116bo, l16b
The delay circuit 118b includes a delay circuit 118b.

Next, we will explain the actual movement.

Selector lllb receives input signal R I N '2lb
, G , N' 22b, B , N' 23b (principal color)? The selection is made according to the selection signal S5. Here, the signal S5 is the area signal A for the two data set by the CPU 20, and the area signal A r40 is the selector 117b.
This is generated by selecting either A or H. In this way, color conversion processing for multiple areas becomes possible.

The signal selected by selector itlb is sent to multiplier 113.
Multiplication with the register value set by the CPU 20 is performed in bR, l13bo, and 113b8.

Here again, the area signal Ar50 has two register values 112
bR, -112bR■, ll2b,, - 11
By selecting 2b, 2, and 112ber/112b8■ by selectors 112bR, 112bo, and 112b8, respectively, different color conversion processing can be performed for a plurality of areas.

Next, selector ll4bR. ll4bQ. The result of multiplication in ll4bB and the two fixed values Ro' set by the CPU 20
*Ro', Go' ・Go, Bo
-Bo inner area signal Ar 70 selector l
One of the fixed values selected in 16bR, 116b0, and 116b8 is selected by mode signal S6. Is this also a mode? The signal S6 is selected by the area signal Ar60 in the same manner as S5.

Finally selector l15bR, 115bllI, 115b
RINGIN using the select signal S8 at B.
+ BIN (RIN I GIN I BIN delayed and timing adjusted) and selector 114bR,
ll4bG, 114bB is selected, and ROLIT+Gout. Output as BOUT. Also hit signal H. U1 is also R. IJTIGou■＋
BO (output in synchronization with IT).

Here, the selector signal S8 is a delay product obtained by ANDing the color determination result 34b and the color conversion enable signal BHi34b. If a non-rectangular enable signal, such as the dotted line in FIG. 10, is input as the BHi signal, color conversion processing can be performed on a non-rectangular area. In this case, the area signal is an area like the one-dot chain line, that is, the top left (Fig. 1O a), the top right (Fig. 1O b), the bottom left (Fig. 1O C), and the bottom left found from the dotted lines. (Fig. 10, d). Further, the non-rectangular area signal BHi is input from an input device such as a digitizer.

When performing color conversion using this non-rectangular enable signal,
Since the enabled area can be specified along the boundary of the area to be converted, the threshold for color detection can be expanded compared to conventional color conversion using rectangles. Therefore, the detection ability is further improved, and an output image subjected to gradation color conversion with high accuracy can be obtained.

From the above, color conversion with brightness according to the main color of the color judgment unit 5b (for example, when converting red to blue, light red is converted to light blue and dark red is converted to dark blue) or fixed value color conversion You can freely perform any of the following for multiple areas.

Hit signal I] as described further below. U. Based on this, it is possible to perform mosaic processing, texture processing, trimming processing, masking processing, etc. only on a specific color area (non-rectangular or rectangular).

Then, as shown in FIG. 2, the output 103 of the color conversion circuit B,
104 and 105 are a logarithmic conversion circuit C1 for converting image data proportional to reflectance into density data; a character image area separation circuit L1 for discriminating character areas, halftone areas, and halftone areas on a document; and this system. External device interface M for communicating data with external devices via cables 135, 136, 137
will be sent to.

Next, the color image data proportional to the input light amount is
The signal is input to a logarithmic conversion circuit C (FIG. 2) which performs processing to match the luminosity characteristics of the human eye.

Here, white = 00 H, black 2FFl{ is converted as much as possible, and the image sources input to the image reading sensor, for example, a normal reflective original, a transparent original such as a film projector, and even the same transparent original as a negative film, Since the input gamma characteristics differ depending on the sensitivity and exposure condition of the positive film or film, as shown in Fig. 11(a),
As shown in (b), there are a plurality of LUTs (look-up tables) for logarithmic conversion, which are used depending on the purpose. Switching is performed by signal lines 1gO, Igl, and ng2, and is performed by inputting an instruction from an operation unit or the like as an I/O port of the CPU 22 (FIG. 2). Here each B
The data output for , G, and R corresponds to the density value of the output image. Mouth-). M (magenta). Since this corresponds to the C (cyan) toner image, subsequent image data will be associated with yellow, magenta, and cyan.

Next, the color correction circuit D performs color correction as described below on each color component image data from the original image obtained by logarithmic conversion, that is, yellow component, magenta component, and cyan component. As shown in Fig. 13, the spectral characteristics of the color separation filters arranged for each pixel in the color reading sensor have unnecessary transparent areas such as the shaded areas, while the spectral characteristics of the color separation filters arranged for each pixel on the color reading sensor have unnecessary transmission areas such as the shaded areas. Color toner (Y, M, C)
It is also well known that the absorbent components have unnecessary absorption components as shown in FIG. 14. Therefore, each color component image data Yi, Mi,
Masking correction is well known in which color correction is performed by calculating a linear equation for each color for Ci. Furthermore, by Yi, Mi, Ci, Min (Yi, Mi, Ci) (Yi,
The minimum value of Mi, Ci) is calculated, and this is sumi (minimum value of Mi, Ci).
As black), an operation of adding black toner later (smearing) and an undercolor removal (UCR) operation of reducing the amount of each coloring material added according to the added black component are also often performed. FIG. 12(a) shows the circuit configuration of a color correction circuit D that performs masking, smearing, and UCR. The characteristics of this configuration are: ■ It has two masking matrices and can be switched at high speed with one signal line "I/O". ■ It has one signal line "I/O" with and without UCR. /O" can be switched at high speed. (2) It has two circuits for determining Sumi 1, and can be switched to high distance with "l/0".

First, prior to image reading, a desired first matrix coefficient M H and a desired second matrix coefficient M2 are set via a bus connected to the CPU 22 . In this example, M, is assigned to registers 87d to 95d, and M2 is assigned to register 96d-1.
It is set to 04d.

Also, llld~122d, 135d, 131d, 13
6d is a selector, which selects A when the S terminal is "1" and selects B when it is "0". Therefore, when selecting matrix M1, switching signal MAREA364 "1"
”, if matrix M2 is selected, it is set to “0”.

Further, 123d is a selector and a selection signal C. ,C
, (366d), 367d), Figure 12 (
Outputs a, b, and c are obtained based on the truth table of b). Selection signal C. + CI and C2 correspond to color signals to be output, for example, in the order of Y, M, C, Bk (
C2, CI, CO) = (0, 0.0), (
0, 0. 1), (0, l, 0). (t,
o, 0), and further as a monochrome signal (0, 1.
1), a desired color-corrected color signal is obtained. Now (Co, C I, C2) = (o, o,
o), and MAREA="B, then selector 123
The outputs (a, b, c) of d have registers 87d,
88d, 89d, therefore (aye, -bv
+, -Cc+) is output. On the other hand, the input signal Yi,M
Min from i, Ci (Yi, Mi, Ci)
The black component signal 374d calculated as =k undergoes a linear transformation of Y=ax-b (a, b are constants) at 137d, and is input to the B inputs of subtracters 124d, 125d, and 126d. In each subtractor 124d to 126d, Y=Yi − (ak− b ), M
= M i − (ak − b), C =
C i - (ak - b) is calculated and sent to multipliers 127d, 128d, 1 for masking operation via signal lines 377d, 378d, 379d.
29d.

The multipliers 127d, 128d, and 129d each have eight inputs ( a Yl , - b Ml
．． - C c1), and the B input has the above-mentioned (Y i
- (ak - b), M i - (
a k − b ), Ci − (ak − b))
= (Yi, Mi, Ci) is input, so as is clear from the figure, output D. Y for U1 under the condition of C2=0 (Y or M or C). U1=?
ix (av+) +Mix (-bMt) +CiX
(-Cc+) is obtained, and yellow image data that has been subjected to masking color correction and undercolor removal processing is obtained. Similarly, M(,,)7 =YiX(-ayz)+MiX(-bM
2)+CiX(-CC2)C,) U7 =YiX(
1ay3)+MiX(-bM3)+CiX(-CC3
) is D. It is output to u■. Select colors according to the order of output to the color printer (co.CI, C2)
is controlled by the CPU 22 according to the table in FIG. 12(b). Registers 105d-t07d, 108d-1
10d is a register for monochrome image formation, and based on the same principle as the above-mentioned masking color correction, MONO=k1
Yi+1!1 Mi+m, Ci is obtained by weighted addition for each color.

Further, when Bk is output, C2 (168) is input as a switching signal to the selector 131d, so that C2=11, so it undergoes a linear conversion such that Y=cx-d in the primary converter 133d, and is output from the selector 131d. Also, Bk
MJ110 is a black component signal output to the outline of a black character based on the output of a character image area separation circuit I, which will be described later. Color switching signals CoC, , C2' 366 to 368 are set from the output port 501 connected to the CPU bus 22, and MAREA 364 is output from the area signal generation circuit 364.

The gate circuits 150d to 153d output a signal C when DHi is "1" based on a non-rectangular area signal DHil22 read from a binary memory circuit (bitmap memory) L537, which will be described later. , Cl ”2 ”“l, l
, 0'' and automatically outputs data for m o no images.

Character image area separation circuit Next, the character image area separation circuit I uses the read image data to determine whether the image data is a character or an image, and whether it is chromatic or achromatic. This is a circuit that determines whether The flow of the process will be explained using FIG. 15.

Red (R) 103, green (G) 104, blue (
B) 105 is a minimum value detection circuit MIN (R+G
*B) 101■ and maximum value detection circuit Max (R,
G, B) is input to 102■. In each block, the maximum value and minimum value are selected from the three types of input luminance signals R, G, and B. A subtraction circuit 1041 calculates the difference between the selected signals. If the difference is large, that is, the input R, G, and B are not uniform, the signal will not be an achromatic color that indicates black and white, but a chromatic color that is biased towards some color. Naturally, if this value is small, it means that the R, G, and B signals are at approximately the same level, and it can be seen that the signal is an achromatic signal and not a signal that is biased towards any color. This difference signal is output to the delay circuit Q as a gray signal GR124. In addition, this difference is stored in register 1 by the CPU.
Threshold value arbitrarily set in 111 and comparator 112
1, and the comparison result is sent to the gray judgment signal GRBil26.
and outputs it to the delay circuit Q. These GRl25,
After the GRBil26 signal is matched in phase with other signals in delay circuit Q, it is sent to character image correction circuit E, which will be described later.
and used as a processing judgment signal.

The minimum value signal obtained in M, N (R, G, B) 1011 is also input to an edge emphasis circuit 1031. The edge emphasis circuit performs the following calculation using front and rear pixel data in the main scanning direction. Edge enhancement is performed.

? )ou■: Image data Di after edge enhancement
: i-th pixel data Note that edge enhancement is not necessarily limited to the above method, and other known techniques may be used. The image signal edge-enhanced in the main scanning direction is then
Then, the average value calculation within the 3×3 window is performed with a 5×5 average of 1091 and a 3×3 average of 1101. Line memories 1051 to 108I are delay memories in the sub-scanning direction for performing averaging processing. 5×5 average 1 091
The 5×5 average value calculated in is then combined with an offset value independently set in an offset section connected to CPUBUS (not shown) and adders 1151, 1191,
124I is added. The added 5×5 average value is Limiter 1 113I, Limiter 2 1181,
Input to limiter 3 123I. Each limit is
They are connected by CPUBUS (not shown), and are configured so that limiter values can be set independently for each.
5 If the average value is greater than the set limiter value, the output is clipped at the limiter value. Output signals from each limiter are input to comparator 1 1161, comparator 2 1211, and comparator 3 1261, respectively. First, the comparator 1 1161 compares the output signal of the limiter 1 1131 with the output from the 3×3 average 110I. Compared comparator 1
The output of 116I is sent to a halftone area discrimination circuit 1221, which will be described later.
Delay circuit 117 to match the phase with the output signal from
It is input to I.・This binarized signal is binarized using the average value to prevent distortion and skipping due to MTF at a certain density or higher, and the halftone dots of the halftone image are also binarized. A 3x3 low-pass filter is used to cut the high frequency components of the halftone image so that they are not detected. Next, the output signal of the converter 2 (1211) is binarized with the through image data to detect high frequency components of the image so that it can be discriminated by the halftone area discriminating circuit 1221 in the subsequent stage. Halftone area discrimination circuit 1 221
Since the halftone image is made up of a collection of dots, the dots are detected from the direction of the edge, and then the number of dots around the edge is counted. A detailed explanation of the halftone dot area discrimination circuit 1222 will be omitted since it is not the subject matter of this patent.

An OR game}1291 is performed between the result determined by the halftone dot area determination circuit in this way and the signal from the delay circuit 117.
After removing the erroneous judgment, the erroneous judgment is removed by the erroneous judgment removal circuit 130I, and then outputted to the AND gate 132I.

In this false judgment removal circuit 1301, taking advantage of the characteristics that characters and the like are thin and images have a wide area, first, the image area of the binarized signal is narrowed, and an isolated image area is taken. Specifically, for the center pixel xij, the surrounding 1 m
When even one pixel other than the image exists within the m-square area, the central pixel is determined to be outside the image. After removing the image area of the isolated point in this way, thickening processing is performed to restore the thin image area to its original size. Similarly, halftone discrimination circuit 1 22
The output of 1 is directly input to the erroneous determination removal circuit 131I, where thinning processing and thickening processing are performed. Here, the mask size for the thinning process is the same as the mask size for the fattening process. There is. Specifically, both the false judgment removal circuits 130I and 1311 are 17X.
After thinning with a 17 pixel mask, further thinning is performed with a 5×5 mask, and then thickening processing is performed with a 34×34 pixel mask. The output signal SCRN signal 127 from the misjudgment removal circuit 1311 is a discrimination signal for smoothing only the halftone dot determination section in a character image correction circuit E, which will be described later, to prevent moiré in the read image.

Next, the output signal from the converter 3 1261 is used to extract the outline of the input image signal in order to sharpen the characters at a later stage. As an extraction method, the output of the binarized comparator 3 1261 is thinned and thickened in 5 x 5 blocks, and the difference area between the fattened signal and the thinned signal is contoured. shall be. The contour signal extracted by such a method must match the phase with the mask signal output from the false determination removal circuit 1301. After passing through the delay circuit 128I, the contour signal is determined by the AND gate 1321 to be a mask signal and an image. The contour signal in the part where the characters are printed is masked, and only the contour signal in the original character part is output. The output from AND gate 132I is then output to contour regenerator 1 331.

Contour Regeneration Unit> Contour Regeneration Unit 1 331 processes pixels that are not determined to be character contour parts to become character contour parts based on information of surrounding pixels, and as a result, converts MjArl24 into a character image correction circuit. The data is sent to E and the processing described below is performed.

Specifically, as shown in Figure 16 (bold letters ((a) in the same figure)
, the character determination unit determines the dotted line part in (b) as a character and performs the processing described below.
Regarding C)), the character part becomes as shown in the dotted line part in FIG. 3(d), and if the processing described below is performed, it may become unsightly due to erroneous determination. To prevent this, the parts were not recognized as characters. Processing is performed to make it a character part based on surrounding information. Specifically, by making the diagonal line part the character part, the character part becomes as shown in the dotted line part (e) in the same figure, which reduces misjudgments even for characters that are so thin that they are difficult to detect, leading to improved image quality. .

FIG. 17 is a diagram showing how surrounding information is used to regenerate a pixel of interest into a character portion.

(a) to (d) are 3 x 3 blocks, with the pixel of interest as the center, and both vertical, horizontal, and diagonal text portions (S, S2 are both "l")
When , the pixel of interest is set as a character portion regardless of the information of the pixel of interest. On the other hand, (e) to (h) are 5x5 blocks with l pixels centered around the pixel of interest, and both vertically, horizontally, and diagonally are text parts (SII82 also "B"), regardless of the information of the pixel of interest. This two-stage structure (multiple types of blocks) makes it possible to deal with a wide range of errors.

FIGS. 18 and 19 are circuits for realizing the process shown in FIG. 17. The circuits shown in FIGS. 18 and 19 include line memories 164i to 167i, and DF/F104f-126i for obtaining information around the pixel of interest.
, In order to realize Fig. 17 (a) to (h), (7)A
ND gates 146i to 153i and OR gate 154
Consists of i.

Figure 17 (
The information of S, , S2 in a) to (h) is extracted. Further, registers 146i to 153i can independently control enable and disable, respectively, by registers 155i to 162i corresponding to the processes (a) to (h).

AND circuits 146i to 153i and FIG. 17(a) to (
The correspondence relationship in h) is as follows.

FIG. 20 shows W1(
This is a timing chart of RE (ENI) and RE (EN2). This is done so that ENI and EN2 are output at the same timing when the image is enlarged to the same size, or WE is written once in two thinned-out lines when the image is enlarged (for example, 200% to 300%).

This expands the size of FIGS. 17(a) to (h).

This is because when enlarging, the information that enters here is an image enlarged only in the sub-scanning direction, so by increasing the size of (a) to (h), processing is performed using the same size image even when enlarging. I'm going to

Character Image Correction Circuit> The character image correction circuit E performs the following processing on black characters, color characters, halftone images, and halftone images, respectively, based on the determination signal generated by the character image area separation circuit I described above.

[Processing 1] Processing related to black characters (1-1) Signal Bk obtained by black-mark extraction as video
Using Mjll2 (1-2) Y, M, C data are multivalued achromatic chromaticity signals GR
125 or according to the set value. On the other hand, Bk
The data is a multivalued achromatic chromaticity signal GR125. If << is added according to the setting value (1-3) Edge emphasis is performed [l-4] Black characters are printed out at 400 lines (400 dpi) [1-53] Perform color residual removal processing [Processing 2] Processing related to colored characters [2-1] Perform edge emphasis (2-2) Print out colored characters at 400 lines (400 dpi) [Processing 3] Regarding halftone images Processing (3-1: Perform smoothing (2 pixels in the main scanning direction) to prevent moire [Processing 4] Processing related to halftone images (4-1) Select smoothing (2 pixels in the main scanning direction) or through possible.

Next, a circuit that performs the above processing will be explained.

FIG. 21 is a block diagram of the character image correction section E.

The circuit of FIG. 21 uses the video input signal 111 or BkM
a selector 6e that selects the selector 112, an AND gate 1-6e that generates a signal to control the selector, a block 16e that performs a residual color removal process to be described later, an AND gate 16e' that generates an enable signal for the same process, and a GR signal 125. A multiplier 9e' that multiplies the set value 10e of the I/O port, the multiplication result 10e or! /0 port selector lle that selects the setting value 7e, output 1 of selector 6e
a multiplier 15e that multiplies the output 14e of 3e and lie;
XOR game} 20e, AND gate 22e, adder/subtractor 24e, line memories 26e, 28e that delay line data, edge emphasis block 30e,
A smoothing block 31e, a selector 33e for selecting through data or smoothing data, a delay circuit 32e for synchronizing control signals of the selector,
A selector 42e for selecting the result of edge emphasis or the result of smoothing, a delay circuit 36e and an OR gate 39e, A for synchronizing control signals of the selector.
ND gate 41e, 400 lines (dp
i) Consists of an inverter circuit 44e for outputting a signal ("L" output), an AND circuit 46e, an OR circuit 48e, and a delay circuit 43e for synchronizing the video output 113 and the LCHG 49e. Further, the character image correction section E is connected to the CPU bus 22 via the I/O port le.

Below is [1] Color residual removal processing that removes the color signal remaining around the edge of the black text area, and a certain percentage is subtracted from the Y, M, and C data of the black text area determination section, and a certain percentage is subtracted from the Bk data. [2] Edge enhancement for the text part, smoothing for the halftone judgment part, and part where through data is selected for other gradation images, [3] L for the text part.
The process will be divided into three parts, each of which will be explained: the part where the CHG signal is set to "L" (printed at 400 dpi).

[1] Color residue removal processing and addition/subtraction processing Here, processing is performed for the area where both the signal GRB 26 indicating that it is an achromatic color and the signal MjAR 124 indicating that it is a character area are active, that is, the edge area of the black character and its surrounding area. hand,
The Y, M, and C components protruding from the edges of black characters are removed, and the edges are filled in.

Next, a detailed explanation of the operation will be given.

This process is subject to character part determination (MjAR124="1"
), this is performed only when the text is black (GRBil26="1'") and the mode is color mode (DHil22="0"). Therefore, ND (black and white) mode (DHi=
This is not done when the character is a color character (GRBi="O").

When scanning a document for recording color Y, M, or C, the video manual 111 selects it with the selector 6e (I/O-
6 (“θ” is set in 5e)). 15e, 20e
, 22e, and 17e, data to be subtracted from the video 8e is generated.

For example, if "0" is set in I/O-312e, selector output data 13e
Multiplying by the value set in I/O-178 is performed by multiplier 1.
It takes place in 5e. Here, data 18e that is 1 times larger than 13e is generated. By setting 1 to registers 9e and 25e, the two's complement data of 18e becomes 17e,
Generated at 20e and 22e. Finally, adder/subtractor 24
Since addition 23e of 8e and 23e in e is a two's complement number, 17e-8e is actually subtracted and output from 25e.

1/0-312 When "'l" is set at e, B data is selected at selector lie.

At this time, the multivalued achromatic color signal GR125 generated by the character image area separation circuit I (a signal that takes a large value if it is close to an achromatic color) l::I/O-2 The value set in 10e is set in 9e. The multiplied value is used as the multiplier of 13e.

When this mode is used, the coefficients can be changed independently for each of the colors Y, M, and C, and the amount of subtraction can be changed depending on the achromatic degree.

When scanning recording color Bk, selector 6e selects BkMj1.
12 selected (I/O-65e “.1
"set). Data to be added to the video 17e is generated in 15e, 20e, 22e, and 17e. The above Y
, M, C, the difference is that "O" is set in I/O-4, 9e, which results in 23e==8e, Ci:=
0, and 17e+8e is output from 25e. The method of generating the coefficient 14e is the same as that for Y, M, and C. Also, in the mode in which 'l' is set in I/O-312e, the coefficient changes depending on the achromatic degree.Specifically, when the achromatic degree is large, the addition amount is large, and when it is small, the addition amount is small. Become.

This process is illustrated in FIG. 22. (a) and (c) are enlarged views of the shaded portion of the black letter N.

For Y, M, and C data, the subtraction from the video is performed when the character signal part is "1" (see figure (b)), and for Bk data, the character signal part is "1". is added to the video ((d) in the same figure). In this figure, 13e
=l8e, that is, the Y, M, and C data of the character section are 0, and the Bk data is twice that of the video.

Through this processing, the outline of black characters is printed in almost a single black color, but the 22nd Y, M, and C data outside the outline signal is
The * mark shown in Figure (b) remains around the characters as residual color, making it unsightly.

The color removal process removes the remaining color.

This processing extends to the area of the text area,
In addition, for pixels where the video data 13e is smaller than the conversion value set by the CPU, that is, outside the text area, where there is a possibility of color remaining, the process takes the minimum value of 3 or 5 pixels before and after. be.

Next, the explanation will be supplemented using a circuit.

Figure 23 shows a character area expansion circuit that works to expand the character area.
e and AND gates 69e, 71e, 73e,
75e and an OR gate 77e.

All I/O ports 70e, 72e, 74e, 76e
When MjArl24 is set to ``1'', when the signal is expanded by 2 pixels in the front and back in the main scanning direction to the I/O ports 70e, 75e''0'', 71e, 73e''1'', it is the main The signal expanded one pixel forward and backward in the scanning direction is Sig2 1
It is output from 8e.

Next, the remaining color removal processing circuit 16e will be explained.

FIG. 24 is a circuit diagram of residual color removal processing.

In FIG. 24, 57e is a 3-pixel min select circuit that selects the minimum value of a total of 3 pixels, including the pixel of interest and the pixels before and after it, for the input signal 13e; 58e is the input signal 13;
For e, select the maximum value of a total of five pixels, including the pixel of interest and two pixels before and after it. 5 pixel min select circuit, 55e
is a comparator that compares the magnitude of input signals 13e and 170-18 (54e), and if 54e is larger, l
Output. 61e, 62e are selectors, 53e,
53'e is an OR gate, and 63e is a NAND gate.

In the above configuration, the selector 60e selects 3 pixels min or 5 pixels based on the value of I/O-19 from the CPU bus.
Select pixel min. With 5 pixels min, the effect of color residual removal is greater. This can be selected by manual setting by the operator or automatic setting by the CPU.

The selector 62e is configured so that the output of the NAND gate 63e is “0”.
'', that is, the comparator 55e determines that the video data 13e is smaller than the register value 54e, and it is within the range of expanding the character part signal, and if 17'e is 1, the A side is selected, otherwise the video data 13e is determined to be smaller than the register value 54e. The B side is selected. (However, at this time, registers 52e and 64e are set to 'l''.
The register 52'e is "0") When the B side is selected, through data is output as 8e.

The EXCON 50e can be used in place of the converter 55e when, for example, a binary luminance signal is input.

FIG. 25 shows the area where the above two processes have been applied. FIG. 25(a) shows the black character N, and FIG. 25(b) shows the area determined as a character in the Y, M, and C data, which is the density data of the shaded area, that is, the character determination part (+2,
3, Cloud 6, +7) are reduced to 0 by subtraction processing, and Cloud 1, +4 are reduced to 0 by color residual removal processing.
← Yellow becomes 5, which results in 0, and Figure 25 (C) is obtained.

On the other hand, for B and data as shown in Figure 25(d),
Only addition processing is performed in the character determination section (Ku 8, Ao 9, Ku 10, Ku 11), resulting in an output with a black ring as shown in FIG. 25.

Note that no changes are made to the colored characters, as shown in FIG. 25(f).

[2] Edge Emphasis or Smoothing Process Here, processing is performed to output edge emphasis for the character determination section, smoothing for the halftone dot section, and outputting through for the others.

Character part → MjARl24 is “B, so 25e, 2
3×3 generated from 3 line signals of 7e and 29e
The output of the edge enhancement 30e is selected by the selector 42e and output from 43e. Note that the edge enhancement here is obtained from a matrix and calculation formula as shown in FIG.

Halftone area → SCRN35e is “1”, M j A R 2
Since 1e is "0", the smoothing 31e applied to 27e is the selector 33e4 42
It is output at e. Note that smoothing is the 27th
As shown in the figure, when the pixel of interest is vN (VN+VN+1
)/2 as vN data, that is, smoothing of two main scanning pixels. This prevents moiré that may occur in the halftone dot area.

Other→Other portions refers to processing for areas that are neither character portions (character outlines) nor halftone dot portions, specifically, midtone portions. At this time MjARl24 and SCRN35
Since both e are "on", the data of 27e is output as is from the video output 43e.

When the characters are colored characters, the above two processes are not performed even in the character determination section.

In the embodiment, an example was shown in which color residual removal was performed only in the main scanning direction, but color residual removal processing may be performed in both the main scanning and sub-scanning directions.

[3] Text section 400 lines (dpi) output processing video output 1
13, LCHG140 is output from 48e. Specifically, the inverted signal of MjAR 124 is output in synchronization with signal 43e. In the case of a character part, LCHG=0, and in other parts, 200/400="1".

As a result, the character part determination part, specifically the character outline part, is 4
00 line (dpi), and the others are printed at 200 line (dpi).

Next, the character image synthesis circuit F will be explained.

FIG. 28(a) is a block diagram of a circuit for processing and modifying images using binary signals in this apparatus. The color image data 138 inputted from the image data input section is inputted to the V input of the 3tol selector 45.

The other two inputs A and B of the 3tol selector 45f contain the lower part (An, B) of the data read out from the memory 43f.
ll) Eight of 555f have An, and B has B,l
is latched by VCLK117 in latch 44f and input. Therefore, the output Y of the selector 45F is the selection force X. , X,, Jl, J2
Either V, A, or B is output based on (11
4).

In this embodiment, data Xn is the top two data in memory.
This bit is a mode signal that determines processing and modification. 139 is a code signal output from the area signal generation circuit.
It is controlled to switch in synchronization with 117, and the memory 43f
is entered as the address of

That is, for example, (X
I(In AIon B+o) = (Olm AI
(1, B+o), and in synchronization with the scanning of line l in the main scanning direction, write "10" from point P to point Q in the code signal 139 from point Q to point R, as shown in FIG. 29(b). If “O” is given until
= (0, l) is read and at the same time (All, Bn
) data (A+o+B+.) is latched and output. The truth table of 3t01 selector 45 is the 28th
As shown in Figure (c) <, (X I. xo) = (
0. 1) is the case of (B), and if Jl is "Bi," the 8 inputs are set to Y, so Y is a constant A, and J1
If is "0", it means (1) that the input is Y, and therefore the input color image data is output as is to the output 114. In this way, for example, so-called tweezers character synthesis of a character portion having a value of (Ago) is realized for a color image of an apple as shown in FIG. 29(b). Similarly, set (X+, Xo) = (1, O), and enter the 29th
When a signal like Jl in figure (C) is input, FIF0
47f to 49f1 and circuit 46f (details in Fig. 28(b)
)), a signal as shown in 12 of the same figure is generated, and the 28th
If we follow the truth table in figure (C), the characters will be output with frames in the apple image as shown in the figure (contours,
or bag characters).

Similarly, in FIG. 28(D), the rectangular area inside the apple is (
B. ), and the characters inside are output with a density of (An). In the same figure (A), (x+'.xo) =
(0. 0), that is, for any Jl, J
Depending on the binary signal, there is a control that does not perform anything even for a change of 2.

The signal with expanded width input to J2 is shown in Fig. 28(b).
According to , it is an expansion of 3×3 pixels, but it is easy to make it even thicker by adding a hardware circuit.

In addition, CO, CI (366, 367) output from the summer/0 port 501 in FIG. 2 in association with the output colors (Y, M, C, Bk) to be printed are
It is input to the lower 2 bits of the address of 3f, and therefore "0.0", corresponding to the output of Y, M, C, Bk.
"O, 1", "1. 0", "l, l
”, so for example, when outputting yellow (Y),
, 4, 8, 12. 16...Address, magenta (M
) is the address 1, 5, 9, 13, l7..., and cyan (C) is 2, 6, 10, 14. 18・
・The street address, black (Bk) is 3, 7, If, 1
5. 19...An address is selected. Therefore, according to an operation instruction on the operation panel, which will be described later, the address corresponding to the area code signal 139 that determines the area and the corresponding memory address within the area, for example, XI to X4='1. 1”
(AI, A2, A3, A4) = (αl, α2, α3
, α4), (Bl, B2, B3, B4) = (β
l, β2, β3, β4), for example, the second
When the Jl signal changes as shown in Figure 9 (D), Jl becomes “L”.
o” section is (Y, M, C, Bk) = (αl, α2
, α3, α4), and Jl is “H
i”, (Y, M, C, Bk) = (βl, β2,
The color is determined by the combination of β3 and β4). In other words, the output color can be arbitrarily determined based on the memory contents. On the other hand, on the operation panel described later, Y, M, C, and Bk are each adjusted or set in percent (%). That is, each gradation 8b
Since I have it, the numerical value is 00 to 255, so
A 1% change is a digital value of 2.55.

Setting values are (Y, M, C, Bk) = CY%, m%, C%
, k%), the values to be set (i.e., the values written to memory) are (2.55Y, 2.55Y), respectively.
m, 2.55c, 2.55k), and in reality, the rounded integer is written into a predetermined memory. Furthermore, if the adjustment mechanism is used to adjust in %, the value obtained by adding (to make it darker) or subtracting (to make it tingle) by 2.55 Δ for the change in % may be written in the memory.

In the truth table of FIG. 28(c), the i column is an input/output table for characters, image gradation, and resolution switching signal LCHG149, and x, , Xo. When A or B is outputted to output Y by Jl and J2, it becomes "0", and when V is outputted to Y, the input is outputted as is. LCHG149 is a signal for switching the print density during printing, for example, when LCHG-“0”, for example, 400 dpi, L
When CHG=“i” (7), print at 200 dpi. Therefore, when A or B is selected, LCHG=O means that the inner area of the synthesized character is 400 dpi,
This means that areas other than text are printed at 200 dpi, and the text is controlled to maintain high resolution, sharp halftone areas, and high gradation, and to be output smoothly. This is why, as described above, the LCHG 140 outputs the output from the character image correction circuit E based on MJAR, which is the output from the character/image separation circuit I.

<Image processing/editing circuit> Next, image signal 1 after undergoing color balance adjustment at P
15 and the gradation resolution switching signal LCHG141 are input to the image processing and editing circuit G. A rough schematic diagram of the image editing processing circuit G is shown in FIG.

Input image signal l15, gradation resolution switching signal LC
The HG 141 is first input to the texture processing section 101g. The texture processing section is roughly divided into a memory section 103g that stores texture patterns, memories RD and WR that control them, an address control section 104g, and an arithmetic circuit 105g that performs modulation processing on input image data according to the stored pattern. has been done. The image data processed by the texture processing section 101g is then subjected to scaling, mosaic, and taber processing section 1.
02g. The scaling, mosaic and Taber processing unit 102g has double buffer memory 105g, 10
6g and a processing/control unit 107g, various processes are independently performed and output by the CPU.

Here, the texture processing section 101g and the scaling, mosaic, and taber processing section 102g receive a G.I. Hil (119)
and GHi2 (149) are configured to perform texture processing and mosaic processing on independent areas.

Further, the gradation resolution switching signal LCHG signal 141 input together with the image data 155 is processed in various processes while matching the phase with the image signal.

The image processing/editing circuit G will be explained in detail below.

<Texture processing section> Texture processing is a process of cyclically reading out a pattern written in memory and applying modulation to the video. For example, the image shown in FIG. It modulates the image in a pattern like this to generate an output image like that shown in FIG.

FIG. 32 is a diagram illustrating the texture processing circuit.

Below, modulation data 2 to texture memory 113g
18g writing section and 113g texture memory
216g of data and 215g of image data (
Texture processing) will be explained separately.

[Data writing section to texture memory 113g] When writing data, masking, undercolor removal, and smearing are performed, and data is input from 201g. This data is selected by selector 202g. On the other hand, selector 208
At g, data 220g is selected and memory 113g is selected.
W1 and the enable signal of the driver 203g. The memory address is generated by a vertical counter 212g that counts up in synchronization with the horizontal synchronization signal HSYNC, and a horizontal counter 211g that counts up in synchronization with the image clock and VCK.B is selected by the selector 210g, and the address of the memory 113g is generated. Enter.

In this way, the density pattern of the input image is stored in the memory 11.
Written to 3g. Typically, this pattern is an input device,
For example, it is located and written using a digitizer.

(Writing data by CPU) CPU data is selected by the selector 202g.

On the other hand, A is selected by the selector 208g, and the memory 11
3g and the enable signal of the driver 203g. As the memory address, A is selected by the selector 210g and inputted to the address of the memory 113g. thus,
An arbitrary density pattern is written into memory.

[Calculation unit for texture memory 113g data 216g and image data 215g] This calculation is realized by a calculation unit 215g. This arithmetic unit here consists of a multiplier. Data 216g and 201 only where enable signal 128g is active
An operation with g is performed, and when the disable is enabled, the signal 201 becomes a through state.

Also, 300g and 301g are XOR and OR gates, respectively, and register 304 is a part that generates an enable signal using MJ signal 308g, that is, a character synthesis signal.
When "O" is set in the register g'''1''305g, texture processing is applied to areas other than those containing composite character signals. On the other hand, when "0" is set in the register 304g and 305g, only the part containing the composite character signal is subjected to texture processing.

302g is a portion that generates an enable signal using a GHil signal 307g, that is, a non-rectangular signal. When the register 306g is "θ", texture processing is performed only where the GHil signal is enabled. At this time enable 12
If 8 is kept active, non-rectangular texture processing is performed that is not affected by non-rectangular signals, that is, synchronized with HSNC.If enable signal GHil and enable 128 are made the same, texture processing is performed that is synchronized with non-rectangular signals. Become.

For example, if a 3 lb bit signal is used for GHil, texture processing can be performed only on a certain color.

The LCHG, N signal 141g is a gradation resolution switching signal, which is delayed by the amount of delay in the arithmetic unit 215g, and then output to LCHG.
Output from ouy 350g.

(Mosaic, scaling, and taper processing unit) Next, the general operation of the mosaic, scaling, and taper processing unit G12 of the image processing/editing circuit G will be described using FIG. 33.

The image data 1 26g and the LCHG signal 350g input to the mosaic, scaling, Taber processing section 102g are first input to the mosaic processing section 401g. The mosaic processing unit 401g uses Mj output from the character synthesis circuit F.
Signal 145 and area signal GHi21 from switching circuit N
49. After the mosaic clock MCLK from the mosaic processing control unit 402g determines the presence or absence of mosaic processing, the size of the mosaic in the main scanning direction, the composition of characters, etc.
It is input to the to2 selector 403g. Here, the main scanning direction size for mosaic processing is the mosaic clock M.
It is made variable by controlling CLK. Control of the mosaic clock MCLK will be explained in detail later.

1 to2 selector-403g, HSYNC118
The input image signal and LCHG signal are output to either Yl or Y2 by the line memory select signal LMSEL whose frequency is divided by the D flipflop 406G.

1 Output from Yl of to2 selector-403g is output from line memory A404g and 2tol selector-407
Connected to A of g. The output from Y2 is line memory 8405g and 2tol selector 40.
Connected to B of 7g. When an image is sent to line memory A from selector 403g, line memory A 404g is in write mode, and line memory 8405g is in read mode. Similarly, when an image is sent from the selector 403g to the line memory 8405g, the line memory B is in write mode.
And the line memory A404g is in read mode.

In this way, the image data read out alternately from line memory A 404g and line memory B 405g is 2to
The L selector 407g outputs continuous image data while switching based on the inverted signal of the LMSEL signal output from the D flip-flop 406g. The output image signal from the 2tol selector 407g is then sent to the enlargement processing section 41.
After predetermined enlargement processing is performed in 4g, the image is output.

Next, write/read control of these memories will be described. First, when writing or reading, line memory A
404g, the address given to the line memory 8405g is synchronized with HSYNC, which is the reference for one scan, and is synchronized with the image C
The up/down counter 409g. increments and decrements in synchronization with LK. 41
It is composed of 0g. A counter enable signal output from the line memory address control unit 413g,
The operation of the address counters (409g, 410g) is controlled by a control signal WENB for controlling a write address and a control signal RENB for controlling a read address generated from the scaling control section 415g. These controlled address signals are input to 2tol selectors 407g and 408g, respectively.

The 2tol selectors 407g and 408g provide a read address to the line memory A 404g and a write address to the line memory 8405g when the line memory A 404g is in the read mode in response to the above-mentioned line memory select signal LMSEL. When the line memory A 404g is in write mode, the opposite operation is performed.

Next, a memory write pulse WEASWEB to line memory A and line memory B is outputted from the variable magnification control section 415g. Memory write pulses WEA and WEB are used when reducing the input image and when the mosaic processing control unit 4
Mosaic processing is controlled by a mosaic length control signal MOZWE in the sub-scanning direction output from 02g.

Next, a detailed explanation of these operations will be given below.

<Mosaic Processing> Mosaic processing is basically realized by repeatedly outputting one image data.

This mosaic processing operation will be explained using FIG. 34.

First, a mosaic processing control unit 402g independently performs main scanning and sub-scanning mosaic processing control.

First, set the variable corresponding to the desired mosaic size to CPU
The CPU sets the latch 501g (for main scanning) and the latch 502g (for sub-scanning) connected to US.

First, for mosaic processing in the main scanning direction, the same data is written continuously to multiple addresses in the line memory, and for mosaic processing in the sub-scanning direction, writing to the line memory is performed at a specified line within the mosaic processing area. This is done by thinning out each time.

(Main scanning direction mosaic processing) A variable corresponding to the mosaic width in the main scanning direction is set in the latch 501g by the CPU. The latch 501g is connected to the main scanning mosaic control counter 504g,
The setting value is loaded by the I4SYNC signal and the ripple carry of the counter 504g. A counter 504g loads the value set in the latch 501g for each HSYNC, counts a predetermined value, and outputs ripple carry to the NOR gate 502g and AND gate 509g.

Mosaic clock MCL from AND gate 509g
K is a signal obtained by multiplying the image clock CLK by the ripple carry from the counter 504g, and MCLK is output only when the ripple carry occurs.

MCLK output from AND gate 509g is then input to mosaic processing section 401g.

The mosaic processing unit 401g operates two D flipflops 510g and 510 regardless of the Mj signal.
Output g. When the GHi2 signal 149 is 1 and the Mj signal is O, a signal from the flip-flop 511g controlled by the mosaic clock MCLK is output.

When the Mj signal is 1, the output is a flip-flop 510g
Output the signal from. With this control, it is possible to output a part of the mosaic-processed image in the main scanning direction without performing the mosaic process. In other words, it is possible to perform mosaic processing on only the image without performing mosaic processing on the characters that have been synthesized into an image by the preceding character synthesis circuit F as shown in FIG. The output from the selector 512g is input to the 2tol selector 403g shown in FIG. 33 mentioned above. As described above, mosaic processing in the main scanning direction is performed.

(Sub-scanning direction mosaic processing) Similarly to the main scanning direction, the sub-scanning direction is also controlled by a latch 502g connected to CPUBUS, a counter 505g, and a NOR gate 503g. The control counter during sub-scanning mosaic is ITOP signal 144, 51 1g, selector 512g, AND gate 514g, inverter 51
It is composed of 3g. Flip flop 510g,
In addition to the image signal, a gradation resolution switching signal LCHG is connected to the flip-flop 510g.
is the image clock CLK, flip-flop 511
g holds the image data inputted by the mosaic processing clock MCLK and the LCHG signal. In other words,
When the gradation resolution switching signal LCHG corresponding to one pixel is in phase, it is sent to the flip-flops 510g and 511g.
is held during each cycle of CLK and MCLK. Each retained image signal and LCHG signal is input to 2tol selector-512g. The output is switched by the mosaic area signal GHi2 and the binary character signal Mj signal. The selector 512g generates ripple carry pulses by counting HSYMCI18. The ripple carry pulse is the mosaic area signal GHi2 to the OR game 508g.
149 inverted signal GHi2 and character signal Mj are input. It is input to the sub-scanning mosaic control signal MOZWE415g, and the NAND gate 515g controls the write pulses generated by the line memory write pulse generation circuit (not shown). The line memory write pulse generation circuit is a circuit that can vary the output clock rate, such as a rate multiplier, which is generally used for variable magnification control. In this embodiment, detailed explanation will be omitted since it differs from the gist of the invention.

The WR pulse controlled by the above MOZWE signal then becomes H
The switching pulse changes from l to 2 selector to W by the switching signal LMSEL signal, which changes the switching pulse every SYNCI18.
WR pulses are alternately output to EA and WEB. With the above control, the mosaic area signal GHi2 signal 149 is “
Even in the case of "1", when the Mj signal becomes "L", writing to the memory is performed, so it is possible to output a part of the mosaic processed image in the sub-scanning direction without mosaic processing. 35(a) is a diagram showing the distribution of density values for each pixel for recorded colors in which mosaic processing is actually performed.In the mosaic processing of FIG.
Each pixel in a 3×3 pixel block is set as a representative pixel value. In this process, the mosaic process is not performed on the character A1, that is, the pixels in the shaded area, based on the character signal Mj. In other words, when a composite character and a mosaic processing area overlap, priority can be given to the character.

Therefore, even when mosaic processing is performed, an image can be formed so that only the characters can be read. Note that the mosaic area is not limited to a rectangular area, and mosaic processing can also be performed on a non-rectangular area.

(Italics, Taber Processing) Next, the italics processing will be described first with reference to FIGS. 33 and 36.

FIG. 36 shows the inside of the line memory address control section 413g in FIG. 33. This line memory address control unit 413g has write and read counters 409g, 4
10g enable signal is controlled, and movement, italics, etc. are possible by controlling an address counter to determine which part of the main scanning line is to be written into or read from the line memory. First, using Figure 36,
The enable control signal generation circuit will be explained.

Counter 701g has a counter output of 0 at HSYNC.
Then, the image clock 117, which is the clock of the counter 701g, is counted. counter 701
The output Q of g is the equisurface comparator 706g, 708g, 7
It is input in 09g and 710g. Converter 70
The eight input sides of each converter other than 9g are connected to independent latches (not shown) connected to CPUBUS, and any set value and counter 701g
When the output matches the output, a pulse is output. The output of the equilateral comparator 706g is the J-K flip-flop 70.
8g and the comparator 707g is connected to the K input, and from the time the comparator 706g outputs a pulse until the comparator 707g outputs a pulse,
-K flip-flop 708g is configured to output l. This output is used as a write address counter control signal, and the write address counter is activated only in the section where it is 1, and generates an address for the line memory. Similarly, the read address counter control signal controls the read address counter. Here, comparator 7-0 9
The input signal g to A is connected to a selector 703g in order to make the input value to the comparator different depending on whether or not italic processing is performed. Here, when italic processing is not performed, the value set in the latch connected to CPUBUS (not shown) is input to the A input of selector 703g, and the 8 inputs are similarly output by the select signal output from the latch (not shown). It is output from selector 703g. The subsequent operation is performed by the aforementioned comparator 706g,
The operation is similar to that of 707g. Next, when performing italics, the value input to A of selector 703g is also input to selector 702g as a preset value. When the select signals of selectors 702g and 703g select the B input, the output of selector 702g is sent to adder 7.
At 04g, addition is performed with a value set in a latch, also not shown. Here, this value indicates the amount of change for each l line due to the oblique angle, and when the desired angle is θ, it is determined by tan θ. The addition result is input to a flipflop 708g clocked by HSYNC 118, and the value is held during one main scan. Fritub Flotub 7
The output of 05g is connected to the B input of selector 702g and the B input of selector 703g. By repeating this addition operation, the output value from the selector to the comparator 709g changes at a constant rate for each scan, so that the start of the read address counter can be varied from HSYNC at a constant rate. This allows line memory A404g and 8405
The reading from g is shifted with respect to HSYNC and italicization processing becomes possible. In addition, the amount of change mentioned above can be either positive or negative (if positive, HSY
The readout is shifted in the direction away from NC, and if it is negative, it is shifted in the direction closer to HSYNC. In addition, the select signals of selectors 702g and 703g are connected to HSYNC.
By changing it in synchronization with , partial italics can be made.

Regarding enlargement processing methods, generally 0-order, 1-order, SINC
There are methods such as interpolation, but since they are different from the gist of the present invention,
Explanation will be omitted. Taber processing is made possible by changing the magnification in the main scanning direction in synchronization with HSYNC for each scanning line while performing diagonal processing.

In addition, in these processes, the input gradation resolution switching signal is processed while matching the phase with the image signal, and the output image data 114 and the output gradation resolution switching signal LCHG are processed.
142 is output to the edge emphasis circuit.

The conceptual diagram of the italic processing and taper processing explained above is shown in the 35th page.
Figure (b). Shown in (C).

FIG. 37(a) is a block diagram showing details of a mask bitmap memory 573L and its control for restricting an area of arbitrary shape. This memory has a shape as shown in FIG. 37(e), for example, and is used for the aforementioned color conversion, image cropping (non-rectangular trimming), and image filling (
It is used as an ON (process)/OFF (non-process) switching signal for various image processing/editing such as non-rectangular painting).

That is, in FIG. 2, BHil23, DHil22,
FHil21, GHi119, PHil45, AHi
It is supplied via the l48 signal line.

As shown in Figure 38, the mask is configured such that 4 x 4 pixels are I blocks, and 1 bit of the bitmap memory corresponds to the ■ block, so for example, l 6
For an image with a pixel density of p e l / m m, 297
For mmX420mm (A3 size), (29
7X420X16X16)÷16=2Mbit, that is, for example, 1 Mbit dynamic RAM
It can be configured with 2 chips.

The signal 132 input to the FIFO 559L in FIG. 37(a) is a data input line for mask generation as described above. When input as , first, 4×
In order to count the number of "l" in the block 4, buffers 559L, 560L, 561 of 1 bit x 4 lines are used.
L, 562L. FIFO559L~56
2L is connected as shown in the figure (the output of 559L is connected to the input of 56OL, the output of 560L is connected to the input of 561L, and so on, and the output of each FIFO is connected to the 4-bit parallel latch 56).
3L to 565L are latched by vCLK (3rd
(See timing chart in Figure 7(d)).

FIFO output 615L and latch 563L. 56
4L, 565L outputs 616L, 617L, 61
8L are added by adders 566L, 567L, and 568L (signal 602L), and the CPU 22 compares the magnitude with the value set via the I/O port 25L (for example, "l2") in the comparator 569L. . That is, here, it is determined whether the number of 1's in the 4×4 block is greater than a predetermined number.

In FIG. 37(d), the number of "l"s in block N is "14" and the number of 1's in block (N+1) is "4", so the comparator 569L in FIG. 37(a) When the signal 602L is "14", the output 603L is larger than "l2", and when the signal "l" is 4, it is smaller than 112", so it becomes "0". Therefore, due to the latch pulse 605L in FIG. 37(d), The latch 570L latches one 4×4 block once, and the Q output of the latch 570 is latched to the memory 57.
3L DIN input, that is, mask creation data. 580L is an H address counter that generates the address in the main scanning direction of the mask memory, and since one address is assigned to a 4x4 block, the pixel clock VCL
Counting up is performed using a clock obtained by dividing K608 by four using a frequency divider 577L. Similarly, 575L is an address counter that generates an address in the sub-scanning direction of the mask memory, and for the same reason, it is counted up by a clock obtained by dividing the synchronization signal HSYNC of each line by 4 using a frequency divider 574L. ■Address operation is 4×4
It is controlled to be synchronized with the counting (addition) operation of "bi" in the block.

In addition, ■ Output of the lower 2 bits of the address counter, 610
L, 611L is NORed by a NOR gate 572L, and a signal 606 gates a 4-frequency clock 607L.
L and the latch signal 605 should be latched only once per 4×4 block by the AND gate 571L as shown in timing chart No. s7Fg (c).
L is taken. Further, 616L is a data path included in the CPU bus 22 (FIG. 2), 613L is an address bus, and a signal 615L is a write pulse WR from the CPU 22. During the WR (write) operation from the CPU 22 to the memory 573L, the write pulse becomes “Lo” and the signals 578L, 576L, 581
L is opened, the address bus and data path from the CPU 22 are connected to the memory 573L, and predetermined data is randomly written, and WR (write) and RD are sequentially written by the H address counter and ■address counter.
When reading, the control lines of gates 576'L and 582L connected to I/O port 25
6'L, 582L is opened and sequential addresses are supplied to memory 573L.

For example, the output 421 of the binarized output 532 or the CPU
22, if a mask as shown in FIG. 39 is formed, images can be cut out, synthesized, etc. based on the area within the bold line frame.

Further, the bitmap memory shown in FIG. 37(a) can be read by thinning out in both the H direction and the ■ direction, and by interpolating if there is too much data.

That is, as shown in FIG. 40 in detail of the H or V address counter (580L, 575L) in FIG.
For example, during reduction, the B input of the selector 634L should be selected.<MULSEL 636L is set to "0".

635L is a thinning circuit (rate multiplier) for the input clock 614L, and FIG. 41 (timing diagram)
As shown in the figure, for example, CLK is thinned out so that it is output once every three times (setting is based on I/O port 641L)
(637L). On the other hand, for example, "2" is set in 630L, and only when the thinned out output 637L is output, the value set in 630L (for example, "2") is added to the output 638L of the address counter 632L, and the result is loaded into the counter. Therefore, as shown in FIG. 41, the clock advances by "+2" every three clocks in the order of l→2→3→5→6→7→9, etc., resulting in a reduction of 80%. On the other hand, during enlargement, MULSEL becomes "1" and the A input 614L is selected, so the address count is 1→2→3→3→4→5→6→6 as shown in the timing chart of FIG.
→ Proceed as follows.

Figure 40 shows the H address counter 580L of Figure 37, ■
This is the details of the address counter 575L, and since the hardware circuit is the same, the explanation will be limited to FIG. 37 only.

As a result, as shown in Fig. 42, enlargement 2 and reduction l are generated for the non-rectangular area l that is immediately input, so once the non-rectangular area is input, no new input work is required. Furthermore, one mask plane can be used to change the magnification according to various magnifications.

Next, the binarization circuit (532 in FIG. 2) and the high-density binary memory circuit K will be explained. In FIG. 43(a), the binarization circuit 532 outputs the video signal 1 of the output of the character image correction circuit E.
13 with a threshold value 141k to obtain a binary signal, the threshold value is set by the CPU bus 22 in conjunction with the operation unit. In other words, the threshold value is the amplitude value of input data =
256, the memory of the operation unit in FIG. 43(C) is set to M(
When specified as the midpoint), it is "128", and as the scale moves in the ten directions, it changes by -30" from the midpoint, and as it moves in one direction, it changes by "+30". Therefore, "Weak → -2 → -1→M→+1→+2→Strong”, the threshold value is “218→188→158→128→98→68→3
8".

In addition, as shown in FIG. 43(a), CPUBUS
From 22, two threshold values are set, and the selector 35
At k, it is switched by the switching signal 151 and set as a threshold value in the comparator 32k. For the switching signal 151, a different threshold value is set only in a specific area set by the Digitiger 58. For example, the threshold value is relatively low for a monochromatic area of a document, and the threshold value is relatively low for a mixed color area. By setting it high, it is possible to always obtain a uniform binary signal regardless of the color of the original.

The memory circuit K is a memory that stores the signal in which the binarized signal 421 is output to 130 for one page of images, and since this device handles images at A3 and 400 (dpi), approximately 3 It has 2 Mbit.

Details of the memory circuit K will be explained in FIG. 43(b).

The input data D, N130 is gated by the enable signal HE528 when writing to the memory, and is further controlled by the CPU 20 when writing to the ■o port 23k? /R
When the l output is "Hi", it is input to the memory part 37k. At the same time, a synchronizing signal HSYNC118 in the main scanning (horizontal scanning) direction is counted from a synchronizing signal ITOP144 in the vertical direction of the image to generate a vertical address. (2) Count the image transfer clock VCLKll7 from the address counter 35k1HSYNCI18, and count the addresses in the horizontal direction. The H address counter generates an address corresponding to storage of image data.

Memory WP input (write timing signal) at this time 5
A clock having the same phase as the clock VCLKll7 is input as a strobe to the clock 51k, and the input data Di is sequentially stored in the memory part 37k (timing diagram, No. 44).
figure). When reading data from the memory 37k, set the control signal W/R 1 to "Lo" and read the output data D using exactly the same procedure. o1 is read. however,
Both data writing and reading are performed by the HE528, so for example, as shown in Figure 44 (when the HE528 is turned to "Hi" at the input timing of D2 and brought down to "Lo" at the input timing of D■, memory 3
Only the images from D2 to DITl are input to 7k, and data after Do, D, and Dm++ are not written, and data "θ" is written instead. The same goes for reading, and except for the section where HE is "Hi", the data will be read as 〒O.'' HE is output from the area signal generation circuit 17, which will be described later. When a text manuscript like that shown in Figure 45A is placed,
If HE is generated as shown in the figure when writing a binary signal, it is possible to import a binary image into the memory with only the character part as shown in A'. Similarly, unnecessary characters can also be erased and written into the memory.

Furthermore, since the address counters 35k and 36k that read data from the memory 37k have the same configuration as in FIG. 40 and operate at the same timing as in FIG. 41, the binary data read from the memory 37k is It becomes possible to change the magnification. Therefore, when compositing the binary character image shown in Figure 46 (B), which has been previously stored in the main memory as shown in Figure 46, with the image shown in Figure 46 (A), both of them are reduced as shown in CC'). You can combine them by using them, or create a sketch ((
It becomes possible to perform compositing by enlarging only the character portion to be composited without changing the size of part A).

FIG. 47 shows the data stored at the equivalent of 100 dpi as described above.
Image processing blocks A, B, D, F for data from binary bitmap memory L for non-rectangular masks (Fig. 2) and 400 dpi binary memory K for characters and line images (Fig. 2)
, P, G, and the distribution of the binarized video image to the memories L, K. The mask data for limiting the non-rectangular area stored in the memory L is sent, for example, to the color conversion circuit B mentioned above (BHi 123), and for example, as shown in FIG.
) Color conversion is applied only to the inside of the shape. 47th
In the figure, in is an I/O boat connected to the CPU bus 22, 8n-13n is a 2tol selector, and when the switching input S = "9", the A input is selected, and when S = "0", the B input is selected. It is configured to output to Y. Therefore, for example, in order to send the output of the 100 dpi mask memory L to the color conversion circuit B as described above, selector -9n selects A, that is, 28n="1", AND gate 3
In n, it is sufficient to set 21n human power = "l". Similarly, other signals can be arbitrarily controlled by 16n to 31n. The outputs 30n and 31n of the I/O port nl are control signals for storing the output of the binarization circuit 532 (FIG. 2) in the binary memory L or K. When 30n="L", Binary human power 421 goes to l00dpi memory L, 31n=
When it is '1', it will be input to the 400 dpi memory K.

By the way, when AHi148-“l”, the image data sent from the external device is combined, and BHil23=”
l”, color conversion is performed as described above, and DI{il2
When 2="l", monochrome image data is calculated and output from the color correction circuit. Below FHi 121, PHi
145, GHi119, and GHi2 149 are used for character composition, color balance change, texture processing, and mosaic processing, respectively.

In this way, it has two binary memories, 100 dpi memory L and 400 dpi memory K, and stores character information in high-density 4-bit memory.
By inputting area information (including rectangular and non-rectangular areas) into the 100 dpi memory L, it is possible to perform character synthesis in a predetermined area, especially in a non-rectangular area.

Furthermore, by having a plurality of bitmap memories, color mudding processing as shown in FIG. 62 is also possible.

FIG. 49 is a diagram for explaining the area signal generation circuit J. The area refers to, for example, the shaded area in FIG. 49(e), which is the area in the sub-scanning direction A. In the section B, the timing chart AREA of FIG. 49(e) is displayed for each line.
It is distinguished from other areas by signals such as . Each area is designated by digitizer 58 in FIG. Figure 49(a)-(d)
), the generation position, section length, and number of sections of this area signal are C
This shows a configuration that is programmable and can be obtained in large numbers by the PU 20. In this configuration, one area signal is generated by one bit of the RAM that can be accessed by the CPU, and for example, n area signals A R E A O - A
In order to obtain R E A n, an n-bit RAM is used.
(Fig. 49(d) 60j, 61N
. Now, if we obtain the area signals AREAO and AREAn as shown in FIG. 49(b), the RAM address XJ
, x3, and all bits 0 of the remaining addresses are set to "0". On the other hand, the RAM address l, x3 is set to "0".
Set "bit" on X I+ X2+
When the data in the RAM is sequentially read out in synchronization with a constant clock 117 based on the reference clock 117, data "B" is read out at addresses X and X3, for example, as shown in FIG. 49(C). Since the read data is in both the J and K terminals of the J-K flip-flops 62j-0 to 62j-n as shown in FIG. When CLK is input, the output “0” → “B, “l” →
'Os, an interval signal such as AREAO, and therefore an area signal, is generated. Furthermore, if data is set to "0" over all addresses, no area section is generated and no area is set. FIG. 47(d) shows this circuit configuration, and 6
0j and 61j are the aforementioned RAMs. For example, RAM60
While data is being read line by line from j, the CPU 20 (Figure 2) performs memory write operations for setting different areas to the RAMB 61j, and alternately generates sections and writes data from the CPU. Switch memory writing. Therefore, if you specify the shaded area in FIG. 49(f), the RA
MA and RAMB are switched, which is shown in Figure 49(d).
In, (C3.C4,C,) = (o, 1,
O), the counter output counted by VCLK117 is given as an address to RAMA60j through selector 63j (Aa), gate 66j is opened,
The gate 68j is closed and read out from the RAM 60j, and the total bit width, n bits, is transferred to the J-K flipflop 62.
j-0 to 62j-n, and interval signals AREAO to AREAn are generated according to the set values. Writing from the CPU to B is performed during this time using the address bus A-Bus, data path D-Bus, and access signal R/W. Conversely, when generating a section signal based on data set in RAMB61j (c3,
By setting C41 C5)=(L0,1), the same operation can be performed and data can be written from the CPU to the RAM 60j.

58 is a digitizer for specifying an area;
The coordinates of the specified position are input from U20 via the I/O port. For example, in FIG. 50, when two points A and B are specified, the coordinates of A (XI, Y2) and B (X2, Yl) are input.

FIG. 51 shows an interface circuit M for bidirectional communication of image data with an external device connected to this image processing system. 1m is an I/O port connected to the CPtJ bus 22, and each data path AO to CO, A
Signals 5m to 9m for controlling the directions of 1 to CI and D are output. 2m and 3m are pass buffers having an output dry state control signal E, and 3m can change its direction by inputting D. For 2m and 3m, when the E input is "1", a signal is output, and when it is "0", the output is in a high impedance state. lOm is 3 systems of parallel human power A, B
, C by selecting one from selection signals 6m and 7m 3
tol selector. In this circuit, basically 1.
(AO, BO, Co) → (AI, Bl, CI), 2.
There is a bus flow of (AI, Bl, CI)→D. C as shown in the truth table in Figure 52.
It is controlled by PU20. In this system, as shown in Fig. 53, images input from external devices through At, A2, and A3 are rectangular, as shown in Fig. 53 (A),
Both non-rectangular and non-rectangular configurations as shown in (B) are possible. When inputting in a rectangle as shown in Figure 53 (A),
The switching input of the selector 503 in FIG. 2 is set to "l" so that 8 is selected, and the control signal 147 is output from the I/O port 501.

Corresponds to the area to be combined at the same time. Area signal generation circuit J
The rectangular area signal 129 is generated by writing predetermined data from the CPU to predetermined addresses in the RAMs 60j and 61j (FIG. 51), as described above. In the area where the image input 128 from the external device is selected by the selector 507, not only the image data 128 but also the gradation and resolution switching signals 140 are switched at the same time. That is, in an area where an image from an external device is input, a character area signal is generated based on the MIAR 124 (FIG. 2), which is detected from the color separation signals of the image read from the document table. By stopping the gradation and resolution switching signals and forcibly setting them to "Hi," the image area from the inserted external device is outputted smoothly in high gradation.

Further, as explained in FIG. 51, the bitmap mask signal AHf 148 from the binary memory L
When selected by signal 147 at 03, Fig. 53 (B)
Image synthesis from external devices such as

<<Outline of Operation Section>> FIG. 54 shows an overview of the main body operation section 1000 of this embodiment. The key tioo is a copy start key.

Key 1 101 is a reset key that returns all settings on the operation panel to the values when the power was turned on. A key 1102 is a clear stop key, which is used to reset input values such as specifying the number of copies and to cancel a copy operation.

A group of keys 1103 is a numeric keypad and is used to input numerical values such as the number of copies and magnification input. A key 1104 is a document size detection key. A key 1105 is a center movement designation key. Key l106 is an ACS function (black original recognition) key. When ACS is ON, a monochrome black original will be copied in monochrome black. The key 1107 is a remote key, and is a key for passing control to the connected device. Key! 108 is a preheating key.

A liquid crystal screen 1109 displays various information.

The surface of the screen is a transparent touch panel, and when you press it with your finger, the coordinate values are captured.

In the standard state, the magnification, selected paper size, number of copies, and copy density are displayed. While setting various copy modes, the screens necessary for mode settings are displayed one after another. (The copy mode is set using the keys displayed on the screen.) Also displays the self-diagnosis display screen on the guide screen.

A key 1110 is a zoom key, and is an enter key for entering a mode for specifying the magnification of magnification. Key 1111 is a zoom program key, and is an enter key for entering a mode in which the magnification is calculated from the original size and copy size.

A key 1112 is an enlarged continuous shooting key, and is an enter key for entering enlarged continuous shooting mode.

A key 1113 is a key for setting inset composition.

A key 1114 is a key set for character composition. key 1
115 is a key for setting color balance. key 1
Reference numeral 116 is a key for setting a color mode such as single color, negative/positive inversion, etc. Key 1117 is a user's color key, and can set any color mode. key 111
8 is a paint key that allows you to set the paint mode. A key 1119 is a key for setting a color conversion mode.

Key 1120 is a key for setting the contour mode. Key 1121 is used to set the mirror image mode. Keys 1124 and 1123 specify trimming and masking.

It is possible to specify an area using the key 1122 and set the internal processing differently from other parts. key 1129
is the enter key to enter the mode that performs tasks such as loading texture images. Key 1128 is an enter key for entering a mosaic mode such as changing the mosaic size.

Key l127 is an enter key to a mode for adjusting the edge sharpness of the output image. The key 1126 is a key for setting an image repeat mode in which a specified image is repeatedly output.

The key l125 is a key for applying italic/taper processing, etc. to an image. Key 1135 is a key for changing the movement mode. The key 1134 is used to make settings such as continuous page copying and arbitrary division, and the key 1133 is used to make settings related to the projector. The key 1l32 is an enter key to a mode for controlling optional connected equipment. The key 1131 is a recall key that allows you to recall the settings up to three times ago. Key 1130 is an asterisk key.

Keys 1136 to 1139 are mode memory recall keys.
Used when recalling a registered mode memory. Keys 1140-1143 are program memory call keys, which are used to call up registered operating programs.

Black color conversion operation procedure> The procedure of color conversion operation will be explained using FIG. 55.

First, when the color conversion key 1119 on the main body operation section is pressed, the display section l109 is displayed as P050.

Place the original on the digitizer and use the pen to specify the color before conversion. When the input is completed, the screen of PO5 1 appears. Here, use the touch keys 1050 and 1051 to adjust the width of the color before conversion, and after completing the settings, press the touch key 105.
Press 2. The screen changes to P052, and the touch key 1053 and touch key 1054 are used to select whether or not to add shading to the converted color.

If you select shading, the color after conversion will have gradation to match the shading of the color before conversion. That is, the above-mentioned gradation color conversion is performed. On the other hand, if you select no shading, the specified color will be converted to the same density. When you select whether or not to have shading, the screen of PO53 appears, and you can select the type of color after conversion. When 1055 is selected in P053, P
The operator can specify any color to O54. Further, when the color adjustment key is pressed, the process moves to P055, and color adjustment can be performed in 1% increments for each of Y, M, C, and Bk.

Also, if you press 1 056 on PO53, it will move to P056,
Specify the desired color of the document on the digitizer using the point pen. Next, the color shading can be adjusted using PO57.

Also, if 1057 is pressed at PO53, the screen moves to P058, where a predetermined registered color can be selected by number.

Procedure for specifying the trimming area> Below, using Figures 56 and 57,
The same goes for masking, and how to specify areas.
The same procedure applies to partial processing, etc. ) Explain the procedure for specifying an area.

Press the trimming key 1124 on the main body operation unit iooo, and when the display unit 1109 changes to Pool, use the digitizer to input two points on the diagonal of the rectangle, the POO2 screen will appear, and you can continue to input the rectangular area. I can do it. Also, if you specify multiple areas, press the area key 1001 before P001, then press the area key 1002 to display POO.
As shown in 2, each designated area in the X-Y coordinates can be confirmed.

On the other hand, in this embodiment, it is possible to specify a non-rectangular area using the bitmap memory. poo t
While displaying the screen, press the touch key 1003 to move to POO3. Select the shape here. For circles, ellipses, R-rectangles, etc., when the necessary coordinate values are input, the shapes are developed into bitmap memory by calculation. In the case of a free shape, coordinate values are continuously input by tracing the desired shape with a point ben using a digitizer, and the values are processed and recorded on a bitmap.

Each non-rectangular area specification will be explained below.

(Circular Area Designation) When key 1004 is pressed in POO3, the display section 1109 moves to POO4, where a circular area can be specified.

The circular area designation will be explained below using the flowchart of FIG. 58. At SlOl, the center point is input from the digitizer 58 of FIG. 2 (POO4).

Next, the display section II09 moves to POO5, and in step 5103, one point on the circumference of a circle having the radius to be specified is inputted from the digitizer 58. In S105, the CPU 20 calculates the coordinate values of the input coordinate values on the bitmap memory L (100 dpi binary memory) shown in FIG.

Further, in S107, coordinate values of another point on the circumference are calculated.

Next, a bank of the bitmap memory L is selected at Sl09, and the above calculation result is input to the bitmap memory L via the CPU bus 22 at Sill. Figure 37(a)
The data is written from CPU DATA 616L to bitmap memory from 604L via driver 578L. Address control is the same as described above, so it will be omitted. This is repeated for all points on the circumference (S113) to complete the circular area designation.

In addition, instead of inputting information while calculating it on the CPU 20 as described above, template information for two pieces of information input in advance is stored in ROMll, and by specifying these two points with a digitizer, it can be input directly without calculating. It is also possible to write to the bitmap memory L.

(Oval area designation) At P003, press key l005 to move to POO7. The process will be explained below using the flowchart shown in FIG.

First, in S202, the diagonal 2 of the largest rectangular area inscribed in the ellipse
A point is designated by the digitizer 58. Below, for the circumferential part, do 8206 in the same way as in the case of specifying the circular area above.
The data is written to the bitmap memory L in the steps from ~S212.

Next, the straight line portion is written into the memory in steps S214 to S220, and the area designation is completed. As in the case of the circular shape, it is also possible to store the template information in the ROM 21 in advance.

(R rectangular area designation) The method of designation is the same as in the case of an ellipse for memory writing, so the explanation will be omitted.

Incidentally, although the cases of a circle, an ellipse, and an R rectangle have been explained above as examples, it goes without saying that other non-rectangular areas can also be specified based on the same template information.

In POO6, POO8, POIO, P102, use the clear key (1009 to 101) after inputting each shape.
2) If you press , you can partially erase the bitmap memory.

Therefore, even if a mistake is made in the designation, only the two points can be quickly cleared and the two points can be designated again.

It is also possible to specify multiple areas in succession. When multiple areas are specified, priority is given to processing of the area specified later when processing each of the overlapping areas. However, the one specified first may be given priority.

FIG. 57 shows an output example obtained by trimming with an ellipse using the above settings.

Operation procedure for character composition> Figure 60 below. The operation setting procedure regarding character synthesis will be explained using FIG. 61 and FIG. 62. When you press the character synthesis key 1114 on the main body operation section, the liquid crystal display section 1109 displays P.
It will be displayed like O20. A character original 1201 to be synthesized is placed on the original table described above, and when the touch key 120 is pressed, the character original is read, binarized, and the image information is stored in the bit map memory shown in FIG. 2 described above. The specific means of processing has been described above, so duplication will be avoided. At this time, to specify the range of the image to be stored, press the touch key 1021 in P020 to go to the screen of PO21, place the text original 1201 on the digitizer 58, and use the point pen of the digitizer to mark the range with two points. specify.

When the specification is completed, the display section changes to P022, and the user selects whether to read within the specified range (trimming) or to read outside the specified range (masking) using the touch keys 1023 and 1024. Also,
Depending on the text document, it may be difficult to extract the character portion of the text document during the above-mentioned binarization process. In this case, the touch key 1022 in PO20 moves to the screen of PO23, and the slice level of the binarization process can be adjusted using the touch keys 1025 and 1026.

Since the slice level can be adjusted manually in this way, appropriate binarization processing can be performed depending on the color, thickness, etc. of the characters on the document.

Furthermore, press touch key l027, PO24'PO2
By specifying an area with 5', it is possible to partially change the slice level with PO26'.

In this way, by specifying an area and changing the slice level only for that part, even if there is, for example, yellow text in a part of the black text document, separate appropriate slice levels can be set for each of the black and yellow text. By doing so, it is possible to perform good binarization processing on the entire character.

When the reading of the character original is completed, the display section 1109 becomes as shown in FIG. 61 PO24.

To select color blank processing, touch key 10 in P024
Press 27 to move to the PO25 screen, and select the color of the characters to be combined from the displayed colors.

It is also possible to partially change the color of the text. In that case, press the touch key 1029 to move to the PO 27 screen and proceed to the edit. After specifying the rear color, select the color of the characters on the screen of P030. Furthermore, it is also possible to add color border processing to the edges of the characters to be synthesized, in which case P03
Move to the screen of P032 with touch key 1031 in 0,
Select a color for the border. At this time, you can adjust the color by
This is the same as in the case of color conversion above. Furthermore, touch key l03
Press 3 to adjust the border width on the screen of P041.

Next, a case in which color number processing is added to a rectangular area containing characters to be synthesized (hereinafter referred to as square processing) will be described. PO2
Press the touch key 1028 in 4 to move to the screen P034 and specify the area. The processing will be performed within the range specified here. When the area designation is completed, the character color is selected in P037, the touch key 1032 is pressed, the screen moves to P039, and the color of the square is selected.

In the above color selection, for example, on the screen P025, by pressing the color adjustment key of the touch key l030, the screen moves to the screen PO26, where it is possible to change the tone of the selected color.

Character synthesis is performed according to the procedure described above. FIG. 62 shows an example of the output when the settings are actually made.

In addition to specifying a rectangular area, the area specification can also specify a non-rectangular area as described above.

<<Texture processing setting procedure>> Next, texture processing will be explained using FIG. 63.

Texture key 1129 on main body operation section 1 0 {10
When you press , the display unit 1109 displays something like PO60.

When applying texture processing, touch key 1060 is pressed to highlight this key. When reading an image pattern for texture processing into the above-mentioned texture image memory (Fig. 32, 113g), press the touch key 106.
Press 1. At this time, if the pattern is already in the image memory, as in PO62, if it is not displayed, P
O6 1 will be displayed. By placing the document with the image to be read on the document table and pressing the touch key l062, the image data is stored in the texture image memory. At this time, in order to read any part of the manuscript,
The user presses the touch key 1063 and makes a designation using the digitizer 58 on the PO63 screen. The specified reading range is 16rnm.
This can be done by inputting with a pen at one point at the center of x16mm.

Reading of a texture pattern by specifying one point as described above can be performed as follows.

Without reading the pattern, press the touch key 1060, set the texture processing, and press the copy start key 1.
If an attempt is made to escape from the PO64 screen using 100, other mode keys (1110 to 1143), touch key 1064, etc., the display section issues a warning as shown at P065.

Further, the length and width of this range can be specified by the operator.

Mosaic Process Setting Procedure> FIG. 64 is a diagram illustrating a mosaic process setting procedure.

When the mosaic key 1128 on the main body operation section is pressed, the display section displays something like PIOO. To apply mosaic processing to a document, touch key 1400 is pressed to highlight this key.

Furthermore, when performing mosaic processing, the mosaic size is changed by pressing the touch key 1401 on the PIOI screen. Change the mosaic size in the vertical (Y) direction. Towards... Horizontal (X)
It is also possible to set the direction independently.

〈About the hard mode operation procedure〉 FIG. 65 is a diagram illustrating the operation procedure in the screen mode.

Press the old key 1130 on the main unit's operation section i ooo to enter the screen mode, and the display section l! 09 is displayed as PI 10. The touch key 1500 enters a color registration mode for registering color information used in paint user colors, color conversion, color text, etc. A touch key 1501 turns on/off a function for correcting image defects caused by the printer.

Touch key 1502 is a key for entering mode memory registration mode. The touch key 1503 enters a mode for specifying the manual feed size. Touch key 1504 enters program memory registration mode. The touch key 1505 is
This key is used to enter the mode for setting default color balance values.

(About color registration mode) When PIIO is displayed, press touch key l500 to enter color registration mode. The display section looks like Pill, and the type of color to be registered is selected. To change the palette color, press touch key l506, select the color you want to change on the PI 16 screen, and select yellow, magenta, cyan, etc. on the PI 17 screen. The value of each black component can be adjusted in 1% increments.

Also, if you want to register any color on the document, touch key 1.
Press 507, select the registration number on the PllB screen,
Specify using the digitizer 58, set the original on the original table when the screen of Pl20 is displayed, press the touch key 1510,
Register.

(Regarding manual feed size specification) As shown in Pl12, manual feed size can be specified as either a regular size or a non-standard size.

For irregular shapes, both the horizontal (X) direction and the vertical (Y) direction can be specified in units of 1 mm.

(Regarding mode memory registration) The set mode can be registered in the mode memory as shown in Pl13.

(Regarding program memory registration) As shown in P114, a series of programs for specifying an area and performing predetermined processing can be registered.

(Regarding color balance registration) As shown in PI15, color balance can be registered for each of Y, M, C, and Bk.

<Regarding program memory operation procedure> The registration operation in the program memory and its usage procedure will be explained below with reference to FIGS. 66 and 67.

Program memory is a memory function that stores operating procedures related to settings and reproduces them. It is possible to connect the necessary modes and make settings that go beyond unnecessary screens. As an example, let's program memory the procedure for changing the magnification of a certain area of a document and repeating the image.

Press the appetizer mode key 1130 on the main body operation section to display the screen P080 on the liquid crystal display section, and press the program memory key of touch key 1200. In this embodiment, four programs can be registered. Select the number to register on the PO81 screen. After this, move to program registration mode. In the program registration mode, for example, the screen shown in FIG. 68 1300 in the normal mode becomes as shown in 1301. The skip key of the touch keys 1302 is designated when the user wants to skip the current screen. The clear key of the touch keys 1303 is used when canceling the current registration in the middle of program memory registration and redoing the registration from the beginning.

The end key of the touch keys 1304 exits the program memory registration mode and registers in the memory of the first determined number.

First, press the trimming key 1124 in the main unit operation section,
Specify the area with the digitizer. The display unit is displaying P084, but if no further area settings are to be made at this point, touch key 1202 is pressed to designate skipping this screen. (The screen becomes P085) Next, when the zoom key 1110 on the main body operation section is pressed, the display section becomes PO86. Here, the magnification is set and when the touch key 1203 is pressed, the display changes to P087. Finally, press the image repeat key 1126 on the main body operation section to make settings regarding image repeat on the screen P088, and then register to number 1 in the program memory using the touch key 1204.

To call up the program registered in the above procedure, press the program memory 1 call key 1140 on the main body operation section. The display section displays PO91 and waits for area input. If you input the area using a digitizer,
The display section displays PO92 and then moves on to the next PO93. After setting the magnification here, if the touch key 1210 is pressed, the display section changes to PO94 and image repeat can be set. When touch key 1211 is pressed, the mode in which the program memory is used (referred to as trace mode) is exited.

Note that from the time the program memory is called until the program is terminated,
Each key (1110 to 1143) in the edit mode is disabled, and operations can be performed according to the registered program.

FIG. 69 shows the program memory registration algorithm. Screen turning in S301 means changing the display on the display unit using keys or touch keys.

When the touch key 1302 is pressed to designate skipping the currently displayed screen (S303), that information is set on the recording table when the next screen is turned over (5305). Then, in S307, a new screen number is set in the recording table. When the clear key is pressed, the entire record table is cleared (S309, S31])
, otherwise, the process returns to S301 and moves to the next new screen. FIG. 71 shows the format of the recording table. FIG. 70 shows an algorithm representing the operation after calling the program memory.

8 4. If the screen turns over at 01, it is determined whether the new screen is a standard screen (S403). If it is a standard screen, the process moves to S411 and sets the next screen number from the recording table, and if it is not a standard image, the new screen number is compared with the scheduled screen number in the recording table (S4
05), if they are equal, the process moves to S409, and if there is a skip flag, S411 is skipped and the process returns to S401. If they are not equal, a recovery process is performed (S407) and the screen is turned over.

As explained above, in this embodiment, a specifying means (FIG. 2, 58) specifies a specific area for input image data and generates an area signal, and image processing and editing is performed for the specific area. control means (FIG. 2 F, G) for performing printing; a first control means (502 in FIG. 2) that changes the conditions; and a second control means (502 in FIG. 2) that controls the image area discrimination signal based on the area discrimination signal that bounds the designated specific area. ), the above objective is achieved.

That is, by providing means for controlling the image area discrimination signal based on the area discrimination signal that bounds the specified specific area, it is possible to achieve both image area separation and image processing and editing for the specific area. .

In addition, in this example, 200 dpi printing and 400 dpi printing
Although the switching signal for dpi printing is changed in accordance with the image editing process, the present invention is not limited to control of the 200/400 dpi switching signal.

That is, it can be applied to any case where printing conditions (for example, dot diameter, density of one dot, etc.) are varied based on the area discrimination signal.

As explained above, according to this embodiment, by controlling the image area discrimination signal based on the area discrimination signal that bounds the designated specific area, it is possible to achieve both image area separation technology and advanced processing and editing. This has the effect of being able to obtain high-quality image output that has undergone advanced processing and editing.

〔Effect of the invention〕

According to the present invention, image processing and editing processing can be performed with high accuracy. Fig. 1 is an overall diagram of an image processing apparatus according to an embodiment of the present invention, and Fig. 2 is a circuit diagram of an image processing according to an embodiment of the present invention. Fig. 3 is a diagram showing the color reading sensor and drive pulses, Fig. 4 is a circuit diagram for generating ODRV118a and EDRVl19a, Fig. 5 is a diagram explaining black correction operation, Fig. 6 is a circuit diagram for shading correction, Figure 7 is a color conversion block diagram, Figure 8 is a color detection block diagram, Figure 9 is a block diagram of a color conversion circuit, Figure 10 is a diagram showing a specific example of color conversion, and Figure 11 explains logarithmic conversion. Figure 12 is a circuit diagram of the color correction circuit, Figure 13 is a diagram showing unnecessary transmission areas of the filter, and Figure 14 is a diagram showing the unnecessary transmission area of the filter.
The figure shows unnecessary absorption components of the filter, Figure 15 is a circuit diagram of a character image area separation circuit, Figure 16 is a diagram explaining the concept of contour regeneration, and Figure 17 explains the concept of contour regeneration. Figure 18 is a contour regeneration circuit diagram, Figure 19 is a contour regeneration circuit diagram, Figure 20 is a timing chart of ENI and EN2,
Figure 1 is a block diagram of the character image correction section, Figure 22 is an explanatory diagram of addition/subtraction processing, Figure 23 is a switching signal generation circuit diagram, Figure 24 is a circuit diagram of color residual removal processing, and Figure 25 is color residual removal processing. , Figure 26 is a diagram showing edge emphasis, Figure 27 is a diagram showing smoothing, Figure 28 is a diagram explaining processing and modification processing using binary signals, Figure 29 is a diagram explaining text, Figure 30 is a block diagram of the image editing circuit, Figure 31 is a diagram showing texture processing, Figure 32 is a circuit diagram of texture processing, Figure 33 is a diagram of mosaic, scaling, and tapering processing. A circuit diagram, FIG. 34 is a circuit diagram of mosaic processing, FIG. 35 is a diagram explaining mosaic processing, etc., FIG. 36 is a circuit diagram of the line memory address control section, FIG. 37 is an explanatory diagram of the mask bit memory, Fig. 38 is a diagram showing addresses, Fig. 39 is a diagram showing a specific example of a mask, Fig. 40 is a circuit diagram of an address counter, Fig. 41 is a timing chart for enlargement and reduction, and Fig. 42 is a diagram for enlargement and reduction. FIG. 43 is an explanatory diagram of a binarization circuit, and FIG. 44 is a diagram showing a specific example. Fig. 45 is a diagram showing a specific example of bitmap memory writing, Fig. 46 is a diagram showing a specific example of character and image composition, Fig. 47 is a circuit diagram of distribution switching, and Fig. 48 is a diagram of a nonlinear mask. A diagram showing a specific example, Figure 49 is a circuit diagram of the area signal generation circuit, Figure 50 is a diagram showing area specification by a digitizer, Figure 51 is an interface circuit diagram with external equipment, and Figure 52 is a truth value of the selector. Table, Figure 53 is a diagram showing examples of rectangular areas and non-rectangular areas, Figure 54
55 is a diagram explaining the procedure of color conversion operation, FIG. 56 is a diagram explaining the procedure of specifying the trimming area, FIG. 57 is a diagram explaining the procedure of specifying the trimming area, Figure 58 is a diagram showing the algorithm for specifying a circular area.
Figure 9 is a diagram showing the algorithm for specifying areas of ellipses and R rectangles, Figure 60 is an explanatory diagram of the operating procedure for character composition, Figure 61 is an explanatory diagram of the operating procedure for character composition, and Figure 62 is an illustration of the operation procedure for character composition. FIG. 63 is a diagram explaining the procedure of texture processing. FIG. 64 is a diagram explaining the procedure of mosaic processing. FIG. 65 is a diagram explaining the procedure of blue mode operation.
Figure 67 is a diagram explaining the program memory operation procedure. Figure 68 is a diagram explaining the program memory operation procedure. Figure 69 is a diagram explaining the program memory registration algorithm. Figure 70 is a diagram showing the algorithm of the operation after calling the program memory; Figure 71 is a diagram showing the format of the recording table;
FIG. 2 is a diagram illustrating image processing and editing.

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Claims (1)

[Scope of Claims] Specifying means for specifying a specific area in input image data and generating an area signal; Control means for processing and editing the image for the specific area; Character area of the input image. image area discriminating means for discriminating areas other than character areas; first control means for varying printing conditions based on the output signal of the image area discriminating means; based on the area discriminating signal for demarcating the designated specific area; and second control means for controlling the image area discrimination signal.