JPH02295354A - Picture processor - Google Patents

Abstract

PURPOSE:To satisfactorily discriminate a character area from a picture, in which a character is mixed, by setting the average value of a first block picture element area as a threshold value and setting a result, for which the average value of a second block picture element area is binarized, as the binarized output of a notice picture element. CONSTITUTION:An emphasis circuit is provided to calculate a luminance signal Y from R, G and B signals, to which color separation is executed, and to execute emphasis processing to the luminance signal Y. the average value around the notice picture element is calculated by using the two matrixes of different sizes for binarization and offset quantity is provided to the average value in the matrix of the larger size. Accordingly, the picture can be separated to the part of paint-out density of a half tone picture and the other part and a deciding reference can be obtained for image area separation. Thus, the character area and half tone area can be satisfactorily identified from the picture in which the character is mixed.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an image processing device for identifying a character area from an image containing mixed characters.

[Conventional technology]

Conventionally, many image area separation methods have been proposed that use the spatial frequency characteristics and autocorrelation characteristics of an image to determine tint points and continuous tone regions.

[Problem to be solved by the invention]

However, most of the above-mentioned conventional techniques use Fourier transform or an autocorrelation function in order to utilize the frequency characteristics of an image, and the calculations are complicated, so there is a limit to the processing speed. In addition, the input halftone image is also the image input system's S/
There were many erroneous judgments because the image did not necessarily have an ideal halftone dot image or smoothly change continuously due to N, blur, etc. On the other hand, when determining a continuous tone area, it is possible to determine a continuous tone image by binarizing input pixels and identifying continuity in the binarized intermediate image. At this time, when converting into binarization, it is desirable that the continuous tone part be smooth data, but actual image data is affected by the S/N of the image input system and processing system, and the binarized signal changes from l→
The signal has many changing points such as 0, 0→l, and is difficult to determine as a continuous tone region.

SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide an image processing device that can satisfactorily distinguish character areas and halftone areas from an image containing mixed characters.

[Means and operations for solving the problems] In order to solve the above problems, the image processing device of the present invention includes means for calculating the average value of a first block pixel region centered on the pixel of interest; means for calculating an average value of a second block pixel area, using the average value of the first block pixel area as a threshold;
It is characterized by comprising a binarization means for converting the digitized result into a binarized output of the pixel of interest.

In the above configuration, the binarization means binarizes the average value of the second block pixel area using the average value of the first block pixel area as a threshold, and uses the result as a binarized output of the pixel of interest. .

(Margin below) 〔Example〕 Hereinafter, the present invention will be explained in detail with reference to the drawings.

FIG. 1 shows an example of a schematic internal configuration of a digital color image processing system according to the present invention. As shown in the figure, this system has a digital color image reading device (hereinafter referred to as color league) 1 at the top and a digital color image printing device (hereinafter referred to as color printer) 2 at the bottom. This color reader l has color separation means and C
A photoelectric conversion element such as a CD reads the color image information of the original for each color and converts it into an electrical digital image signal. Further, the color printer 2 is an electrophotographic laser beam color printer that reproduces a color image in each color according to the digital image signal, and records the image by transferring it to recording paper multiple times in the form of digital dots.

First, an overview of the color reader I will be explained.

3 is a document, 4 is a platen glass on which the document is placed, and 5 is a robot for condensing the reflected light image from the document exposed and scanned by a halogen exposure lamp 1O, and transmitting the image to a 1-magnification full-power color sensor 6. It is a door array lens, 5, 6,
7. 10 as a document scanning unit 11 performs exposure scanning in the direction of arrow AI.

The color separation image signals read every line without exposure scanning are amplified to a predetermined voltage by the sensor output signal amplification circuit 7, and then inputted to a video processing unit to be described later via a signal line 501, where they are processed. . Details will be described later. 501 is a coaxial cable for ensuring faithful transmission of signals. A signal 502 is a signal line that supplies drive pulses for the same-magnification full-strength color sensor 6, and all necessary drive pulses are generated within the video processing unit l2. 8
．． Reference numeral 9 denotes a white plate and a black plate for white level correction and black level correction of the image signal, which will be described later.By irradiating with the halogen exposure lamp 10, a signal level of a predetermined density can be obtained, and the white plate of the video signal can be obtained. Level correction゜,
Used for black level correction. 13 is a control unit having a microcomputer, which is connected to the bus 50
8 to display on the operation panel 20, key manual control and control the video processing unit 12, position sensors St and S2 to detect the position of the document scanning unit 11 via signal lines 509 and 510, and signal line 503 to detect the position of the scanning unit 11. Stepping motor drive circuit control that pulse-drives the stepping motor l4 to move the halogen exposure lamp IO via the signal line 504, ON/OFF control of the halogen exposure lamp IO by the exposure lamp driver via the signal line 504, light amount control, and control via the signal line 505. It controls all parts of the color reader part 1, including the digitizer 16, internal keys, and display control. The color image signal read by the exposure scanning unit 11 described above during exposure scanning of the original is sent to the video processing unit 1 via the amplifier circuit 7 and the signal line 501.
2, undergoes various processes described below within this unit 12, and is sent to the printer part 2 via the interface circuit 56.

Next, an outline of the color printer 2 will be explained. 711 is a scanner, a laser output unit that converts the image signal from the color reader l into an optical signal, and a polyhedron (for example, an octahedron).
polygon mirror 712, a motor (not shown) for rotating this mirror 712, and an f/θ lens (imaging lens)
713 etc. 714 is a reflecting mirror that changes the optical path of the laser beam, and 715 is a photosensitive drum. The laser beam emitted from the laser output section is reflected by a polygon mirror 712, passes through a lens 713 and a mirror 714, and linearly scans (raster scan) the surface of a photosensitive drum 715, forming a latent image corresponding to the original image. do.

In addition, 711 is a primary charger, 718 is a full exposure lamp,
723 is a cleaner section for collecting residual toner that has not been transferred; 724 is a pre-transfer charger; these members are disposed around the photosensitive drum 715.

726 is a developer unit that develops the electrostatic latent image formed on the surface of the photosensitive drum 715 by laser exposure; 731Y, 731M, 731C, and 731Bk are developing sleeves that directly develop the photosensitive drum 715;
0Y, 730M, 730C, 730Bk are toner hoverers for holding spare toner, 732 is a screw for transporting developer, and these sleeves 731Y~
731Bk,} The developing device unit 726 is constituted by the inner hoppers 730Y to 7308k and the screw 732, and these members are arranged around the rotation axis P of the developing device unit. For example, when forming a yellow toner image, yellow toner development is performed at the position shown in this figure, and when forming a magenta toner image, the developing device unit 72
6 is rotated around the axis P in the figure, and the developing sleeve 731M in the magenta developing device is disposed at a position in contact with the photoreceptor 715. Cyan and black development work in the same way.

Further, 716 is a transfer drum that transfers the toner image formed on the photosensitive drum 715 onto paper, 7l9 is an actuator plate for detecting the moving position of the transfer drum 716, and 720 is in close proximity to this actuator plate 719. 725 is a transfer drum cleaner, 727 is a paper press roller, 728 is a static eliminator, and 729 is a transfer charger. These members 71
9, 720, 725, 727, 729 are transfer rollers 7
It is arranged around 16.

On the other hand, 735 and 736 are paper feed cassettes that store paper (paper sheets), and 737 and 738 are cassettes 735 and 738, respectively.
Paper feed rollers that feed paper from 736, 739, 74
0 and 741 are timing rollers that take the timing of paper feeding and conveyance, and the paper fed and conveyed via these is guided to a paper guide 749 and wrapped around a transfer drum 716 while its leading edge is carried by a gripper to be described later. , transition to the image formation process.

Further, 550 is a drum rotation motor, and the photosensitive drum 7
15 and a transfer drum 716 are rotated in synchronization. 750 is a peeling claw that removes the paper from the transfer drum 716 after the image forming process is completed, 742 is a conveyor belt that conveys the removed paper, and 743 is a conveyor belt that is conveyed by the conveyor belt 742. The image fixing unit 743 is an image fixing unit that fixes the paper that has been received.

The image processing circuit according to the present invention will be described in detail with reference to FIG. 2 and subsequent figures. This circuit exposes a full-color original with an illumination source such as a halogen lamp or fluorescent lamp (not shown), captures a reflected color image with a color image sensor such as a CCD, and sends the obtained analog image signal to an A/D converter. A color image copying device that processes and processes the digitized full-color image signal and outputs it to a thermal transfer color printer, inkjet color printer, laser beam color printer, etc. (not shown) to obtain a color image, or a color image copying device that obtains a color image by processing the digitized full-color image signal Applicable to color image output devices, etc. that input color image signals from computers, other color image reading devices, color image transmitting devices, etc., perform processing such as composition, and output them to the color printer mentioned above. It is.

The document is first irradiated by an exposure lamp (not shown), and the reflected light is separated into colors for each image and read by a color reading sensor 500a, and amplified to a predetermined level by an amplifier circuit 501a. 533a is a CCD driver that supplies pulse signals for driving the color reading sensor, and the necessary pulse source is generated by a system control pulse generator 534a.

FIG. 3 shows the color reading sensor and drive pulses. Figure 3(a) shows the color reading sensor used in this example, which reads by dividing the main scanning direction into five (63
．． Assuming that 5 μm is one pixel (4 dots/inch (hereinafter referred to as dpi)), there are 1024 pixels, that is, one pixel is divided into three by G, B, and R in the main scanning direction as shown in the figure, so a total of 1024 x 3 = 3072 effective pixels. It has the number of pixels. On the other hand, each of the chips 58 to 62 is formed on the same ceramic substrate, and the chips 58 to 62 are formed on the same ceramic substrate. 3. 5th (58a
, 60a, 62a) are on the same line LA, 2,
The fourth is LA for 4 lines (63.5 μm x 4 = 25
4 μm) on the line LB, and scans in the direction of the arrow AL when reading the document.

1, 3 out of each 5 CCDs. The fifth one is for the drive pulse group ODRV118a, and the second and fourth are for the EDRV119a.
are driven independently and synchronously.

OOIA, 002A, OR included in ODRVI18a
EOIA, EO2A included in S and EDRV119a,
ERS are a charge transfer clock and a charge reset panorez in each sensor, respectively; l, 3. 5th and 2.
Due to mutual interference with the fourth and noise limitations, they are generated in perfect synchronization so that there is no jitter between them. Therefore, these pulses are generated by one reference oscillation source OSC558a (second
Figure).

Figure 4(a) shows ODRV118a and EDRVl19a.
FIG. 4(b) is a timing chart of the circuit block that generates the pulse generator 534a of FIG. 2, which is included in the system control pulse generator 534a of FIG. Clock K obtained by dividing the original clock CLKO generated from a single OSC558a
0135a is a clock that generates reference signals SYNC2 and SYNC3 that determine the generation timing of ODRV and EDRV (7), and SYNC2 and SYNC3 are the settings of the resettable counters 64a and 65a that are set by the signal line 22 connected to the CPU path. The output timing is determined according to the value, and SYNC2 and SYNC3 are connected to the frequency divider 66a.
, 67a and drive pulse generators 68a, 69a
Initialize. In other words, the HS input to this block
Based on YNCI18, all with one oscillation source OSC55
Notes and ODR generated by the CLKO output from 8a and the divided clocks that are all generated synchronously.
The respective pulse groups of Vl18a and EDRV119a are obtained as synchronous signals with no jitter, and signal disturbances due to interference between sensors can be prevented.

Here, the sensor-driven panoresque ODRVI18a obtained in synchronization with each other are l, 3. Fifth sensor 58a
, 60a, 62a, the EDRV 119a is supplied to the second and fourth sensors 59a, 61a, and each sensor 58a,
59a, 60a. Video signals V1-V5 are independently output from 61a and 62a in synchronization with the drive pulse, and an independent amplifier circuit 501 is provided for each channel shown in FIG.
-1 to 501-5 are amplified to a predetermined voltage value, and V1, V3, and V5 are transmitted through the coaxial cable 101a at the timing of OOS 129a in FIG. input to the processing circuit.

The color image signal obtained by dividing the original input into the video image processing circuit into five parts is processed by the sample hold circuit S/H502a in three colors of G (green), B (blue), and R (red). separated into

Therefore, after S/H, 3×5=15 signals are processed.

The analog color image signals sampled and held for each color R, G, and B by the S/H circuit 502a are as follows:
The next stage A/D conversion circuit 503a digitizes each channel from 1 to 5, and each channel from 1 to 5 is independently connected in parallel.
Output to the next stage.

Now, in this embodiment, as described above, 4 lines (63.
5 μm x 4 = 254 μm) in the sub-scanning direction,
In addition, since the document is read using five staggered sensors divided into five areas in the main scanning direction, the reading positions of channels 2.4, which is being scanned in advance, and the remaining channels 1 and 3.5 are shifted. Therefore, in order to connect this correctly, a shift correction circuit 504a equipped with memory for multiple lines is used to
We are correcting that discrepancy.

Next, using FIG. 5(a), the black correction/white correction circuit 506
The black correction operation in a will be explained. As shown in FIG. 5(b), when the amount of light input to the sensor is small, the black level outputs of channels 1 to 5 vary greatly between chips and between pixels. If this is output as is and an image is output, streaks and unevenness will occur in the data portion of the image. Therefore, it is necessary to correct the output variation in the black portion, and this correction is performed using a circuit as shown in FIG. 5(a). Prior to the original reading operation, the original scanning unit is moved to the position of a black plate having uniform density that is placed in a non-image area at the tip of the original table, the halogen is turned on, and a black level image signal is input to this circuit.

Regarding the blue signal BIN, in order to store one line of this image data in the black level RAM78a,
Select A with the selector 82a (■), close the gate 80a (■), and open 81a. That is, the data line is 151a
-+152a-+153a, while RAM78
Address 155a of a is initialized with m and VCL
Output 1 5 of address counter 84a that counts K
4a is input to the selector 83a, and the black level signal for l lines is R A M 7 8
(hereinafter referred to as black reference value import mode).

When reading an image, RAM78a is in data readout mode, and data lines 153a + 157a
Each line and every l pixel are read out and inputted to the B input of the subtractor 79a through the path . That is, at this time gate 81
a is closed (■), and 80a is open (■). Moreover, the selector 86a becomes an A output. Therefore, the black correction circuit output 156
a is for black level data DK (i), for example, in the case of a blue signal B IN (i) −DK (i)”B
OLIT (i) (referred to as black correction mode). Similarly, Green GINI Red RIN is also 77
Similar control is performed by aG and 77aR.

In addition, the control lines of each selector gate for this control
, ■, ■, ■ are performed under CPU control by latch 85a assigned as I/O of CPU 22 (FIG. 2). Note that the selectors 82a, 83a, 86a are
RAM 7 by the CPU 22 by selecting
8a becomes accessible.

Next, white level correction (shading correction) in the black correction/white correction circuit 506a will be explained with reference to FIG. White level correction corrects variations in sensitivity of the illumination system, optical system, and sensor based on white data obtained when the document scanning unit is moved to the position of a uniform white plate and irradiated. The basic circuit configuration is shown in FIG. 6(a). The basic circuit configuration is the fifth
Although it is the same as in FIG.
The only difference is that ``is used'', so the explanation of the same parts will be omitted.

COD (500a) for reading originals during color correction
) is at the reading position (home position) of a uniform white plate, that is, before a copying operation or a reading operation, an exposure lamp (not shown) is turned on and image data of a uniform white level is stored in the correction RAM 78'a for one line. Store. For example, if it has an A4 longitudinal width in the main scanning direction, it is 16peI! /mm = 16X297mm = 475
2 pixels, that is, at least the RAM capacity is 4752 bytes, and as shown in FIG.
Data for the white plate for each pixel is stored in a as shown in FIG. 6(c).

On the other hand, for Wi, the read value Di of the normal image of the i-th pixel is corrected data Do = D i xF
It should be FH/Wi. Therefore, from CPU22,
Gates 80'a and 81'a are opened for latches 85'a■', ■', ■', and ■', and selector 8
2' a, 83' a, 86' a so that B is selected, and R A M 7 8' a to CP.
Allow U access.

Next, in the procedure shown in FIG. 6(d), the CPU 22 sets FFH/Wo for the first pixel Wo, FF/W for w,
. . . are operated sequentially to replace the data. When the blue component of the color component image is completed (Fig. 6(d) Step
B) Similarly, green component (Step G), red component (
Step R) is performed sequentially, and thereafter, for the input original image data Di, D o = D i X F F H
The gate 80'a is opened so that /W i is output (■
'), 81' a is closed (■'), selector 83' a,
A is selected for 86'a, and the coefficient data FFH/Wi read from the RAM 78'a is connected to the signal line 153a→
157a and input from one side.
The product is multiplied by 1a and output.

? As mentioned above, the black level and white level are corrected based on various factors such as the black level sensitivity of the image input system, the dark current variation of the CCD, the sensitivity variation between each sensor, the optical system light amount variation, and the white level sensitivity. Image data B uniformly corrected for each color, both white and black, in the main scanning direction. U
TlOl, GOUTl02, ROU■103 are obtained. The white and black level-corrected color separation image data obtained here are processed by detecting pixels on the image having a specific color density or a specific color ratio according to instructions from an operation unit (not shown). The data is sent to a color conversion circuit B which converts the data into another color density or color ratio specified by the unit.

<Color Conversion> FIG. 7 is a block diagram of color conversion (gradation color conversion and density color conversion). The circuit in FIG. 7 uses an 8-bit color separation signal R IN
．． A color detection section 5b that determines an arbitrary color set in the register 6b by the CPU 20 for G INI B IN (lb to 3b), an area signal Ar4b for performing color detection and color conversion for a plurality of locations, and ? A line memory 10b that performs processing to spread a signal indicating "a specific color" (hereinafter referred to as a hit signal) outputted by the color detection section in the main scanning and sub-scanning directions (in the example of FIG. 7, only the sub-scanning direction).
-1lb, OR gate 12b, expanded hit signal 3
4b and non-rectangular signals (including rectangular) Color conversion enable signal 33b generated from BHi 27b, enable signal 33b and input color separation data (R IN+ G IN+
B IN It) to 3b), line memories 13b to 16b for synchronizing area signal Ar4, delay circuits 17b to 20b1 enable signal 33b1 synchronized color separation data (RIN.GIN,B
IN 2lb~23b), area signal Ar' 24b
and a color conversion unit 2 that performs color conversion based on the color data after color conversion set in the register 26b by the CPU 20.
5b1 Color separation data subjected to color conversion processing (ROUT, GO
U1, BoU■28b-30b), ROUT + G
Hit signal H output in synchronization with OUT + BOUT. Consists of lJ■3lb.

Next, we will outline the algorithms for gradation color determination and gradation color conversion. Here, gradation color judgment and gradation color conversion mean color judgment and conversion of the same hue in order to save the density value and perform color conversion for colors of the same hue when performing color judgment and color conversion. It is to perform a transformation.

It is known that for the same color (certain hue), for example, the ratios of the red signal R1, the green signal G, and the blue signal B are equal.

Therefore, data M of one of the colors to be converted (maximum value color, hereinafter referred to as principal color) is selected, and the ratio between it and the data of the other two colors is determined. For example, and the input data R,
, G. , Bi, M, X γ1 ≦
Ri≦M, X γ2 However, α1, βl+ 71
≦1 α2·β2, γ2 ≧1 is determined to be a pixel to be color-converted.

Furthermore, the data after color conversion (R21 G21 B2) is also
Data M of the main color (in this case, the maximum value color) within that data
2 and the data of the other two colors.

For example, when G2 is the main color, M2 = 62, and for the main color M of input data, if the data is a color conversion pixel, if it is not a color conversion pixel, then (R+, G+, B+) is output.

As a result, all parts of the same hue with gradation are detected,
It becomes possible to output color conversion data according to gradation.

FIG. 8 is a block diagram showing an example of a color determination circuit. This part is a part that detects pixels to be color-converted.

In this figure, 50b is R, N bl, G, N b2
, B, N. b3 is a smoothing unit that smooths the input data, and 5lb is a selector 52bR, 52b0, and 52bB that selects one of the outputs (primary color) of the smoothing unit, and 52b0 and 52bB are the output of selector 5lb and a fixed value R. , a selector for selecting one of Go, Bo, 54bR, 54bo, 54b
8 is OR gate, Q3b, 64b R, 64b o, 6
4b8 are selectors 5lb, 52bR, 52bo, 52b8 based on area signals ArlO, Ar20, respectively.
Selector for setting the select signal to 56bR
, 56bG. 56bB and 57bR, 57bo, 57
b8 is a multiplier that calculates the upper and lower limits of each.

Further, each upper limit ratio register 58b R, 58b , 58b 8, lower limit ratio register 59b R, 59b o. , 59b 8 can each set data for color detection for a plurality of areas based on the area signal A'30.

Here, ArlO, Ar20, and Ar30 are signals created based on Ar4b in Fig. 7, and each has the required number of stages of D.
Contains F/F. Also, 6lb is an AND gate, 62
b is an OR gate, and 67b is a - register.

Next, we will explain the actual movement. R,N bl,G,N
The selector 5lb selects one of the data R'G'B' obtained by smoothing b2, B, and Nb3, respectively, using the select signal S set by the CPU 20, and the main color data is selected. Here, CPU2
0 indicates different data A in registers 65b and 66b.
, B are set, and the selector 63b selects either A or B according to the ArlO signal and inputs it as the S signal to the selector 5lb.

In this way, prepare two registers, 65b and 66b,
Input different data to A and H of selector 63b,
With the configuration in which the area signal ArlO selects one of them, separate color detection can be performed for a plurality of areas. This area signal ArlO may be a signal for not only a rectangular area but also a non-rectangular area.

In the next selectors 52bR, 52b, 52bB, CP
R set by U20. Either +GO+BO or the main color data selected by the selector 5lb is selected by a selection signal generated by the outputs 53ha to 53bc of the decoder 53b and the fixed color mode signal S2. In addition, the selectors 64bR, 64b, ,
By selecting either A or H according to the area signal A r20, the sensor 64b8 can detect different colors for a plurality of areas, as in the case of the selector 63b. Here, Ro, Go, and B0 are selected when the main color is in conventional color conversion (fixed color mode) and gradation color determination, and the main color data is selected when it is a color other than the main color in gradation color conversion. .

Note that the operator can freely select between fixed color determination and gradation color determination from the operation section. Alternatively, it is also possible to change it by software using color data (color data before color conversion) input from an input device such as a digitizer.

These selectors 52bR, 52b, 52b
8 and the upper limit ratio registers 58bR, 58b, 58bB and lower limit ratio registers 59bR, 59bG, 59b8 set by the CPU 20, the upper and lower limit values of R'G' and B', respectively, are determined by the multiplier 56bR, 56bo, 56b8 and 57bR
, 57bG, 57b8 and set as upper and lower limit values in window comparators 60bR, 60b, , 60b8.

Window comparator 60bR, 60bo, 6
AND gate 6 determines whether the data of the main color is within a certain range at 0bB and the two colors other than the main color are within a certain range.
Determined by lb. The register 67b can set "1" regardless of the determination signal by the enable signal 68b of the determination section. In that case, the color to be converted exists in the portion marked with "l".

The above configuration enables fixed color determination or gradation color determination for a plurality of areas.

FIG. 9 is a block diagram of an example of a color conversion circuit.

? The circuit selects the color-converted signal or the original signal based on the output 7b of the color determining section 5b.

In FIG. 9, the color conversion unit 25b includes a selector lllb, registers 112bR, . 112bR■,
112bo,, 1l2b02, 112bB
,,1l2b8■, multiplier 113bR, 113b,,
113b8, selector l14bR, 114bo, 1
14bB, selector 115bR, l15b, 115b
I11, AND gate 32b1 Figure 7 area signal Ar
Ar50, Ar60, Ar generated based on 24
70, the data set by the CPU 20 is sent to the selector lllb, the multipliers 113bR, 113b, ll
3bB, selector 114bR, 114bo, l14
Selector 117b, 112bR, 11 set to b8
2b,, 112b8, 116bR, 116bo,
116bB, and a delay circuit 118b.

Next, we will explain the actual movement.

Selector lllb receives input signals R, N2lb, G
, N' 22b, B, N' 23b (
Main color)? The selection is made according to the selection signal S5. Here, the signal S5 is the area signal Ar40 that selects the selector l17b for the two data set by the CPU20.
Occurs by selecting one of the following. In this way, color conversion processing for multiple areas becomes possible.

The signal selected by selector lllb is sent to multiplier 113.
Multiplication with the register value set by the CPU 20 is performed in bR, 113b, , 113b8.

Here again, the area signal Ar50 has two register values 112
bR, − 112bR■, 112b,, − 1
By selecting 12b, 2, 112b8, .multidot.112bB■ by selectors ll2bR, 112.b, .112bB, respectively, different color conversion processing can be performed for a plurality of areas.

Next, selectors 114bR, 114bo, 114
The result of multiplication in bB and the two fixed values set by the CPU 20 Ro' - Ro' Go *Go Bo'
-Bo, one of the fixed values selected in the selectors 116bR, 116b, 116bB by the area signal Ar 70 is selected by the mode signal S6. Is this also a mode? The signal S6 is selected by the area signal Ar60 in the same manner as S5.

Finally, selector 115bR, 115bo, 115b8 uses select signal SB to select RINGIN/BI.
N (RIN, GIN, BIN delayed and timing adjusted) and selectors 114bR, l14b, 11
Either the output of 4b8 is selected and ROUT
+ G OUT + BO UT. Also hit signal H. U, also R. U■, Go. JA+
It is output in synchronization with BOIJ7.

Here, the selector signal SB is a delay product obtained by ANDing the color determination result 34b and the color conversion enable signal BHi34b. If a non-rectangular enable signal such as the dotted line in FIG. 10 is input as the BHi signal, color conversion processing can be performed on a non-rectangular area. In this case, the area signal is an area like the one-dot chain line, that is, the top left (Fig. 10 a), the top right (Fig. io b), the bottom left (Fig. 10 C), and the bottom left found from the dotted lines. (Fig. 10, d). Also, non-rectangular area belief? BHi is input from an input device such as a digitizer.

When performing color conversion using this non-rectangular enable signal,
Since the enabled area can be specified along the boundary of the area to be converted, the threshold for color detection can be expanded compared to conventional color conversion using rectangles. Therefore, the detection ability is further improved, and an output image subjected to gradation color conversion with high accuracy can be obtained.

From the above, color conversion with brightness according to the main color of the color judgment unit 5b (for example, when converting red to blue, light red is converted to light blue and dark red is converted to dark blue) or fixed value color conversion You can freely perform any of the following for multiple areas.

Furthermore, as will be described later, the hit signal H. Mosaic processing based on U■ only for specific color areas (non-rectangular or rectangular)
Texturing processing, trimming processing, masking processing, etc. can be performed.

Then, as shown in FIG. 2, the output 103 of the color conversion circuit B,
104 and 105 are a logarithmic conversion circuit C1 for converting image data proportional to reflectance into density data; a character image area separation circuit I1 for determining character areas, halftone areas, and halftone dot areas on a document; and the present system. External device interface M for communicating data with external devices via cables 135, 136, 137
will be sent to.

Next, the color image data proportional to the input light amount is
The signal is input to a logarithmic conversion circuit C (FIG. 2) which performs processing to match the luminosity characteristics of the human eye.

Here, white = 00H, black = FF}l is converted as much as possible, and the image sources input to the image reading sensor are, for example, a normal reflective original, a transparent original such as a film projector, and even the same transparent original as a negative film, Since the input gamma characteristics differ depending on the sensitivity and exposure condition of the positive film or film, as shown in Fig. 11(a),
As shown in (b), there are a plurality of LUTs (look-up tables) for logarithmic conversion, which are used depending on the purpose. Switching is done using the signal lines f gO, f gl, I!
g2, and as an I/O port of the CPU 22,
This is performed by inputting an instruction from an operation unit or the like (FIG. 2). Here, the data output for each B, G, and R corresponds to the density value of the output image, and the data output for each B (blue), G
(green) and R (red) signals correspond to toner amounts of Y (yellow), M (magenta), and C (cyan), respectively, so subsequent image data will be yellow, magenta, and cyan. Match.

Next, the color correction circuit D performs color correction as described below on each color component image data from the original image obtained by logarithmic conversion, that is, yellow component, magenta component, and cyan component. As shown in Fig. 13, the spectral characteristics of the color separation filters arranged for each pixel in the color reading sensor have unnecessary transmission areas such as the shaded areas, and on the other hand, for example, the color transferred to the transfer paper Toner (Y, M, C)
It is also well known that the fluorophore also has unnecessary absorption components as shown in Figure 14. Therefore, each color component image data Yi, Mi,
Masking correction is well known in which color correction is performed by calculating a linear equation for each color for Ci. Furthermore, by Yi, Mi, Ci, Min (Yi, Mi, Ci) (Yi, M
(minimum value of i, Ci), set this as black and then add black toner (smearing);
An undercolor removal (UCR) operation is also performed to reduce the amount of each coloring material added depending on the added black component. In Figure 12(a),
The circuit configuration of a color correction circuit D that performs masking, smearing, and UCR is shown. The characteristics of this configuration are: ■ It has two masking matrices, and can be switched at high speed with "1/0" of one signal line. ■ One signal line "1" with and without UCR. /0", it can be switched at high speed. (2) It has two circuits that determine the amount of smear, and it can be switched at high speed with "I/O".

First, prior to image reading, a desired first matrix coefficient Ml and second matrix coefficient M2 are set via a bus connected to the CPU 22. In this example, M1 is placed in registers 87d to 95d, and M2 is placed in registers 96d to 104.
It is set to d.

Also, llld~122d, 135d, 131d, 13
6d is a selector, which selects A when the S terminal is "1" and selects B when the S terminal is "0". Therefore, when selecting matrix M1, switching signal MAREA364="
1'', when selecting matrix M2, set it to "O".

Further, 123d is a selector and a selection signal C. ,C
, (366d), 367d), Figure 12(b)
) outputs a, b, and c are obtained based on the truth table of ). Selection signal C. +CI and C2 correspond to color signals to be output, for example, in the order of Y, M, C, Bk (C2
r C'+ + Co) = (On O+ O)+
(Or O+ 1)+(0, l, 0),
(1, 0. 0), and further as a monochrome signal (0,
1. 1) Desired color correction by? Obtain the color signal. Now (Co, CI, C2) = (0, 0
．． 0) and MAREA="l", the outputs (a, b, c) of the selector 123d contain the contents of the registers 87d, 88d, 89d, and therefore (ay+.
-bMI+-Cc+) is output. On the other hand, Min (Yi, Mi,
The black component signal 374d calculated as Ci) =k undergoes a linear transformation of Y=ax-b (a, b are constants) at 137d, and is then sent to subtracters 124d, 125d, 126d.
is input to the B input of In each subtractor 124d-126d, Y=Yi-(ak-b), M=
Mi − (ak-b), C=Ci − (ak-b
) are calculated, and the signal lines 377d, 378d, 379
d, a multiplier 127d for masking operation,
It is input to 128d and 129d.

The multipliers 127d, 128d, and 129d each have eight inputs (a y+ , − b Ml
, −C c+ ), and the B input has the above-mentioned ( Y
i − (ak − b), M i −
(ak-b), Ci-(ak-b))
= (Yi, Mi, Cil are input, so as is clear from the figure, output D.U■ has Y.l.I under the condition of C2=0 (Y or M or C).
T=? iX (av+) +MiX (-bMt) +
CiX (-Cc+) is obtained, and yellow image data subjected to masking color correction and undercolor removal processing is obtained. Similarly, MOUT=YiX(-ay2)+MiX(-bM
2) +CiX(-CC2)C■ ,, 7 =YiX(
-ay3)+MiX(-bMa)+CiX(-CC3
) is D. Output to U1. Select colors according to the order of output to the color printer (Co, C+, C2)
is controlled by the CPU 22 according to the table in FIG. 12(b). Registers 105d-107d, 108d-1
10d is a register for monochrome image formation, and based on the same principle as the above-mentioned masking color correction, MONO=kl
Yi + j! It is obtained by weighted addition for each color using lMi+m and Ci.

Also, when outputting Bk, C2 (368) is input as a switching signal to the selector 131d, so that C2=1, so the primary converter 133d undergoes a primary conversion such that Y=cx-d, and the output is output from the selector 131d. . Also, Bk
MJl10 is a black component signal output to the outline of a black character based on the output of a character image area separation circuit (2) to be described later. Color switching signal C.

C, , C2 366 to 368 are set from the output port 501 connected to the CPU bus 22, and MAREA
364 is output from the area signal generation circuit 364.

Gate circuits 1 50d to 153d set DHi="l" by a non-rectangular area signal DHil22 read from a binary memory circuit (bitmap memory) L537, which will be described later.
”, the signal C., C) + C2 − “1,
1. 0'' and automatically outputs data for m o n o images.

Character image area separation circuit Next, the character image area separation circuit uses the read image data to determine whether the image data is a character or an image, and whether it is chromatic or achromatic. This is a circuit that determines whether The flow of the process will be explained using FIG. 15.

Red (R) 103, green (G) 104, blue (B) input from color conversion B to character image area separation circuit ■
) 105 is a minimum value detection circuit M I N (R+G
, B) 1011 and the maximum value detection circuit Max (R,
G, B) Input to 102I. In each block, the maximum value and minimum value are selected from the three types of input luminance signals R, G, and B. A subtraction circuit 1041 calculates the difference between the selected signals. If the difference is large, that is, the input R, G, and B are not uniform, this indicates that the signal is not an achromatic signal that indicates black and white, but is a chromatic color that is biased toward some color.

Naturally, if this value is small, it means that the R, G, and B signals are at approximately the same level, and it can be seen that the signal is an achromatic signal and not a signal that is biased towards any color. This difference signal is output to the delay circuit Q as a gray signal GR124. In addition, this difference is calculated using a threshold value arbitrarily set in the register 111I by the CPU and a comparator ll.
2I, and the comparison result is sent to the gray judgment signal GRBil2.
6 and output to the delay circuit Q. These GR125
, GRBil26 are matched in phase with other signals in a delay circuit Q, and then input to a character image correction circuit E, which will be described later, and used as a processing determination signal.

The minimum value signal obtained by M IN (R, G, B) IOII is input to the edge emphasis circuit 103I by performing the following calculation using front and rear pixel data in the main scanning direction. Edge enhancement is performed.

I) oua: Image data Di after edge enhancement
: i-th pixel data Note that edge enhancement is not necessarily limited to the above method, and other known techniques may be used. The image signal edge-enhanced in the main scanning direction is then
The average value within the 3×3 window is calculated using a 5×5 average of 1091 and a 3×3 average of 110×. Line memories 1057 to 108I are delay memories in the sub-scanning direction for performing averaging processing. The 5×5 average value calculated by 5×5 average 109I is then calculated using C, which is also not shown.
Offset values and adders 1151, 1191.124 independently set in the offset section connected to PUBUS
It is added by 1. The added 5×5 average value is limiter 1
It is input to 113I, limiter 2 1181, and limiter 3 123I. Each limiter is connected to a CPU bus (not shown), and is configured so that a limiter value can be set independently. If the 5×5 average value is larger than the set limiter value, the output is clipped at the limiter value. The output signals from each limiter are transmitted to comparator l 1161 and comparator 2 1, respectively.
211, Comparator 3 Human input to 1261. First, in comparator 1 116I, limiter 1
The output signal of 113I and the output from 3x3 average 1101 are compared. Compared comparator l 1161
The output is input to a delay circuit 117I in order to match the phase with an output signal from a halftone area discriminating circuit 122I, which will be described later. This binarized signal is M
In order to prevent distortion and skipping due to TF, binarization is performed using the average value. Further, in order to cut the high frequency components of the halftone dot image so that the halftone dots of the halftone dot image are not detected by binarization, a 3×3 low-pass filter is passed. Next, the output signal of comparator 2 (1211) is binarized with through image data in order to detect high frequency components of the image so that it can be discriminated by halftone area discriminating circuit 1 221 in the subsequent stage. Since a halftone image is composed of a collection of dots, the halftone dot area determination circuit 1221 detects dots by confirming dots from the direction of the edge and counting the number of dots around the edge. A detailed explanation of the halftone area determination circuit 1221 will be omitted since it is not the gist of this patent.

The results determined by the halftone dot area discriminating circuit and the signal from the delay circuit 117 are used in an OR gate 1291.
After removing the erroneous judgment with the erroneous judgment removal circuit 13 (H), the erroneous judgment is removed and outputted to the AND gate 132I.

In this erroneous judgment removal circuit 130I, taking advantage of the characteristics that characters and the like are thin and images have a wide area, first, the image area of the binarized signal is narrowed, and an isolated image area is taken. Specifically, for the center pixel xij, the surrounding area is 1 mm.
When even one pixel other than the image exists within the corner area, the center pixel is determined to be outside the image. After removing the image area of the isolated point in this way, thickening processing is performed to restore the thin image area to its original size. Similarly, the output of the halftone dot discriminating circuit 122I is directly input to the erroneous judgment removal circuit 1311, where thinning processing and thickening processing are performed. Here, the mask size for the thinning process is the same as the mask size for the fattening process, or by making the mask size for the fattening process larger, the determination results when fattening are made to cross each other. Specifically, both the false judgment removal circuits 130I and 1311 are thinned using a 17 x 17 pixel mask, further thinned using a 5 x 5 mask, and then thickened using a 34 x 34 pixel mask. It is being said. The output signal SCRN signal 127 from the misjudgment removal circuit 1311 is a discrimination signal for smoothing only the halftone dot determination section in a character image correction circuit E, which will be described later, to prevent moiré in the read image.

Next, the output signal from the comparator 3 126I should be processed to sharpen the characters in the subsequent stage (extracting the outline of the input image signal). As an extraction method, the output of the binarized comparator 3 1261 is thinned and thickened in 5 x 5 blocks, and the difference area between the fattened signal and the thinned signal is contoured. shall be. The contour signal extracted by such a method is passed through a delay circuit 1281 in order to match the phase with the mask signal output from the misjudgment removal circuit 1301, and then an AND gate 1321 determines that the contour signal is a mask signal and is an image. The contour signal in the part is masked and only the contour signal in the original character part is output. The output from the AND gate 132■ is then output to the contour regenerating section 133I.

<Contour regeneration section> The contour regeneration section 133I processes pixels that are not determined to be character contours to become character contours based on information of surrounding pixels, and as a result, converts MjArl24 into character image correction circuit E. and perform the processing described below.

Specifically, as shown in Figure 16, bold letters ((a) in the same figure)
, the character determination unit determines the dotted line part in (b) as a character and performs the processing described below.
Regarding C)), the character part becomes as shown in the dotted line part in FIG. 10(d), and if the processing described below is performed, it may become unsightly due to misjudgment. In order to prevent this, processing is performed to treat parts that are not determined as characters based on surrounding information.

Specifically, by making the diagonal line part the character part, the character part becomes as shown in the dotted line part (e) in the same figure, which reduces misjudgments even for characters that are so thin that they are difficult to detect, leading to improved image quality. .

FIG. 17 is a diagram showing how surrounding information is used to regenerate a pixel of interest into a character portion.

(a) to (d) are 3 x 3 blocks with text in both vertical, horizontal, and diagonal directions centered on the pixel of interest (both Sl and S2 are "1")
When , the pixel of interest is set as a character portion regardless of the information of the pixel of interest. On the other hand, (e) to (h) are 5 x 5 blocks, with one pixel centered around the pixel of interest, and both vertical, horizontal, and diagonal text parts (SI and S2 are both “1”) are of interest regardless of the information of the pixel of interest. The pixel is used as a character part. Like this 2
The structure of tiered blocks (multiple types of blocks) makes it possible to handle a wide range of errors.

FIGS. 18 and 19 show the skin paths for realizing the process shown in FIG. 17. 18th centroid The circuit in FIG. 19 includes line memories 1641 to 167i, DF/Fs 104i to 126i for obtaining information around the pixel of interest, and FIGS. 17(a) to (
AND gates 146i to 153i for realizing h)
and an OR gate 154i.

Figure 17 (
The information of S, , S2 in a) to (h) is extracted. Further, registers 146i to 153i can independently control enable and disable, respectively, by registers 155i to 1621 corresponding to the processes (a) to (h).

AND circuits 146i-153i and FIGS.
) is as follows.

Figure 20 shows line memory 1 6 4 i-1 6 7
It is a timing chart of WE (ENI) and RE (EN2) of i. This means that ENI and EN2 appear at the same timing when the size is the same, or when it is enlarged (for example, from 200% to 300%).
%), W1 is written once in the thinned out 2 lines.

This expands the size of FIGS. 17(a) to (h).

This is because when enlarging, the information that comes in here comes as an image enlarged only in the sub-scanning direction, so by increasing the size of (a) to (h), processing can be done with the same size image even when enlarging. Is going.

Character Image Correction Circuit> The character image correction circuit E performs the following processing on black characters, color characters, halftone images, and halftone images, respectively, based on the determination signal generated by the character image area separation circuit I described above.

[Processing 1] Processing related to black characters [:1-1] Signal B obtained by black-mark extraction as a video
Use kMjll2 (1-2) Y, M, C data are multivalued achromatic chromaticity signals G
Rl25 If << performs subtraction according to the set value. On the other hand, B
The k data is added according to the multivalued achromatic chromaticity signal GR 1 25 or the set value (1-3) Edge emphasis is performed (1-4) Black characters are printed out at 400 lines (400 dpi) (1-3) 5) Perform color residual removal processing [Processing 2] Processing related to colored characters (2-1) Perform edge emphasis [2-2] Print out colored characters at 400 lines (400 dpi) [Processing 3] Halftone dots Image-related processing (3-1) Smoothing to prevent moiré (main scan 2
[Processing 4] Processing related to halftone images [4-1] Enables selection of smoothing (two pixels at a time in the main scanning direction) or through.

Next, a circuit that performs the above processing will be explained.

FIG. 21 is a block diagram of the character image correction section E.

The circuit of FIG. 21 uses the video input signal 111 or BkM
A selector 6e that selects 112, an AND gate 6e' that generates a signal to control the selector, a block 16e that performs color residual removal processing to be described later, an AND gate 16e that generates an enable signal for the same processing, and a GR signal 125.
and a multiplier 9e that multiplies the I/O port setting value 10e.
', a selector lle that selects the multiplication result 10e or the setting value 7e of the I/O port, a multiplier 15e that multiplies the output 13e of the selector 6e and the output 14e of lle, XOR
Game} 20e, AND game} 22e, adder/subtractor 2
4e, Line memory 2 that delays 1 line data
6e, 28e, edge emphasis block 30e, smoothing block 31e. A selector 33e for selecting through data or smoothing data, a delay circuit 32e for synchronizing control signals of the selector, and a selector 4 for selecting edge emphasis results or smoothing results.
2e, a delay circuit 36e and an OR gate 39e for synchronizing the control signals of the selector, AND
Gate 41e, 400 lines (dpi) for character determination section
Inverter circuit 4 for outputting a signal (“L” output)
4e, an AND circuit 46e, an OR circuit 48e, and a delay circuit 43e for synchronizing the video output 113 and the LCHG 49e. Also, character image correction section E
is connected to the CPU bus 22 via the I/O port le.

Below (1) Color residual removal processing that removes the color signal remaining around the edge of the black text area, subtracting a certain percentage from the Y, M, and C data of the black text part determination section, and subtracting a certain percentage from the Bk data. [2] Edge enhancement for the text part, smoothing for the halftone judgment part, and part where through data is selected for other gradation images, [3] L for the text part.
The process is divided into three parts, each of which is a part where the CHG signal is set to "L" (printed at 400 dpi), and each part will be explained.

[1] Remaining color removal processing and addition/subtraction processing Here, processing is performed for the area where both the signal GRBil26 indicating that it is an achromatic color and the signal MjAR124 indicating that it is a text area are active, that is, the edge area of the black character and its surrounding area, The Y, M, and C components protruding from the edges of black characters are removed, and the edges are filled in.

Next, a detailed explanation of the operation will be given.

This process is subject to character part determination (MjAR124="l"
), this is performed only when the text is black (GRBil26="BI") and the color mode is set (DHil22="O").
”), and color characters (GRBi-“On)”.

When scanning a document for recording color Y, M, or C, the video manual 111 selects it using the selector 6e (1/
0-6 (set to “0” in 5e)). At 15e, 20e, 22e, and 17e, data to be subtracted from video 8e is generated.

For example, if "0" is set in I/O-312e, selector output data 13e
Multiplying by the value set in I/O-178 is performed by multiplier 1.
It takes place in 5e. Here, data 18e that is 1 times larger than 13e is generated. By setting 1 to registers 9e and 25e, the two's complement data of 18e becomes 17e,
Generated at 20e and 22e. Finally, adder/subtractor 24
Since addition 23e of 8e and 23e in e is a two's complement number, 17e-8e is actually subtracted and output from 25e.

When "1" is set in I/O-312e, B data is selected by selector lle.

At this time, the value set in I/O-210e is applied to the multi-valued achromatic color signal GR125 (a signal that takes a large value if it is close to an achromatic color) generated by the character image area separation circuit ■ at 9e. The multiplied value is used as the multiplier of 13e. When this mode is used, the coefficients can be changed independently for each of the colors Y, M, and C, and the amount of subtraction can be changed depending on the achromatic degree.

When scanning recording color Bk, selector 6e selects BkMj1.
12 is selected (I/O-6 5 e has “l”
set). 15e, 20e, 22e, and 17e generate data to be added to video 17e. Above Y,
The difference from M and C is that "0" is set in I/O-4 and 9e, so that 23e=8e and Ci=O, and 17e+8e is output from 25e. Coefficient 14e
The method of generation is the same as for Y, M, and C. Also, I/
In the mode in which "l" is set in O-312e, the coefficient changes depending on the degree of achromatic color. Specifically, when the degree of achromaticness is large, the amount of addition is thick (《), and when it is small, it is small.

This process is illustrated in FIG. 22. (a) and (c) are enlarged views of the shaded portion of the black letter N.

For Y, M, and C data, subtraction from the video is performed when the character signal part is "1" (Figure (b)), and for Bk data, the character signal part is "l". is added to the video ((d) in the same figure). In this figure, 13e=1
8e, that is, the Y, M, and C data of the character section are 0, and the Bk data is twice that of the video.

Through this processing, the outline of black characters is printed in almost a single black color, but the Y, M, and C data outside the outline signal (see Figure 22 (b)
) The * mark shown in ) remains around the letters as residual color, making it unsightly.

The color removal process removes the remaining color.

This processing extends to the area of the text area,
In addition, processing to take the minimum value of 3 or 5 pixels before and after pixels where the video data 13e is smaller than the comparison value set by the CPU, that is, outside the character area, where there is a possibility of color remaining. It is.

Next, the explanation will be supplemented using a circuit.

Figure 23 shows a character area expansion circuit that works to expand the character area.
ND gate 69e, 71e, 73e, 75e,
It is composed of an OR gate 77e.

All I/O ports 70e, 72e, 74e, 76e
When M j A r 1 2 4 is set to "B", the signal expanded by 2 pixels front and rear in the main scanning direction is sent to I/O ports 70e, 75e"0", 71e, 7
3e'' When the signal spread by l pixels front and back in the main scanning direction is S
Output from ig2 18e.

Next, the remaining color removal processing circuit 16e will be explained.

FIG. 24 is a circuit diagram of residual color removal processing.

In FIG. 24, 57e is a 3-pixel min select circuit that selects the minimum value of a total of 3 pixels, including the pixel of interest and one pixel before and after it, in response to the input signal 13e; 58e is a human, force signal +
For 3e, the maximum value of a total of 5 pixels, including the pixel of interest and two pixels before and after it, is selected. 5 pixel min select circuit, 55
e is a comparator that compares the magnitude of the input signal 13e and I/O-18 (54e), and if 54e is larger,
Output l. 61e, 62e are selectors, 53e,
53'e is an OR gate, and 63e is a NAND gate.

In the above configuration, the selector 60e selects 3 pixels min or 5 pixels min based on the value of I/O-19 from the CPU bus. The effect of color residual removal is greater when the number of pixels is 5 pixels min. This can be selected by manual setting by the operator or automatic setting by the CPU.

The selector 62e indicates that the output of the NAND gate 63e is "0".
'', that is, the video data 13e is determined by the converter 55e to be smaller than the register value 54e, and is within the range where the signal of the character part is expanded, and 17'e is 1.
If so, side A is selected, otherwise side B is selected. (However, at this time, registers 52e and 64e are “1”
The register 52'e is "0") When the B side is selected, through data is output as 8e.

The EXCON 50e can be used in place of the converter 55e when, for example, a binary luminance signal is input.

FIG. 25 shows the area where the above two processes have been applied. FIG. 25(a) shows the black character N, and FIG. 25(b) shows the area determined to be a character in the Y, M, and C data, which is the density data of the shaded area, that is, the character determination part (+2.
43. 46. 47) becomes O by subtraction processing,
-%l, %4 is Kaoru 1 ← Ao 0, due to color residual removal processing
Cloud 4 ← bitter 5, resulting in O, Figure 25 (
C) is required.

On the other hand, for B and data as shown in Figure 25(d),
Character judgment part (Ku 8, Kaoru 9, Jk 10, Kan 11)
Only addition processing is applied to the output, resulting in an output with a black ring as shown in FIG. 25.

Note that no changes are made to the colored characters, as shown in FIG. 25(f).

[2] Edge Emphasis or Smoothing Process Here, <<processing is performed to output edge emphasis for the character determination section, smoothing for the halftone dot section, and outputting through for the rest.

Character part → MjAR124 is “1”, so 25e,
3 generated from the 3 line signals of 27e and 29e
The output of the x3 edge enhancement 30e is selected by the selector 42e and output from 43e. Note that the edge enhancement here is obtained from a matrix and calculation formula as shown in FIG.

Halftone part - "SCRN35e is "l", M j A R
Since 2 1 e is "0", the smoothing 31e applied to 27e is the selector 33e, 4
2e is output. Note that smoothing is the second
As shown in Figure 7, when the pixel of interest is vN (V Ill
+V N+1)/2 as vN data, that is, smoothing of two pixels in the main scan. This prevents moiré that may occur in the halftone dot area.

Other→Other portions refers to processing for areas that are neither character portions (character outlines) nor halftone dot portions, specifically, midtone portions. At this time, MjAR124 and SCRN35e
Since both are "0", the data of 27e is output as is from the video output 43e.

When the characters are colored characters, the above two processes are not performed even in the character determination section.

In the embodiment, an example was shown in which color residual removal was performed only in the main scanning direction, but color residual removal processing may be performed in both the main scanning and sub-scanning directions.

[3] Text section 400 lines (dpi) output processing video output 1
13, LCHG140 is output from 48e. Specifically, the inverted signal of MjAR 124 is output in synchronization with signal 43e. When it is a character part, it is LCHGO, and for other parts, it is 200/400="1".

As a result, the character part determination part, specifically the character outline part, is 4
00 line (dpi), and the others are printed at 200 line (dpi).

Next, the character image synthesis circuit F will be explained.

FIG. 28(a) is a block diagram of a circuit for processing and modifying images using binary signals in this apparatus. The color image data 138 input from the image data input section is 3to! It is input to the V input of the selector 45.

For the other two-man power A and B of the 3tol selector 45f,
The lower part (An
, B n) Of the 555f, A has An and B has Bn.
is latched by VCLK117 in latch 44f and input. Therefore, the output Y of the selector 45f has a select input x. , X l+ Jl, J
Based on 21=, either V, A, or -B is output (
114).

In this embodiment, data Xn is the top two data in memory.
This bit is a mode signal that determines processing and modification. 139 is a code signal output from the area signal generation circuit.
It is controlled to switch in synchronization with 117, and the memory 43f
is entered as the address of

That is, for example, (x
lo, AH(1, B+o) = (01. AIO
+ Boo) is written in advance, and as shown in FIG. 29(b), in synchronization with the scanning of line l in the main scanning direction, "lO" is written from point P to point Q in the code signal 139, and "lO" is written from point Q to point R in the code signal 139. 0'' is given, and data x,;(0
．． 1) is read out, and at the same time, data (A+o, B+o) is latched and output in (Afl, B,). The truth table of the 3tol selector 45f is shown in Figure 28 (C
) as shown in <, (X + - Xo) = (0.
1) is the case of (B), and if Jl is "l", 8 inputs are set to Y, and therefore, Y is a constant A1. , Jl is “0”
", it means that the ■input is set to Y, and therefore the input color image data is output as is to the output 114. Thus, for example, for a color image of an apple as shown in FIG. 29(b), ( So-called tweezers character synthesis of the character part with the value (AIO) is realized.Similarly, (X
l + xo) = (t, o), and the second
When a signal like Jl in Figure 9 (C) is input, the FIF
○47f to 49f1 and circuit 46f (details in Fig. 28 (
b)), a signal like J2 in the same figure is generated, and the second
If the truth table in Figure 8(C) is followed, characters will be output with a cross-mark (contour or envelope character) in the image of an apple as shown in the same figure.

Similarly, in FIG. 28(D), the rectangular area inside the apple is (
Bn), and the inner characters are output with a density of (AIl). The same figure (A) is (X1.xo)”
(o, o), i.e. for any Jl,
Depending on the binary signal, there is also control in which nothing is done in response to a change in J2.

The signal with expanded width input to J2 is shown in Fig. 28(b).
According to , the size is expanded by 3×3 pixels, but it is easy to increase the size even further by adding a hardware circuit.

Also, CO and CI (366, 367) output from the I/O port 501 in FIG. 2 in association with the output colors (Y, M, C, Bk) to be printed are stored in the memory 4.
It is input to the lower 2 bits of the address of Y. "0.0" 0 corresponding to M, C, Bk output
, l"l, O", "1, 1", so for example when yellow (Y) is output, it changes as 0, 4, 8, 12.
16...Address, magenta (M) is 1, 5, 9
, 13, I7... address, cyan (C) is 2,
6, 10, 14. 18... number, black (
Bk) is 3, 7, 11, 15. 19...An address is selected. Therefore, according to the operation instructions on the operation panel, which will be described later, the area code signal 139 that determines the area and the corresponding memory address within the area and the corresponding address 2, for example, X1 to x4="1. 1" (Al, A2, A3,
A4) = (αl, α2, α3, α4), (Bl, B
2, B3, B4) = (βl, β2, β3, β4
), for example, 1 as shown in Figure 29 (D).
1 signal changes, the section where J1 is “Lo” becomes (Y,
The color is determined by mixing M, C, Bk) = (αI, α2, α3, α4), and when Jl is “Hi”, (Y, M
, C, Bk) = (βl, β2, β3, β4). In other words, the output color can be arbitrarily determined based on the memory contents. On the other hand, on the operation panel described below,
Y, M, C, and Bk are each adjusted or set in percent (%). That is, since each gradation has 8 bits, the numerical value is 00 to 255, so a 1% fluctuation is a digital value of 2.55.

The setting value is (Y, M, C, Bk) = (Y%.m%, C%
, k%), the values to be set (i.e., the values written to memory) are (2.55Y, 2.55Y), respectively.
m, 2.55c, 2.55k), and in reality, the rounded integer is written into a predetermined memory. Further, if the adjustment mechanism is used to adjust in %, the value obtained by adding (darkering) or subtracting (darkening) 2.55 Δ to the variation in Δ% can be written in the memory.

In the truth table of FIG. 28(C), the i column is an input/output table for characters, image gradation, and resolution switching signal LCHG149, and A or B outputs Y depending on X,, Xo, Jl, and J2. When V is output to Y, it is output as "0", and when V is output to Y, the input is output as is. LCHG149 is a signal for switching the print density during printing, for example, when LCHG="0", for example, 400 dpi, L
When CHG="1", print at 200 dpi. Therefore, when A or B is selected, LCHG = 0 means that the inner area of the synthesized characters is printed at 400 dpi, and the area other than the characters is printed at 200 dpi, and the characters maintain high resolution and are sharp. The halftone part maintains high gradation,
It is controlled to output smoothly. As mentioned above, LCHG140 is a character and image separation circuit! That is why the character image correction circuit E outputs the signal based on MJAR, which is the output of the character image correction circuit E.

<Image processing/editing circuit> Next, image signal 1 after undergoing color balance adjustment at P
15 and the gradation resolution switching signal LCHG141 are input to the image processing and editing circuit G. A rough schematic diagram of the image editing processing circuit G is shown in FIG.

Input image signal 115, gradation resolution switching signal LC
The HG 141 is first input to the texture processing section 101g. The texture processing section is roughly divided into a memory section 103g that stores texture patterns, memories RD and WR that control them, an address control section 104g, and an arithmetic circuit 105g that performs modulation processing on input image data according to the stored pattern. has been done. The image data processed by the texture processing section 101g is then subjected to scaling, mosaic, and taper processing section 1.
02g. The variable magnification, mosaic, and taper processing section 102g has double buffer memory 105g, 10
6g and a processing/control unit 107g, various processes are independently performed and output by the CPU.

Here, the texture processing section 101g and the scaling, mosaic, and taper processing section 102g perform processing on independent areas using enable signals GHil (119) and GHi2 (149) for each process sent from the switching circuit N.
It is configured to perform texture processing and mosaic processing.

Furthermore, the gradation resolution switching signal LCHG signal 141 input together with the image data 155 is processed in various processes while matching the phase with the image signal.

The image processing/editing circuit G will be explained in detail below.

<Texture Processing Unit> Texture processing is a process of cyclically reading out a pattern written in memory and applying modulation to the video. For example, the image shown in FIG. It modulates the image in a pattern like this to generate an output image like that shown in FIG.

FIG. 32 is a diagram illustrating the texture processing circuit.

Below, modulation data 2 to texture memory 113g
18g writing section and 113g texture memory
216g of data and 215g of image data (
Texture processing) will be explained separately.

[Data writing section to texture memory 113g] When writing data, masking, undercolor removal, and smearing are performed, and data is input from 201g. This data is selected by selector 202g. On the other hand, selector 20
8g, data 220g is selected and the memory 113
g and the enable signal of the driver 203g. The memory address is generated by a vertical counter 212g that counts up in synchronization with the horizontal synchronization signal HSYNC and a horizontal counter 211g that counts up in synchronization with the image clock and VCK.B is selected by the selector 210g, and the address of the memory 113g is input.

In this way, the density pattern of the input image is stored in the memory 11.
Written to 3g. Typically, this pattern is an input device,
For example, it is located and written using a digitizer.

[Writing data by CPU] CPU data is selected by the selector 202g.

On the other hand, A is selected by the selector 208g, and the memory 11
3g and input to the enable signal of the driver 203g. As the memory address, A is selected by the selector 210g and inputted to the address of the memory 113g. thus,
An arbitrary density pattern is written into memory.

[Calculation unit for texture memory 113g data 216g and image data 215g] This calculation is realized by a calculation unit 215g. This arithmetic unit here consists of a multiplier. Data 216g and 201 only where enable signal 128g is active
An operation with g is performed, and when the disable is enabled, the signal 201 becomes a through state.

Also, 300g and 301g are XOR and OR gates, respectively, and register 304 is a part that generates an enable signal using MJ signal 308g, that is, a character synthesis signal.
When "0" is set in the register g"1305g, texture processing is applied to areas other than those containing composite character signals.On the other hand, registers 304g"0" and 305g are "0".
When set in the register, texture processing is applied only to the part where the composite character signal is included.

302g is a portion that generates an enable signal using a GHil signal 307g, that is, a non-rectangular signal. When the register 306g is "0", texture processing is performed only where the GHil signal is enabled. At this time enable 12
If 8 is kept active, non-rectangular texture processing is performed that is not affected by non-rectangular signals, that is, synchronized with HSNC.If enable signal GHil and enable 128 are made the same, texture processing is performed that is synchronized with non-rectangular signals. Become.

For example, if a 3 lb bit signal is used for GHil, texture processing can be performed only on a certain color.

The LCHG1N signal 141g is a gradation resolution switching signal, and is delayed by the amount of delay in the arithmetic unit 215g.
It is output from U, 350g.

Mosaic, variable magnification, and taper processing section> Next, the general operation of the mosaic, variable magnification, and taper processing section G12 of the image processing/editing circuit G will be described with reference to FIG.

The image data 126g and the LCHG signal 350g input to the mosaic, scaling, and taper processing section 102g are first input to the mosaic processing section 401g. The mosaic processing unit 401g uses the Mj signal 145 output from the character synthesis circuit F and the area signal GHi 2149 from the switching circuit N.
, after the mosaic clock MCLK from the mosaic processing control unit 402g determines the presence or absence of mosaic processing, the size of the mosaic in the main scanning direction, the composition of characters, etc.
It is input to the o2 selector-403g. Here, the main scanning direction size for mosaic processing is the mosaic clock MCL.
It is made variable by controlling K. Control of the mosaic clock MCLK will be explained in detail later.

l to2 selector-403g, HSYNCI18
is input by the line memory select signal LMSEL frequency-divided by the D flip-flop 406G. The image signal and LCHG signal are output to either Yl or Y2.

1 Output from Y1 of to2 selector-403g is output from line memory A404g and 2tol selector-407
Connected to A of g. Also, the output from Y2 is line memory B405g and 2tol selector-407.
Connected to B of g. When an image is sent from selector 403g to one line memory, line memory A
404g is in write mode and line memory 8
405g is in read mode. Similarly, when an image is sent from the selector 403g to the line memory B 405g, the line memory B is in the write mode and the line memory A 404g is in the read mode. In this way, the image data read out alternately from the line memory A 404g and the line memory 8405g is 2tol.
The selector 407g outputs continuous image data while switching based on the inverted signal of the LMSEL signal output from the D flip-flop 406g. The output image signal from the 2tol selector 407g is then sent to the enlargement processing section 414.
After a predetermined enlargement process is performed in g, the image is output.

Next, write/read control of these memories will be described. First, when writing or reading, line memory A
404g, the address given to the line memory 8405g is synchronized with HSYNC, which is the reference for one scan, and is synchronized with the image C
Up/down counters 409g, 41 to increment and decrement in synchronization with LK.
It is composed of 0g. A counter enable signal output from the line memory address control unit 413g,
The operation of the address counters (409g, 410g) is controlled by a control signal WENB for controlling a write address and a control signal RENB for controlling a read address generated from the scaling control section 415g. These controlled address signals are input to 2tol selectors 407g and 408g, respectively.

The 2tol selectors 407g and 408g provide a read address to the line memory A 404g and a write address to the line memory B 405g when the line memory A 404g is in the read mode in response to the above-mentioned line memory select signal LMSEL. When the line memory A 404g is in write mode, the opposite operation is performed.

Next, memory write pulses WEA and WEB to line memory A and line memory B are outputted from the variable magnification control section 415g. Memory write pulses WEA and WEB are used when reducing the input image and when the mosaic processing control unit 4
Mosaic processing is controlled by a mosaic length control signal MOZWE in the sub-scanning direction output from 02g.

Next, a detailed explanation of these operations will be given below.

Mosaic Processing> Mosaic processing is basically realized by repeatedly outputting one image data.

This mosaic processing operation will be explained using FIG. 34.

First, a mosaic processing control unit 402g independently performs main scanning and sub-scanning mosaic processing control.

First, set the variable corresponding to the desired mosaic size to CPU
The CPU sets the latch 501g (for main scanning) and the latch 502g (for sub-scanning) connected to US.

First, for mosaic processing in the main scanning direction, the same data is written continuously to multiple addresses in the line memory, and for mosaic processing in the sub-scanning direction, writing to the line memory is performed at a specified line within the mosaic processing area. This is done by thinning out each time.

(Main scanning direction mosaic processing) A variable corresponding to the mosaic width in the main scanning direction is set in the latch 501g by the CPU. The latch 501g is connected to the main scanning mosaic control counter 504g,
The setting value is loaded by the HSYNC signal and the ripple carry of the counter 504g.

A counter 504g loads the value set in the latch 501g for each HSYNC, counts a predetermined value, and outputs ripple carry to the NOR gate 502g and AND gate 509g.

Mosaic clock MCL from AND gate 509g
K is a signal obtained by multiplying the image clock CLK by the ripple carry from the counter 504g, and MCLK is output only when the ripple carry occurs.

MCLK output from AND gate 509g is then input to mosaic processing section 401g.

The mosaic processing unit 401g operates the two D flipflops 510g and the flipflop 510 regardless of the Mj signal.
Output g. When the GHi2 signal 149 is 1 and the Mj signal is O, a signal from the flip-flop 511g controlled by the mosaic clock MCLK is output.

When the Mj signal is 1, the output is 510g
Output the signal from. With this control, it is possible to output a part of the mosaic-processed image in the main scanning direction without performing the mosaic process. In other words, it is possible to perform mosaic processing on only the image without performing mosaic processing on the characters that have been synthesized into an image by the preceding character synthesis circuit F as shown in FIG. The output from the selector 512g is input to the 2tol selector 403g shown in FIG. 33 mentioned above. As described above, mosaic processing in the main scanning direction is performed.

(Sub-scanning direction mosaic processing) Similarly to the main scanning direction, the sub-scanning direction is also controlled by a latch 502g connected to CPUBUS, a counter 505g, and a NOR gate 503g. The sub-scanning mosaic width control counter is the ITOP signal 144, 511g1 selector-512g, AND gate 514g, and inverter 513.
It is composed of g. flipflop 510g,
511g includes a gradation resolution switching signal L in addition to the image signal.
CHG is connected, and the flip-flop 510g is connected to the image clock CLK, the flip-flop 511g.
holds the image data input by the mosaic processing clock MCLK and the LCHG signal. In other words, the gradation resolution switching signal LCHG corresponding to one pixel is sent to the flip-flops 510g and 511g in phase.
is held during each cycle of CLK and MCLK. Each retained image signal and LCHG signal are input to a 2to1 selector-512g. The output is switched by the mosaic area signal GHi2 and the binary character signal Mj signal. Selector-512g
generates ripple carry pulses by counting HSYNCI18. The ripple carry pulse is applied to the mosaic area signal GHi to the OR gate 508g.
The inverted signal GHi2 of 2149 and the character signal Mj are input. It is input to the sub-scanning mosaic control signal MOZWE415g, and the NAND gate 515g controls the write pulse generated by a line memory write pulse generation circuit (not shown). The line memory write pulse generation circuit is a circuit whose output clock rate is variable, such as a rate multi-briar which is generally used for variable magnification control. In this embodiment, detailed explanation will be omitted since it differs from the gist of the invention.

The WR pulse controlled by the above MOZWE signal then becomes H
The switching pulse changes from l to 2 selector to W by the switching signal LMSEL signal, which changes the switching pulse every SYNCI18.
WR pulses are alternately output to EA and WEB. With the above control, the mosaic area signal GHi2 signal 149 is “
Even in the case of "l", writing to the memory is performed when the Mj signal becomes "l", so it is possible to output a part of the mosaic processed image in the sub-scanning direction without mosaic processing. 35(a) is a diagram showing the distribution of density values for each pixel for recorded colors in which mosaic processing is actually performed.In the mosaic processing of FIG.
Each pixel in a 3×3 pixel block is set as a representative pixel value. In this process, the mosaic process is not performed on the character A1, that is, the pixels in the shaded area, based on the character signal Mj. In other words, when a composite character and a mosaic processing area overlap, priority can be given to the character.

Therefore, even when mosaic processing is performed, an image can be formed so that only the characters can be read. Note that the mosaic area is not limited to a rectangular shape, and mosaic processing can also be performed on a non-rectangular area.

(Italics, Taper Processing) Next, the italics processing will be described first with reference to FIGS. 33 and 36.

FIG. 36 shows the inside of the line memory address control section 413g in FIG. 33. This line memory address control unit 413g has write and read counters 409g, 4
10g enable signal is controlled, and movement, italics, etc. are possible by controlling an address counter to determine which part of the main scanning line is to be written into or read from the line memory. First, using Figure 36,
The enable control signal generation circuit will be explained.

Counter 701g has a counter output of 0 at HSYNC.
Then, the image clock 117, which is the clock of the counter 701g, is counted. counter 701
The output Q of g is the equisurface comparator 706g, 708g, 7
It is input in 09g and 710g. Comparator 70
The A input side of each comparator other than 9g is connected to an independent latch (not shown) connected to CPUBUS, and any set value and counter 701g are connected to each other.
When the output matches the output, a pulse is output. The output of the equilateral comparator 706g is the J-K flip-flop 70.
8g and the comparator 707g is connected to the K input, and from the time the comparator 706g outputs a pulse until the comparator 707g outputs a pulse
-K flip-flop 708g is configured to output l. This output is used as a write address counter control signal, and the write address counter is activated only in the section where it is 1, and generates an address for the line memory. Similarly, the read address counter control signal controls the read address counter. Here, A of comparator 709g
A selector 703g is connected to the input signal to make the input value to the comparator different depending on whether italic processing is performed or not. Here, when the italic processing is not performed, the value set in the latch connected to CPUBUS (not shown) is input to the A input of selector 703g, and the A input is similarly output by the select signal output from the latch (not shown). It is output from selector 703g. The subsequent operation is performed by the aforementioned comparators 706g and 707.
This is the same operation as g. Next, when performing italics, the value input to A of selector 703g is also input to selector 702g as a preset value. selector
When the select signals 702g and 703g select the B input, the output of the selector 702g is added to an adder 704g with a value set in a latch, also not shown. Here, this value indicates the amount of change for each l line due to the oblique angle, and if the desired angle is θ, then tanθ
is required. The addition result is input to a flipflop 708g clocked by HSYNC 118, and the value is held during one main scan. The output of the flip-flop 705g is connected to the B input of the selector-702g and the selector-7.
Connected to the B input of 03g. By repeating this addition operation, the output value from the selector to the comparator 709g changes at a constant rate for each scan, so that the start of the read address counter is set to HS.
It can be varied at a constant rate from YNC. As a result, the reading from the line memories A404g and A8405g is shifted with respect to HSYNC, and italic processing becomes possible. Further, the amount of change described above may be either positive or negative; if it is positive, the readout will shift away from HSYNC, and if it is negative, it will shift toward HSYNC. In addition, selectors 702g, 7
By changing the select signal of 03g in synchronization with HSYNC, partial italics can be made.

Regarding enlargement processing methods, generally O-order, 1st-order, SINC
There are methods such as interpolation, but since they are different from the gist of the present invention,
Explanation will be omitted. Taber processing is made possible by changing the magnification in the main scanning direction in synchronization with HSYNC for each scanning line while performing diagonal processing.

In addition, in these processes, the input gradation resolution switching signal is processed while matching the phase with the image signal, and the output image data 114 and the output gradation resolution switching signal LCHG are processed.
142 is output to the edge emphasis circuit.

The conceptual diagram of the italic processing and taper processing explained above is shown in the 35th page.
Figure (b). Shown in (C).

FIG. 37(a) is a block diagram showing details of a mask bitmap memory 573L and its control for restricting an area of arbitrary shape. This memory has a shape as shown in FIG. 37(e), for example, and is used for the aforementioned color conversion, image cropping (non-rectangular trimming), and image filling (
It is used as an ON (process)/OFF (non-process) switching signal for various image processing/editing such as non-rectangular painting).

That is, in FIG. 2, BHil23, DHil22,
FHil21, GHil19, PHil45, A
It is supplied via the Hil48 signal line.

As shown in Figure 38, the mask is constructed so that 4 x 4 pixels are used as I blocks, and 1 bit of the bitmap memory corresponds to the ■ block, so for example, l 6
For an image with a pixel density of p e l / m m, 297
For mmX420mm (A3 size), (297
X420
It can be configured with a chip.

The signal 132 input to the FIFO 559L in FIG. 37(a) is a data input line for mask generation as described above. For example, the output 421 of the binarization circuit 532 in FIG. When done manually, first, 4×
In order to count the number of "l" in the block 4, buffers 559L, 560L, 561L for 1 bit x 4 lines are used.
, 562L. FIFO559L~562L
As shown in the figure (output of 559L is input to 56OL,
The output of 560L is connected to the input of 561L, and so on, and the output of each FIFO is connected to a 4-bit parallel memory transistor 563L.
~565L+, :, VCLK+. : is latched (see the timing chart in FIG. 37(d)).

FIFO output 615L and latch 563L, 56
4L, 565L outputs 616L, 617L, 61
8L are added by adders 566L, 567L, and 568L (signal 602L), and the CPU 22 compares the magnitude with the value (for example, "12") set via the I/O port 25L in the comparator 569L. . That is, here, it is determined whether the number of 1's in the 4×4 block is greater than a predetermined number.

In FIG. 37(d), the number of "1"s in block N is . “14”, and the number of 1s in block (N+1) is “4”, so when the signal 602L is “14”, the output 603L of the comparator 569L in FIG. 37(a) is greater than “12”, so m1 ``''When 4n is smaller than 12, it becomes 0. Therefore, by the latch pulse 605L in FIG. 37(d), the latch 570L latches once per 4×4 block, and the The output becomes the DIN input of the memory 573L, that is, the mask creation data. 580L is an H address counter that generates an address in the main scanning direction of the mask memory, and since one address is assigned to a 4×4 block, the pixel clock V
Counting up is performed using a clock obtained by dividing CLK608 by four using a frequency divider 577L. Similarly, 575L is an address counter that generates an address in the sub-scanning direction of the mask memory, and for the same reason, it is counted up by a clock obtained by dividing the synchronization signal HSYNC of each line by 4 by a frequency divider 574L. ■Address operation is 4
It is controlled to be synchronized with the counting (addition) operation of "1" in the X4 block.

In addition, ■ Output of the lower 2 bits of the address counter, 610
L, 611L is NORed by a NOR gate 572L, and a signal 606 gates a 4-frequency clock 607L.
L and the AND gate 571L allows one block to be divided into 4×4 blocks as shown in timing chart FIG. 37(C).
A latch signal 605L is generated so that latching is performed only once. Further, 616L is a data path included in the CPU bus 22 (FIG. 2), 613L is an address bus, and a signal 615L is a write pulse WR from the CPU 22. Memory 57 from CPU 22
During WR (write) operation to 3L, the write pulse is “L”
o", the gates 578L, 576L, and 581L are opened, and the address bus and data path from the CPU 22 are connected to the memory 573L, and predetermined data is written at random, and WR is sequentially written by the H address counter and the ■address counter. (write), RD read, the gate 576' is connected to the I/O port 25 by the control lines of the gates 576'L and 582L.
L, 582L is opened and sequential addresses are provided to memory 573L.

For example, the output 421 of the binarized output 532 or the CPU
22, if a mask as shown in FIG. 39 is formed, images can be cut out, synthesized, etc. based on the area within the bold line frame.

Further, the bitmap memory shown in FIG. 37(a) can be read by thinning out or interpolation in both the H direction and the ■ direction.

That is, as shown in FIG. 40 in detail of the H or V address counter (580L, 575L) in FIG.
For example, when reducing, the B input of the selector 634L should be selected (MULSEL 636L is set to "0").

635L is a thinning circuit (rate multiplier) for the input clock 614L, and FIG. 41 (timing diagram)
As shown in the figure, for example, CLK is thinned out so that it is output once every three times (setting is based on I/O port 641L)
(637L). On the other hand, 630L is set to, for example, "2", and only when the thinned out output 637L is output, the output 638L of address counter 632L and the value set in 63OL (for example, "2") are added, and the result is loaded into the counter. Therefore, as shown in Fig. 41, the clock advances +2m every three clocks as l→2→3→5→6→7→9, etc., resulting in a reduction of 80%.On the other hand, when enlarging, MULSEL="B". , the A input 614L is selected, so as shown in the timing chart of FIG.
Address count is l → 2 → 3 → 3 → 4 → 5 → 6 → 6 →
...and so on.

Figure 40 shows the H address counter 580L1V in Figure 37.
This is the details of the address counter 575L, and since the hardware circuit is the same, the explanation will be limited to FIG. 37 only.

As a result, as shown in Fig. 42, enlargement 2 and reduction l are generated for the input non-rectangular area 1, so once the non-rectangular area is input, no new input work is required. Furthermore, with one mask brain, it is possible to change the magnification according to various magnifications.

Next, the binarization circuit (532 in FIG. 2) and the high-density binary memory circuit K will be explained. In FIG. 43(a), the binarization circuit 532 outputs the video signal 1 of the output of the character image correction circuit E.
13 with a threshold value 141k to obtain a binary signal, the threshold value is set by the CPU bus 22 in conjunction with the operation unit. In other words, the threshold value is the amplitude value of the input data -
256, the memory of the operation unit in FIG. 43(C) is set to M(
When specified as the midpoint), it is "128", and as the scale moves in the ten directions, it changes by -30" from the midpoint, and as it moves in one direction, it changes by "+30". Therefore, "Weak → -2 → - 1→M→+l→+2→strong”, the threshold value is “218→188→158→128→98→68→3
It is controlled to change to 8''.

In addition, as shown in FIG. 43(a), CPUBUS
From 22, two threshold values are set, and the selector 35
At k, it is switched by the switching signal 151 and set as a threshold value in the converter 32k. For the switching signal 151, a different threshold value is set only in a specific area set by the Digitiger 58. For example, the threshold value is relatively low for a monochromatic area of a document, and the threshold value is relatively low for a mixed color area. By setting it high, it is possible to always obtain a uniform binary signal regardless of the color of the original.

The memory circuit K is a memory that stores the signal in which the binarized signal 421 is output to 130 for one page of images, and since this device handles images at A3 and 400 (dpi), approximately 3 It has 2 Mbit.

Details of the memory circuit K will be explained in FIG. 43(b).

The input data D and N130 are gated by the enable signal HE528 during memory writing, and are further controlled by the CPU 20 during writing.■0 port 23k? /R
When the l output is "Hi", it is input to the memory part 37k. At the same time, the synchronization signal HSYNC118 in the main scanning (horizontal scanning) direction is transmitted from the synchronization signal ITOP144 in the vertical direction of the image.
to generate a vertical address. (2) The address counter 35k1HSYNC118 counts the image transfer clock VCLKll7, and counts the addresses in the horizontal direction. The H address counter generates an address corresponding to storage of image data.

Memory WP input at this time (write timing signal)
A clock having the same phase as the clock VCLK117 is input as a strobe to the clock 551k, and the input data Di is sequentially stored in the memory part 37k (timing diagram, No. 4).
Figure 4). When reading data from the memory 37k, the control signal W/Rl is set to "Lo" and the output data D is read in exactly the same manner. U■ is read out. However, since data writing and reading are both performed by the HE528, for example, as shown in Figure 44 (HE528
is raised to ``Hi'' at the input timing of D2, and Dm
When it falls to ``Lo'' at the input timing of , only the images from D2 to Dm are input to the memory 37k, and the images after Do, D, and Dm++ are not written, and data ``0'' is written instead.Reading is the same, and except for the section where HE is “Hi”, the data is “
O" will be read out. HE is output from the area signal generation circuit l7, which will be described later. That is, for example, when a character document as shown in FIG. 45A is placed on the document table, 2
If HE is generated as shown in the figure when writing the digitized signal, it is possible to import a binary image into the memory using only the character part as shown in A'. Similarly, unnecessary characters can also be erased and written into the memory.

Furthermore, since the address counters 35k and 36k that read data from the memory 37k have the same configuration as in FIG. 40 and operate at the same timing as in FIG. 41, the binary data read from the memory 37k is It becomes possible to change the magnification. Therefore, when synthesizing the binary character image shown in (B) of the same figure, which has been previously stored in this memory as shown in Fig. 46, with the image of (A), both of them are reduced as shown in (C). or create a sketch ((A) as shown in (D)).
It is possible to perform composition by enlarging only the character part to be composited without changing the size of the part ).

FIG. 47 shows the data stored at the equivalent of 100 dpi as described above.
Binary bitmap memory L for non-rectangular masks (Figure 2) and 400d pi binary memory K for characters and line images (Figure 2)
Each image processing block of data from A, B, D,
This is a switching circuit for switching between distribution to F, P, and G and distribution of binarized video images to memories L and K. The mask data for limiting the non-rectangular area stored in the memory is, for example, the color conversion circuit B described above.
(BHi 123), for example, in Figure 48 (
Color conversion is applied only to the inside of the shape shown in B). Fourth
In Figure 7, In is the I/O connected to the CPU bus 22.
Ports 8n to 13n are 2tol selectors, and are configured to output 8 inputs to Y when switching input S="9", and output B input to Y when S="0". Therefore, for example, in order to send the output of the 100 dpi mask memory L to the color conversion circuit B as described above, in the selector 9n,
, that is, 28n="1", and 2In manual power="l" in AND gate 3n. Similarly, other signals can be arbitrarily controlled by 16n to 31n. I
The outputs 30n and 31n of the /O port n1 are control signals for storing the output of the binarization circuit 532 (Fig. 2) in the binary memory L or K. When 30n="L",
Binary human power 421 goes to 100dpi memory L, 31n="
1", it will be input to the 400 dpi memory K.

By the way, when AHil48="1", the image data sent from the external device is combined and BHil23="1"
”, color conversion is performed as described above, and DHil22=
When "l", monochrome image data is calculated and output from the color correction circuit. Below FHi 121, PHj145
, GHi119, and GHi2 149 are used for character composition, color balance change, texture processing, and mosaic processing, respectively.

In this way, it has two binary memories, 100 dpi memory L and 400 dpi memory K, and stores character information in high-density 4-bit memory.
By inputting area information (including rectangular and non-rectangular areas) into the 00 dpi memory K and inputting area information (including rectangular and non-rectangular areas) into the 100 dpi memory L, character synthesis can be performed in a predetermined area, especially in a non-rectangular area.

Furthermore, by having a plurality of bitmap memories, color mudding processing as shown in FIG. 62 is also possible.

FIG. 49 is a diagram for explaining the area signal generation circuit J. The area refers to, for example, the shaded area in FIG. 49(e), which refers to the timing chart AREA in FIG. 49(e) for each line in the section in the sub-scanning direction A-B.
It is distinguished from other areas by signals such as . Each area is designated by digitizer 58 in FIG. Figure 49(a)-(d)
), the generation position, section length, and number of sections of this area signal are C
This shows a configuration that is programmable and can be obtained in large numbers by the PU 20. In this configuration, one area signal is generated by one bit of a CPU-accessible RAM, and for example, in order to obtain n area signals AREAO-AREAn, two RAMs each having an n-bit configuration are used. (Fig. 49(d) 60j, 61i). Now, Figure 49 (
If the area signals AREAO and AREAn as shown in b) are obtained, "1" is set in bit 0 of address XI+X3 of the RAM, and all bits 0 of the remaining addresses are set to "0". On the other hand, RAM address l,X I+
x2+x4 is set to "l", and all bits n of other addresses are set to mO". If data in the RAM is sequentially read in synchronization with a constant clock 117 using HSYNC 118 as a reference, for example, 4
As shown in FIG. 9(C), data "l" is read at addresses X1 and x3. This read data is J- of 62j-0 to 62j-n in FIG. 49(d).
Since it is connected to both the J and K terminals of the K flip-flop, the output toggles, that is, when "1" is read from the RAM and CLK is input, the output changes from "0" to "L".
By changing from "l" to "0", an interval signal such as AREAO, and hence an area signal is generated. Furthermore, if data is set to "O" over all addresses, no area section is generated and no area is set. FIG. 47(d) shows this circuit configuration, and 60j and 61j are the aforementioned RAMs.

For example, R
While reading data line by line from the AMA 60j, the CPU 20 (Figure 2) performs memory write operations for setting different areas to the RAMB 61j, and alternately generates sections and writes data from the CPU. Switch memory writing. Therefore, Fig. 49(f)
If you specify the shaded area of
In figure (d), (C3, C4, Cs) = (0,
l, 0), the counter output counted by VCLK117 is given as an address to RAMA60j through selector 63j (Aa), and gate 66
j is opened, gate 68j is closed, the data is read from RAM 60j, and the total bit width, n bits, are input to J-K flip-flops 62j-0 to 62j-n, and ARE A O - is output according to the set value. A R E A n interval signal is generated. Writing to B from the CPU is
During this time, address bus A-Bus, data bus D-B
This is done using us and the access signal R/W. Conversely, when generating a section signal based on the data set in RAMB61j (C3 + C4 1 C5)
By setting it to 1 (1+0.1), the same operation can be performed and data can be written from the CPU to the RAM 60j.

58 is a digitizer for specifying an area;
The coordinates of the specified position are input from U20 via the I/O port. For example, in Figure 50, if you specify two points A and B, A (X + + Y 2 ), B (X2.YI
) coordinates are input.

FIG. 51 shows an interface circuit M for bidirectional communication of image data with an external device connected to this image processing system. 1m is an I/O port connected to the CPU bus 22, and each data bus AO-CO, AI
Signals 5m to 9m for controlling the direction of -Cl1D are output. 2m and 3m are pass buffers having an output dry state control signal E, and 3m can change its direction by inputting D. For 2m and 3m, when E input = “l”,
When the signal ' is output and is "0", the output is in a high impedance state. 10m is 3 systems of parallel human power A, B
, C by selecting one from selection signals 6m and 7m 3
tol selector. Basically, the main thing in this circuit is 1.
．． (AO, BO, Co) → (AI, Bl, Cl),
2. There is a bus flow of (AI, Bl, CI)→D. Each is controlled by the CPU 20 as shown in the truth table of FIG. In this system, the 53rd
As shown in the figure, At, A2,
The image input through A3 has a rectangular shape as shown in FIG. 53 (A), and a non-rectangular shape as shown in FIG. When inputting in a rectangular shape as shown in FIG. 53 (A), change the switching input of selector 503 in FIG.
“1” is selected so that I/O port 50 is selected.
1 outputs a control signal 147.

Corresponds to the area to be combined at the same time. Area signal generation circuit J
The rectangular area signal 129 is generated by writing predetermined data from the CPU to predetermined addresses in the RAMs 60j and 61j (FIG. 51), as described above.

In the area where the image input 128 from the external device is selected by the selector 507, not only the image data 128 but also the gradation and resolution switching signals 140 are switched at the same time. That is, in a region where an image from an external device is input manually, it is generated based on the character area signal MIAR 124 (FIG. 2) detected from the color separation signals of the image read from the document table. By stopping the gradation and resolution switching signals and forcibly setting them to "Hi," the image area from the inserted external device is outputted smoothly in high gradations.

Further, as explained in FIG. 51, bitmap mask signal AHi 148 from binary memory L
When selected by signal 147 at 03, Fig. 53 (B)
Image synthesis from external devices such as

<Outline of operation section> FIG. 54 shows an overview of the main body operation section 1000 of this embodiment. Key 1100 is a copy start key.

Key 1101 is a reset key that returns all settings on the operation unit to the values at power-on. A key 1102 is a clear stop key, which is used to reset input values such as specifying the number of copies and to cancel a copy operation.

A group of keys 1103 is a numeric keypad and is used to input numerical values such as the number of copies and magnification input. A key 1104 is a document size detection key. A key 1105 is a center movement designation key. The key 1106 is AC. This is the S function (black original recognition) key. When ACS is ON, a monochrome black original will be copied in monochrome black. A key 1107 is a remote key, and is a key for passing control to a connected device. key 110
8 is a preheating key.

A liquid crystal screen 1109 displays various information.

The surface of the screen is a transparent touch panel, and when you press it with your finger, the coordinate values are captured.

In the standard state, the magnification, selected paper size, number of copies, and copy density are displayed. While setting various copy modes, the screens necessary for mode settings are displayed one after another. (The copy mode is set using the keys displayed on the screen.) Also displays the self-diagnosis display screen on the guide screen.

A key 1110 is a zoom key, and is an enter key for entering a mode for specifying the magnification of magnification. The key 1111 is a zoom program key, and the 6 enter key is used to enter a mode for calculating the magnification ratio from the original size and copy size. The key 1l12 is an enlarged continuous shooting key, and is an enter key for entering enlarged continuous shooting mode.

A key 1113 is a key for setting inset composition.

A key 1114 is a key set for character composition. key 1
115 is a key for setting color balance. key 1
Reference numeral 116 is a key for setting a color mode such as single color, negative/positive inversion, etc. Key 1117 is a user's color key, and can set any color mode. key 111
8 is a paint key that allows you to set the paint mode. A key 1119 is a key for setting a color conversion mode.

Key 1120 is a key for setting the contour mode. Key 1121 is used to set the mirror image mode. Specify trimming and masking with keys 1124 and 1l23.

It is possible to specify an area using the key 1122 and set the internal processing differently from other parts. key l129
is the enter key to enter the mode that performs tasks such as loading texture images. Key 1128 is an enter key for entering a mosaic mode such as changing the mosaic size.

Key 1127 is an enter key to a mode that adjusts the edge sharpness of the output image. The key 126 is a key for setting an image repeat mode in which a designated image is repeatedly output.

The key l125 is the image. This key is used to apply italic/taeno processing, etc. to the image. The key 1l35 is a key for changing the movement mode. The key 1l34 is used to make settings such as continuous page copying and arbitrary division, and the key 1l33 is used to make settings related to the projector. Key 1132 is an enter key to a mode for controlling optional connected equipment.

The key 1131 is a recall key that allows you to recall the settings up to three times ago. Key l130 is an asterisk key.

Keys 1136 to 1139 are mode memory recall keys.
Used when recalling a registered mode memory. Keys 1140 to 1143 are program memory call keys, which are used to call up registered operation programs.

<Color conversion operation procedure> The procedure of color conversion operation will be explained using FIG. 55.

First, when the color conversion key 1119 on the main body operation section is pressed, the display section 1109 is displayed as PO50.

Place the original on the digitizer and use the pen to specify the color before conversion. When the input is completed, the screen of PO51 appears. Here, use the touch keys 1050 and 1051 to adjust the width of the color before conversion, and after completing the settings, press the touch key 1052.
Press. The screen changes to PO52, and the touch key 1053 and touch key 1054 are used to select whether or not to add shading to the converted color.

If you select shading, the color after conversion will have gradation to match the shading of the color before conversion. That is, the above-mentioned gradation color conversion is performed. On the other hand, if you select no shading, the specified color will be converted to the same density. If you select whether or not to have shading, the screen of P053 will appear, allowing you to select the type of color after conversion. When 1055 is selected in P053, P
054, the operator can specify any color. Further, when the color adjustment key is pressed, the process moves to P055, and color adjustment can be performed in 1% increments for each of Y, M, C, and Bk.

Also, if 1056 is pressed on PO53, the screen moves to PO56, and the desired color of the document on the digitizer is specified using the pointer. Next, the color shading can be adjusted using PO57.

Furthermore, if 1057 is pressed at P053, the screen moves to P058, where a predetermined registered color can be selected by number.

Procedure for specifying the trimming area> Below, using Figures 56 and 57,
The same goes for masking, and how to specify areas.
The same procedure applies to partial processing, etc. ) Explain the procedure for specifying an area.

Press the trimming key l124 on the main unit operation unit l000, and when the display unit l109 changes to Pool, use the digitizer to input two diagonal points of the rectangle.The POO2 screen will appear, allowing you to continue inputting the rectangular area. can. Also, if you have specified multiple areas, press the area key 1001 before POOI, then press the area key 1 002 to display POOI.
As shown in 2, each designated area in the X-Y coordinates can be confirmed.

On the other hand, in this embodiment, it is possible to specify a non-rectangular area using the bitmap memory. While displaying the screen of P001, touch key 1003 is pressed to move to POO3. Select the shape here. For circles, ellipses, R rectangles, etc., when the necessary coordinate values are input, the shapes are expanded into the bitmap memory by calculation. In the case of free shapes, coordinate values are input continuously by tracing the desired shape with a point pen using a digitizer, and the values are processed and recorded on a bitmap.

Each non-rectangular area specification will be explained below.

(Circular area designation) When key l004 is pressed at P003, the display section 1109 will display P.
Moving to 004, a circular area can be specified.

The circular area designation will be explained below using the flowchart of FIG. 58. In Slot, the center point is input from the digitizer 58 in FIG. 2 (POO4).

Next, the display unit 1109 moves to P005 and inputs one point on the circumference of a circle having the radius to be specified from the digitizer 58 in S103. In S105, the input coordinate values shown in FIG. 2 are stored in bitmap memory L (look%pi binary memory).
The above coordinate values are calculated by the CPU 20.

Further, in S107, coordinate values of another point on the circumference are calculated.

Next, a bank of the bitmap memory L is selected at 8109, and the above calculation result is input to the bitmap memory L via the CPU bus 22 at Sill. Figure 37(a)
The data is written from CPU DATA 616L to bitmap memory from 604L via driver 578L. Address control is the same as described above, so it will be omitted. This is repeated for all points on the circumference (3113) to complete the circular area designation.

Note that instead of inputting information while calculating it on the CPU 20 as described above, template information for the two pieces of information to be inputted is stored in the ROMII, and these two pieces of information are stored in the ROMII.
It is also possible to write the point directly into the bitmap memory L without calculation by specifying the point with a digitizer.

(Specify oval area) P0031m, press key l005, poo7+
．． :． Move. The process will be explained below using the flowchart shown in FIG.

First, in S202, the diagonal 2 of the largest rectangular area inscribed in the ellipse
A point is designated by the digitizer 58. Below, for the circumferential part, do 8206 in the same way as in the case of specifying the circular area above.
The data is written to the bitmap memory L in the steps from ~S212.

Next, the straight line portion is written into the memory L in steps 3214 to S220, and the area specification is completed. As in the case of a circular shape, it can also be stored in the ROM 21 in advance as template information.

(R rectangular area designation) The method of designation is the same as in the case of an ellipse for memory writing, so the explanation will be omitted.

Incidentally, although the cases of a circle, an ellipse, and an R rectangle have been explained above as examples, it goes without saying that other non-rectangular areas can also be specified based on the same template information.

In POO6, POO8, POIO, and P102, by pressing the clear key (1009 to 1012) after inputting each shape, it is possible to partially erase the bitmap memory.

Therefore, even if a mistake is made in the designation, only the two points can be quickly cleared and the two points can be designated again.

It is also possible to specify multiple areas in succession. When multiple areas are specified, priority is given to processing of the area specified later when processing each of the overlapping areas. However, the one specified first may be given priority.

FIG. 57 shows an output example obtained by trimming with an ellipse using the above settings.

Operational Procedures for Character Synthesis> The operation and setting procedures for character synthesis will be described below with reference to FIGS. 60, 61, and 62. When you press the character synthesis key 1114 on the main body operation section, the liquid crystal display section 1109 displays P.
It is displayed as 020. A character original 120l to be synthesized is placed on the above-mentioned original table, and when the touch key 120 is pressed, the character original is read, binarized, and the image information is stored in the above-mentioned bitmap memory FIG. 2. The specific means of processing has been described above, so duplication will be avoided. At this time, to specify the range of the image to be stored, press the touch key 1021 in PO20 to go to the screen of PO21, place the text original 1201 on the digitizer 58, and use the point pen of the digitizer to mark the range with two points. specify.

When the specification is completed, the display section changes to P022, and the user selects whether to read within the range specified by the touch keys 1023 and 1024 (trimming) or to read outside the specified range (masking). Also,
Depending on the text document, it may be difficult to extract the character portion of the text document during the above-mentioned binarization process. In this case, the touch key 1022 in PO20 moves to the screen of PO23, and the slice level of the binarization process can be adjusted using the touch keys 1025 and 1026.

Since the slice level can be adjusted manually in this way, appropriate binarization processing can be performed depending on the color, thickness, etc. of the characters on the document.

Furthermore, press the touch key 1027, PO24'PO2
By specifying an area with 5', it is possible to partially change the slice level with PO26'.

In this way, by specifying an area and changing the slice level only for that part, even if there is, for example, yellow text in a part of the black text document, separate appropriate slice levels can be set for each of the black and yellow text. By doing so, it is possible to perform good binarization processing on the entire character.

When the reading of the character original is completed, the display section l109 becomes as shown in FIG. 61 P024.

To select color blank processing, touch key 10 in P024
Press 27 to move to the screen of P025, and select the color of the characters to be combined from among the displayed colors.

It is also possible to partially change the color of the text, in which case the user presses the touch key l029 to move to the screen of PO27, specifies an area, and then selects the color of the text on the screen of PO30. Furthermore, it is also possible to add color border processing to the edges of the characters to be synthesized, in which case P030
Use the touch key 1031 inside to move to the PO32 screen and select the color of the border. At this time, color adjustment can be performed in the same way as in the case of color conversion described above. Furthermore, touch key 1033
Press to adjust the border width on the PO4 1 screen.

Next, a case in which color number processing is added to a rectangular area containing characters to be synthesized (hereinafter referred to as square processing) will be described. P02
Press the touch key 1028 in 4 to move to the screen P034 and specify the area. The processing will be performed within the range specified here. When the area designation is completed, the character color is selected in P037, the touch key 1032 is pressed, the screen moves to PO39, and the color of the square is selected.

In the above color selection, for example, on the screen P025, by pressing the color adjustment key of the touch key 1030, the screen moves to the screen PO26, where it is possible to change the tone of the selected color.

Character synthesis is performed according to the procedure described above. FIG. 62 shows an example of the output when the settings are actually made.

In addition to specifying a rectangular area, the area specification can also specify a non-rectangular area as described above.

<Texture processing setting procedure> Next, texture processing will be explained using FIG. 63.

When the texture key 1129 on the main body operation section 1000 is pressed, the display section 1109 displays something like PO60.

When applying texture processing, touch key 1060 is pressed to highlight this key. When reading an image pattern for texture processing into the above-mentioned texture image memory (Fig. 32, 113g), press the touch key 106.
Press 1. At this time, if the pattern is already in the image memory, as in P062, if it is not displayed, P
O61 will be displayed. By placing the document with the image to be read on the document table and pressing the touch key 1062,
Image data is stored in the texture image memory.

At this time, in order to read any part of the document, the user presses the touch key 1063 and makes a designation using the digitizer 58 on the P063 screen. The specified reading range is 16m'mX.
This can be done by inputting with a pen at one point at the center of 16 mm.

Reading of a texture pattern by specifying one point as described above can be performed as follows.

Without reading the pattern, press the touch key 1060, set the texture processing, and press the copy start key 1.
If an attempt is made to escape from the P064 screen using 100, other mode keys (1110 to 1143), or touch key 1064, the display section issues a warning as shown at P065.

Further, the length and width of this range can be specified by the operator.

<Mosaic processing setting procedure> FIG. 64 is a diagram explaining the procedure of mosaic processing setting.

When the mosaic key 1128 on the main body operation section is pressed, the display section displays something like PIOO. To apply mosaic processing to a document, touch key 1400 is pressed to highlight this key.

Furthermore, when performing mosaic processing, the mosaic size can be changed by pressing the touch key 1401 on the P101 screen. The mosaic size can be changed independently in both the vertical (Y) direction and the horizontal (X) direction.

<About feeding mode operation procedure> FIG. 65 is a diagram illustrating the cloud mode operation procedure.

When the tatami key 1130 on the main body operation section 1000 is pressed, the screen mode is entered, and the display section 1109 is displayed as PI 10. Touch key 1 500 enters a color registration mode for registering color information used in paint user colors, color conversion, color text, and the like. A touch key 1501 turns on/off a function for correcting image defects caused by the printer. Touch key 1502 is a key for entering mode memory registration mode. The touch key 1503 enters a mode for specifying the manual feed size. Touch key 1504 enters program memory registration mode. A touch key 1505 is a key for entering a mode for setting a default color balance value.

(About color registration mode) When PI10 is displayed, press touch key 1 500.
Enter color registration mode. The display will look like Plll,
Select the type of color to register. To change the palette color, press the touch key 1506, select the color you want to change on the screen of P116, and adjust the values of each component of yellow, magenta, cyan, and black in 1% steps on the screen of PI17. can do.

Also, if you want to register any color on the document, touch key l.
Press 507, select the registration number on the PI18 screen,
Specify using the digitizer 58, set the original on the original table when the screen of P120 is displayed, press the touch key 1510,
Register.

(About manual feed size specification) As shown on page 112, manual feed size can be specified as either standard or non-standard size.

For irregular shapes, both the horizontal (X) direction and the vertical (Y) direction can be specified in units of 1 mm.

(Regarding mode memory registration) The set mode can be registered in the mode memory as shown in P113.

(Regarding Program Memory Registration) As shown in P114, a series of programs for specifying an area or performing predetermined processing can be registered.

(Regarding color balance registration) As shown in P115, color balance can be registered for each of Y, M, C, and Bk.

<Regarding program memory operation procedure> The registration operation in the program memory and its usage procedure will be explained below with reference to FIGS. 66 and 67.

Program memory is a memory function that stores operating procedures related to settings and reproduces them. It is possible to connect the necessary modes and make settings that go beyond unnecessary screens. As an example, let's program memory the procedure for changing the magnification of a certain area of a document and repeating the image.

Press the Kaoru mode key 1130 on the main body operation section to display the screen P080 on the liquid crystal display section, and press the program memory key of the touch key 1200. In this embodiment, four programs can be registered. Select the number to be registered on the P081 screen. After this, move to program registration mode. In the program registration mode, for example, the screen shown in 300 in FIG. 68 in the normal mode changes to 1301. The skip key of touch key l302 is designated when the user wants to skip the current screen. The clear key of the touch keys 1303 is used when canceling the current registration in the middle of program memory registration and redoing the registration from the beginning. The end key of touch key 1304 exits the program memory registration mode and registers in the memory of the first determined number.

First, press the trimming key 1124 in the main unit operation section,
Specify the area with the digitizer. The display unit is displaying PO84, but if no further area settings are to be made at this point, touch key 1202 is pressed to designate skipping this screen. (The screen becomes PO85) Next, when the zoom key 1110 on the main body operation section is pressed, the display section becomes P086. Here, the magnification is set and when touch key 1 203 is pressed, the display changes to P087. Finally, press the image repeat key 1126 on the main body operation section, make settings regarding image repeat on the screen P088, and then register to program memory No. 1 using the touch key 1204.

To call up the program registered in the above procedure, press the program memory 1 call key 1140 on the main body operation section. The display section displays PO91 and waits for area input. If you input the area using a digitizer,
The display section is P. 092 is displayed, and the process further moves to the next P093. After setting the magnification here, if the touch key 1210 is pressed, the display section changes to PO94 and image repeat can be set. When the touch key 1211 is pressed, the mode in which the program memory is used (referred to as trace mode) is exited.

Note that from the time the program memory is called until the program is terminated,
Each key (1110 to 1143) in the edit mode is disabled, and operations can be performed according to the registered program.

FIG. 69 shows the program memory registration algorithm. Screen turning in S301 means changing the display on the display unit using keys or touch keys.

If you press the touch key 1302 and specify to skip the currently displayed screen (S303), that information will be set on the recording table when the next screen is turned (S303).
305). Then, in S307, a new screen number is set in the recording table. If the clear key is pressed, the record table is completely cleared (S309, S311); otherwise, the process returns to S301 and moves to the next new screen. FIG. 71 shows the format of the recording table. FIG. 70 shows an algorithm representing the operation after calling the program memory.

If there is a screen shift in S401, it is determined whether the new screen is a standard screen (S403). If it is a standard screen, the process moves to S411 and sets the next screen number from the recording table; if it is not a standard image, the new screen number is compared with the scheduled screen number in the recording table (S405);
If they are equal, the process moves to S409, and if there is a skip flag, S411 is skipped and the process returns to S401. If they are not equal, a recovery process is performed (S407) and the screen is rotated.

The correspondence relationship between this embodiment and the scope of the claims will be explained.

In this embodiment, the 5×5 average of 1091 in FIG. 15 corresponds to the average value of the first block pixel area, and
The 3×3 average of tot corresponds to the average value of the second block pixel area.

In this example, a 5x5 block was used as the first block pixel area, and a 3x3 block was used as the second block pixel area, but the way the blocks are arranged may be changed depending on the image quality and hardware configuration. Of course, the methods are not limited to these.

Furthermore, the "predetermined value" in the claims can be set to an appropriate value so that the determination can be made with high accuracy.

Moreover, instead of adding a predetermined value of offset to the average value of the first block pixel area, it may be considered that the configuration is the same even if a predetermined value is subtracted from the average value of the second block pixel area. That is, exactly the same effect can be obtained.

According to this embodiment, the first block pixel area is 5×
Since the average value of five blocks is taken and binarized, it is possible to prevent distortion and skipping due to MTF.

In addition, since the average value of the 3x3 block, which is the second block pixel area, is taken and binarized, the high frequency component of the halftone image can be set, and the halftone dots of the halftone image can be detected by binarization. You can prevent it from happening.

Furthermore, since the offset is set to a predetermined value, character images can be discriminated with high accuracy by setting an appropriate value to minimize misjudgments.

Therefore, characters such as black characters can be accurately separated from the image, and Bk (black) can be used for processing black characters.
By using only toner, clear black characters without color bleeding can be reproduced.

[Second Example] In this example, the reflected light from the original is divided into R, G, B
An image processing device that obtains an image signal by separating the colors into three colors and photoelectrically converting them using an image sensor, includes an emphasis circuit that performs emphasis processing on the image signal, and also connects a luminance signal from the emphasized image signal. It has two matrices of different sizes as a means of binarization, a smoothing circuit that calculates the average value in the vicinity of the pixel of interest, and a circuit that compares the two average values. An image processing apparatus characterized by performing image processing will be described.

In particular, it is characterized by having an offset within the smoothing circuit.

Conventionally, image binarization processing devices pre-scan a document and binarize the image signal using a fixed threshold, or binarize the pixel of interest using the average value around the pixel of interest as a threshold.
Some methods convert the image signal into a value, or extract the change in the average value of the image signal using a low-pass filter or the like, set a threshold value based on this, and then perform binarization.

However, in the conventional method described above, floating binarization is simply performed as a binarization method for the pixel of interest.
Even in halftone images, there are areas where highlights and dark areas are adjacent to each other, and there are also areas where patterns of white (ON) and black (OFF) appear successively, so it is difficult to distinguish between text areas and halftone areas. Binarization separation could not be performed.

Therefore, in this embodiment, the reflected light from the original is collected using a CCD.
It separates the color into three colors of R, G, and H using an image sensor such as , and is equipped with a processing circuit for shading correction, color shift correction, and MTF correction, and calculates the luminance based on NTSC conversion from the R, G, and B signals. By providing a conversion circuit and a signal enhancement circuit for obtaining a signal, a smoothing circuit for obtaining an average value around the pixel of interest using two different matrices, and a comparator for comparing the two average values,
This system performs binarization processing for classifying images in a document.

FIG. 72 shows a block diagram of the processing method of this embodiment, and FIG. 73 is a drawing showing an image reading section of a digital copying apparatus using the processing of the invention.

First, when you press the copy start button (not shown), the reading unit 30l6 in FIG.
3 through the imaging optical system 3014 while illuminating the CCD
It forms an image on the sensor 3015, reads it, and moves in the direction of V.

Immediately send the signal read by the sensor 3015 to R,
G and B are separated into three colors. Separated color signal R
, G, and H are each subjected to shading correction 3002.
will be held. At this time, the sensor used for reading is the 7th sensor.
In the case of a linear array as shown in Figure 4 (a), the center pixel is set to Gre.
If en, the phases of Red and Blue pixels are shifted by A pixels each. For this reason, correction is performed as a means for aligning the read signal.

This suppresses positional deviation (phase deviation) between the three colors R, G, and B. In addition, due to the above color shift correction, R
, B, the frequency characteristics of the signals M T
Deterioration to 52.7% at 4 F/mm. Therefore, MTF correction is performed on the Green signal,
Balance R, G, and H. Next, R, G,
A luminance signal Y is created from the B signal based on NTSC conversion.

Y=0.3OR+0.59G+0.11B Emphasis processing in the main scanning direction is performed on this Y signal.

This signal is for increasing the contrast of the Y signal, and is also a signal for obtaining the average value calculated by a smoothing circuit, which will be described later.

In implementing this embodiment, the coefficients of this emphasis circuit are set as shown in FIG. 76.

The emphasized Y' signal is 5X5 with different matrix sizes.
The average value around the pixel of interest AVEI. Calculate AVE2. At this time, data α is added from an offset 3010 to the average value AVEI calculated by the smoothing circuit 3007. This is because enhancement processing picks up slight noise when reading the image, so taking this into account
This is to provide an offset of .

After that, comparator 3009 calculates AVEI (including offset)
Compare AVE2 with
white), and if it is small, it outputs an O (black) signal, and the 2 of the pixel of interest is
Perform value conversion.

This is because, as shown in FIG. 77, in the case of halftone images such as photographs, the Y' signal does not have a sharp change (high contrast) like that caused by characters, so the smoothing circuit 3007 and the smoothing circuit 3008 can When comparing the average values, no difference can be seen. As a result, a determination result of 255 (white) is obtained for the halftone image portion.

Furthermore, in areas other than the halftone image, the contrast increases due to the effect of the above-mentioned emphasis circuit, and the black and white pattern continues (FIG. 78).

In addition, as shown in FIG. 79, the emphasis processing is performed using color shift correction, M
It can also be set to be performed on R, G, and B signals after TF correction.

In addition, as shown in FIG.
It can also be performed on R, G, and B signals after TF correction and LOG conversion.

Furthermore, instead of the NTSC conversion circuit as the Y signal, R,
A smoothing circuit that calculates the average value of the G and B3 signals may be used.

As explained above, according to this embodiment, color-separated R,
A brightness signal Y is calculated from the G and B signals, an emphasis circuit is provided to perform emphasis processing on the brightness signal Y, and two matrices of different sizes are used for binarization to calculate the area around the pixel of interest. By calculating the average value and adding an offset amount to the average value in a large matrix, it is possible to accurately separate the solid density or halftone image part from the other part. This has the effect of being used as a criterion for image area separation.

〔Effect of the invention〕

As explained above, according to the present invention, it is possible to satisfactorily discriminate a character area from an image containing mixed characters. A circuit diagram of image processing according to an embodiment of the invention, FIG. 3 is a diagram showing a color reading sensor and drive pulses, FIG. 4 is a circuit diagram for generating ODRV 118a and EDRV 119a, and FIG. 5 is a diagram explaining black correction operation. , Figure 6 is a circuit diagram of shading correction, Figure 7 is a color conversion block diagram, Figure 8 is a color detection block diagram, Figure 9 is a block diagram of a color conversion circuit, and Figure 10 is a specific example of color conversion. Figure 11 is a diagram explaining logarithmic conversion, Figure 12 is a circuit diagram of the color correction circuit, Figure 13 is a diagram showing unnecessary transmission areas of the filter, Figure 14 is a diagram showing the unnecessary transmission area of the filter.
The figure shows unnecessary absorption components of the filter. 15 is a circuit diagram of a character image area separation circuit, FIG. 16 is a diagram explaining the concept of contour regeneration, FIG. 17 is a diagram explaining the concept of contour regeneration, and FIG. 18 is a diagram explaining the concept of contour regeneration. Regeneration circuit diagram, Fig. 19 is a contour regeneration circuit diagram, Fig. 20 is a timing chart of ENI and EN2, Fig. 2
Figure 1 is a block diagram of the character image correction section, Figure 22 is an explanatory diagram of addition/subtraction processing, Figure 23 is a switching signal generation circuit diagram, Figure 24 is a circuit diagram of color residual removal processing, and Figure 25 is color residual removal processing. , Figure 26 is a diagram showing edge emphasis, Figure 27 is a diagram showing smoothing, Figure 28 is a diagram explaining processing and modification processing using binary signals, Figure 29 is a diagram explaining text, Figure 30 is a block diagram of the image editing circuit, Figure 31 is a diagram showing texture processing, Figure 32 is a circuit diagram of texture processing, Figure 33 is a diagram of mosaic, scaling, and tapering processing. A circuit diagram, FIG. 34 is a circuit diagram of mosaic processing, FIG. 35 is a diagram explaining mosaic processing, etc., FIG. 36 is a circuit diagram of the line memory address control section, FIG. 37 is an explanatory diagram of the mask bit memory, Fig. 38 is a diagram showing addresses, Fig. 39 is a diagram showing a specific example of a mask, Fig. 40 is a circuit diagram of an address counter, Fig. 41 is a timing chart for enlargement and reduction, and Fig. 42 is a diagram for enlargement and reduction. Figure 43 is an explanatory diagram of the binarization circuit, Figure 44 is a timing chart of the address counter, Figure 45 is a diagram showing a concrete example of bitmap memory writing, Figure 46 is a diagram showing characters and images. Figure 47 is a diagram showing a specific example of synthesis, Figure 47 is a circuit diagram of distribution switching, Figure 48 is a diagram showing a specific example of a nonlinear mask, Figure 49 is a circuit diagram of a region signal generation circuit, and Figure 50 is a diagram of a region generated by a digitizer. Figure 51 is an interface circuit diagram with external equipment, Figure 52 is a selector truth table, Figure 53 is a diagram showing examples of rectangular areas and non-rectangular areas, Figure 54 is a diagram showing designation.
55 is a diagram explaining the procedure of color conversion operation, FIG. 56 is a diagram explaining the procedure of specifying the trimming area, FIG. 57 is a diagram explaining the procedure of specifying the trimming area, Figure 58 is a diagram showing the algorithm for specifying a circular area.
Figure 9 is a diagram showing the algorithm for specifying areas of ellipses and R rectangles, Figure 60 is an explanatory diagram of the operating procedure for character composition, Figure 61 is an explanatory diagram of the operating procedure for character composition, and Figure 62 is an illustration of the operation procedure for character composition. Fig. 63 is a diagram explaining the procedure of texture processing, Fig. 64 is a diagram explaining the procedure of mosaic processing, Fig. 65 is a diagram explaining the procedure of dinner mode operation, Fig. 66
Figure 67 is a diagram explaining the program memory operation procedure. Figure 68 is a diagram explaining the program memory operation procedure. Figure 69 is a diagram explaining the program memory registration algorithm. Figure 70 is a diagram showing the algorithm of the operation after calling the program memory; Figure 71 is a diagram showing the format of the recording table;
Figure 2 is a block diagram of the binarization process according to the second embodiment of the present invention, Figure 73 is a diagram showing the reading section of a digital copying machine using the present invention, and Figure 74 is a diagram of the one-dimensional array used for reading. Figure 75 is a diagram showing the pixel arrangement of CCD. Figure 75 is a diagram showing MTF changes due to color shift correction.
Figure 6 shows the coefficients in the emphasis circuit used in the present invention and their MTFs.
FIG. 77 is a diagram showing the read signal of a halftone image and a signal after smoothing. FIG. 78 is a diagram showing a read signal of a character image and a signal after smoothing. FIG. 79 is a diagram showing the present invention. FIG. 80 is a diagram showing a modification of the second embodiment of the present invention.

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Claims (3)

[Claims] (1) Means for calculating an average value of a first block pixel area centered on the pixel of interest; means for calculating an average value of a second block pixel area centered on the pixel of interest; said first block pixel An image processing device comprising: binarization means for binarizing the average value of the second block pixel region using the average value of the region as a threshold, and outputting the result as a binarized output of the pixel of interest. (2) further comprising means for adding a predetermined value to the first block pixel region, and using the addition result of the adding means as a threshold, the result of binarizing the average value of the second block pixel region is 2. The image processing apparatus according to claim 1, further comprising means for outputting a binarized pixel of interest. (3) Claim (1) characterized in that the first block pixel area is an M×M block, the second block pixel area is an N×N block, and M≧N.
, (2) The image processing device described in (2).