JPH02294885A - Image processor - Google Patents

Abstract

PURPOSE:To execute satisfactory contour extraction by extracting a contour signal based on the respective output signals of a first processing means, which executes thinning processing to an input image, and a second processing means to execute thickening processing. CONSTITUTION:For the thinning processing, 1 bit data of L1-L17, which are delayed for each line by FIFO (fast-in, fast-out) memories 7001 and 7002, execute AND in an AND circuit 7003 and as a result, the thinning processing is executed in 17X17 masks. For the thickening processing, the respective 1 bit data of the L1-L17, which are delayed for each line by FIFO memories 8001 and 8002, execute OR in an OR circuit 8003 and as a result, the thickening processing is executed in the 17X17 masks. Namely, since a means to input image data, the first processing means to execute the thinning processing to the input image and the second processing means to execute the thickening processing are provided, image area discrimination can be securely executed without being affected by a noise, etc. Thus, image separation can be accurately executed to the image where a character is mixed.

Description

[Detailed description of the invention]

[Industrial Application Field] The present invention relates to an image processing device that digitally processes an input image and performs various image processing on the input image. [Prior Art] In recent years, digital color copying machines have become widely used, which separate color originals into colors, read each pixel, digitally process the read image data, and output it to a color printer to produce digital color hard copies. It is being done. This type of device has the advantage of being able to process image data digitally, so it is possible to move the image output position (
Fig. 75(a)), extracting a desired image area (Fig. 75(b)), converting only a certain color within the desired area (Fig. 75(C)), and storing the image in memory. It has become possible to perform various image processing such as inserting written characters and images into a reflective original (FIG. 75(d)), and its application in the field of so-called color copying is expanding. Therefore, by combining various functions, it has become possible to easily apply it to color proposals, advertising posters, promotional materials, design drawings, etc. On the other hand, for color reflective originals, the letters look more like letters.
There is a growing demand for images to look more like real images, and in response to this, image area separation is used to separate the text and image areas.
High-resolution processing is applied to the text portion, particularly black characters are printed in a single black color, while high-gradation processing is applied to the image portion. [Problems to be solved by the invention] However, in the conventional example described above, Labrasian processing was performed and contour extraction and character area determination were performed based on the results, which resulted in disadvantages such as ■ being susceptible to noise; and ■ increasing the circuit scale. There were many false positives. SUMMARY OF THE INVENTION Therefore, it is an object of the present invention to provide an image processing device that can eliminate the above-mentioned drawbacks and perform good contour extraction. [Means and operations for solving the problems] In order to solve the above problems, the image processing apparatus of the present invention includes a means for inputting image data, a first processing means for performing thinning processing on the input image, a second processing means for performing thickening processing on the input image; a means for extracting a contour signal based on the output signal of the first processing means and the output signal of the second processing means;
It is characterized by having the following. In the above configuration, the first processing means performs thinning processing on the human-powered image data, and the second processing means performs fattening processing on the input image data. The extraction means extracts a contour signal based on the output signals of the first and second processing means. (The following is a blank space) [Example] The present invention will be described in detail below with reference to the drawings. FIG. 1 shows an example of a schematic internal configuration of a digital color image processing system according to the present invention. As shown in the figure, this system includes a digital color image reading device (hereinafter referred to as color league) 1 at the top and a digital color image printing device (hereinafter referred to as color printer) 2 at the bottom. This color reader l has color separation means and C
A photoelectric conversion element such as a CD reads the color image information of the original for each color and converts it into an electrical digital image signal. Further, the color printer 2 is an electrophotographic laser beam color printer that reproduces a color image in each color according to the digital image signal, and records the image by transferring it to recording paper multiple times in the form of digital dots. First, an overview of the color reader I will be explained. 3 is a document, 4 is a platen glass on which the document is placed, and 5 is a lens for condensing the reflected light image from the document exposed and scanned by a halogen exposure lamp 1O, and inputting the image to a 1-magnification full-power color sensor 6. It is a door array lens, 5, 6,
7. 10 as a document scanning unit 11 performs exposure scanning in the direction of arrow AI. The color separation image signals read every line without exposure scanning are amplified to a predetermined voltage by the sensor output signal amplification circuit 7, and then inputted to a video processing unit to be described later via a signal line 501, where they are processed. . Details will be described later. 501 is a coaxial cable for ensuring faithful transmission of signals. A signal 502 is a signal line that supplies drive pulses for the same-magnification full-color sensor 6, and all necessary drive pulses are generated within the video processing unit 1-12. Reference numeral 8.9 denotes a white plate and a black plate for white level correction and black level correction of image signals, which will be described later. By irradiating them with a halogen exposure lamp 1O, a signal level of a predetermined density can be obtained, and the video signal white level correction,
Used for black level correction. l3 is a control unit with a microcomputer, which is connected to the bus 50
8, the display on the operation panel 20, key manual control, and control of the video processing unit 12; position sensors Sl, S2 detect the position of the original scanning unit 11 via signal lines 509, 510; Stepping motor drive circuit control that pulse-drives the stepping motor 14 to move the halogen exposure lamp 10 via the signal line 504, ON/OFF control of the halogen exposure lamp 10 by the exposure lamp driver, light 1 control, via the signal line 505. It controls all parts of the color reader part 1, such as the digitizer l6, internal keys, and display unit. The color image signal read by the above-mentioned exposure scanning unit 11 during original exposure scanning is sent to the video processing unit l via the amplifier circuit 7 and the signal line 501.
2, undergoes various processes described below within this unit 12, and is sent to the printer part 2 via the interface circuit 56. Next, an outline of the color printer 2 will be explained. 711 is a scanner, a laser output unit that converts the image signal from the color reader l into an optical signal, and a polyhedron (for example, an octahedron).
polygon mirror 712, a motor (not shown) for rotating this mirror 712, and an f/θ lens (imaging lens)
713 etc. 714 is a reflecting mirror that changes the optical path of the laser beam, and 715 is a photosensitive drum. The laser beam emitted from the laser output section is reflected by a polygon mirror 712, passes through a lens 713 and a mirror 714, and linearly scans (raster scan) the surface of a photosensitive drum 715, forming a latent image corresponding to the original image. do. In addition, 711 is a primary charger, 718 is a full exposure lamp,
723 is a cleaner section that collects residual toner that has not been transferred; 724 is a pre-transfer charger; these members are arranged around the photosensitive drum 715. 726 is a developing unit that develops the electrostatic latent image formed on the surface of the photosensitive drum 715 by laser exposure, and 731Y, 731M, 731C, and 7318k are developing sleeves that directly develop the photosensitive drum 715;
0Y, 730M, 730C, 7308k hold spare toner (toner hopper), 732 is a screw for transporting developer, and these sleeves 731Y~
7318k, toner hoppers 730Y to 7308k, and the screw 732 constitute a developing unit 726, and these members are arranged around the rotation axis P of the developing unit. For example, when forming a yellow toner image, develop the yellow toner at the position shown in this diagram.
When forming a magenta toner image, the developer unit 7
26 is rotated around the axis P in the figure, and the developing sleeve 731M in the magenta developing device is disposed at a position in contact with the photoreceptor 715. Cyan and black development work in the same way. Further, 716 is a transfer drum that transfers the toner image formed on the photosensitive drum 715 onto paper, 7l9 is an actuator plate for detecting the moving position of the transfer drum 716, and 720 is a drum that is in close proximity to this actuator plate 719. 725 is a transfer drum cleaner, 727 is a paper pressing roller, 728 is a static eliminator, and 729 is a transfer charger. These members 71
9, 720, 725, 727, and 729 are arranged around the transfer roller 716. On the other hand, 735 and 736 are paper feed cassettes that store paper (paper sheets), and 737 and 738 are cassettes 735 and 7.
Paper feed rollers 739, 740 that feed paper from 36
, 741 are timing rollers that take the timing of paper feeding and conveyance, and the paper fed and conveyed via these is guided by a paper guide 749 and wound around the transfer drum 716 while its leading edge is carried by a gripper (to be described later). Shift to image formation process. Further, 550 is a drum rotation motor, and the photosensitive drum 7
15 and a transfer drum 716 are rotated in synchronization. 750 is a peeling claw that removes the paper from the transfer drum 716 after the image forming process is completed, 742 is a conveyor belt that conveys the removed paper, and 743 is a conveyor belt that is conveyed by the conveyor belt 742. The image fixing unit 743 is an image fixing unit that fixes the paper that has been received. Two image processing circuits according to the present invention will be described in detail with reference to FIG. 2 and subsequent figures. This circuit exposes a full-color original to an illumination source such as a halogen lamp or fluorescent lamp (not shown), captures a reflected color image with a color image sensor such as COD,
The obtained analog image signal is digitized using an A/D converter, etc., and the digitized full-color image signal is processed and outputted to a thermal transfer color printer, inkjet color printer, laser beam color printer, etc. (not shown) to produce a color image. a color image copying device that obtains
Alternatively, input a pre-digitized color image signal from a computer, other color image reading device, or color image transmitting device, perform processing such as compositing, and output it to the color printer mentioned above. applicable. The document is first irradiated by an exposure lamp (not shown), and the reflected light is separated into colors for each image and read by a color reading sensor 500a, and amplified to a predetermined level by an amplifier circuit 501a. 533a is a COD driver that supplies pulse signals for driving the color reading sensor, and the necessary pulse source is generated by a system control pulse generator 534a. FIG. 3 shows the color reading sensor and drive pulses. Figure 3(a) shows the color reading sensor used in this example, which reads by dividing the main scanning direction into 5 parts.
．． With 5 μm as one pixel (4 dots/inch (hereinafter referred to as dpi)), 1024 pixels, that is, 1 pixel as shown in the figure, are divided into three by G, B, and R in the main scanning direction, so the total effective IO is 24 x 323072. It has the number of pixels. On the other hand, each of the chips 58 to 62 is formed on the same ceramic substrate, and the chips 1, 3, . The 5th (58a, 60a, 62a) are on the same line LA, and the 2.4th is 4 lines away from LA (63.5 μm x 4
254 μm) on the line LB, and scans in the direction of the arrow AL when reading the document. Of each 5 CCDs! , 3. The fifth is the drive pulse group ODRV118a, and the second and fourth are the EDRVll9a.
are driven independently and synchronously. ODRV118al: Includes OOIA, 002A, O
RS and EDRV119al: EOIA, EO2 included
A and ERS are a charge transfer clock and a charge reset panorez in each sensor, respectively; l, 3. Due to mutual interference and noise limitations between the fifth and second and fourth signals, they are generated in complete synchronization so that there is no jitter between them. Therefore, these pulses are generated by one reference oscillation source OSC558a.
(Figure 2). Figure 4(a) shows ODRVII8a, EDRV119a
FIG. 4(b) is a timing chart of the circuit block that generates the pulse generator 534a of FIG. 2, which is included in the system control pulse generator 534a of FIG. Clock K obtained by dividing the original clock CLKO generated by a single OSC558a
Ol35a is a clock that generates reference signals SYNC2 and SYNC3 that determine the timing of ODRV and EDRV (7) generation, and SYNC2 and SYNC3 are the settings for the resettable counters 64a and 65a, which are set by the signal line 22 connected to the CPU bus. The output timing is determined according to the value, and SYNC2 and SYNC3 are connected to the frequency divider 66.
a, 67a and drive pulse generators 68a, 6
Initialize 9a. In other words, with HSYNC118 input to this block as a reference, all oscillation source OSC
The respective pulse groups of ODRV1+8a and EDRV119a, which are generated by the CLKO output from 558a and the divided clock which are all synchronously generated, are obtained as synchronous signals with no jitter at all, and the sensor It is possible to prevent signal disturbance due to interference between Here, the sensor drive panores ODRVl18al and 1, 3. which were obtained in synchronization with each other. 5th sensor 58
The EDRV 119a is supplied to the second and fourth sensors 59a, 61a, and each sensor 5 8
Video signals Vl-V5 are independently output from a 5 9 a 60 a, 61 a, and 62 a in synchronization with the drive pulse, and are predetermined by independent amplifier circuits 501-1 to 501-5 for each channel shown in FIG. Figure 3 (b)
(7) OOS +29a (7) Vl at timing
, V3, V5 become V2 at EOS134a(7) timing.
, V4 are sent out and input to the video image processing circuit. The color image signals obtained by dividing the original input into the video image processing circuit into 5 parts and reading them are processed into G (green), B (blue), R ( Therefore, after S/H, the signal is processed in 3×5=15 systems. Analog color samples and holds for each color R, G, and B are processed by the S/H circuit 502a. The image signal is sent to the next stage A/
The D conversion circuit 503a digitizes each of channels 1 to 5, and outputs each channel of 1 to 5 independently in parallel to the next stage. Now, in this embodiment, as described above, 4 lines (63.
5 μm x 4 = 254 μm) in the sub-scanning direction,
In addition, since the document is read using five staggered sensors divided into five areas in the main scanning direction, the reading positions of channels 2 and 4, which are being scanned in advance, and the remaining channels 1, 3, and 5 are shifted. Therefore, in order to connect this correctly, a shift correction circuit 504a equipped with memory for multiple lines is used to
We are correcting that discrepancy. Next, using FIG. 5(a), the black correction/white correction circuit 506
The black correction operation in a will be explained. As shown in FIG. 5(b), the black level outputs of channels 1 to 5 vary greatly between chips and between pixels when the light input to the sensor is very small. If this is output as is and an image is output, the data portion of the image will be uneven or uneven. Therefore, it is necessary to correct the output variation in the black portion, and this correction is performed using a circuit as shown in FIG. 5(a). Prior to the original reading operation, the original scanning unit is moved to the position of a black plate having a uniform density, which is placed in a non-image area at the tip of the original table, the halogen is turned on, and a black level image signal is input to this circuit. Regarding the blue signal BIN, in order to store one line of this image data in the black level RAM78a,
Select A with the selector 82a (■), close the gate 80a (■), and open 81a. That is, the data line is 151a
−+ 152a −+ Connected to 153a, while R
The output 1 54a of the address counter 84a which is initialized by HSYNC and counts VCLK should be input to the address 1 55a of AM78a.
■ for a is output, and the black level signal for l lines is stored in RAM78a (hereinafter referred to as black reference value capture mode). When reading an image, the RAM 78a is in a data read mode, and each line and l pixels are read out and input to the B input of the subtracter 79a via the data line 153a→157a path. That is, at this time, game 1-81a is closed (
■), 80a opens (■). In addition, the selector 86a is
This becomes the output. Therefore, for example, in the case of a blue signal, the black correction circuit output 156a is BI N (i) DK (i)=B OUT (i
) (called black correction mode). Similarly, green GIN and red RIN are also 77aG and 77aR.
Similar control is performed by. In addition, the control lines of each selector gate for this control
, ■, ■, ■ are performed under CPU control by latch 85a assigned as I/O of CPU 22 (FIG. 2). Note that by selecting B from the selectors 82a, 83a, and 86a, the CPU 22 selects R A M 7 8
a becomes accessible. Next, white level correction (shading correction) in the black correction/white correction circuit 506a will be explained with reference to FIG. White level correction corrects variations in sensitivity of the illumination system, optical system, and sensor based on white data obtained when the document scanning unit is moved to the position of a uniform white plate and irradiated. The basic circuit configuration is shown in FIG. 6(a). The basic circuit configuration is shown in Figure 5 (
This is the same as a), but the only difference is that the subtracter 79a performs the correction in the black correction, whereas the multiplier 79'a is used in the white correction, so a description of the same parts will be omitted. CCD (500a) for reading originals during color correction
When R A M78 is at the reading position (home position) of a uniform white board, that is, before a copying operation or a reading operation, an exposure lamp (not shown) is turned on and the uniform white level image data is corrected by one line. 'a'. For example, if it has an A4 longitudinal width in the main scanning direction, 16 pef/mm is 16 x 297 mm = 475
2 pixels, that is, the capacity of at least RAM is 475
As shown in FIG. 6(b), if the i-th pixel white board data Wi (i=1 to 4752)
8'a stores data for the white plate for each pixel, as shown in FIG. 6(C). On the other hand, for Wi, the read value Di of the normal image of the i-th pixel is corrected data Do=DiXFFH/Wi
It should be. Therefore, from the CPU 22, the latch 85
Gate 80 for ′a■′,■' , ■' l■′
'a, 81' Open a and select selector 82'
a, 83' a, 86' A is output so that B is selected, and the RAM 78'a is made accessible to the CPU. Next, in the procedure shown in FIG. 6(d), the CPU 22 performs data replacement by sequentially calculating FFH/Wo for the first pixel to Vo, FF/W for W, and so on. When finished for the blue component of the color component image (Figure 6 (
d) Step B) Similarly, green component (Step G)
, red component (Step R), and then Do=DiXFF H/ for the input original image data Di.
Gate 80'a is opened so that Wi is output (■'),
81' a is closed (■'), selector 83' a, 86
'a is selected as A, coefficient data FF read from RAM 78'a, /Wi is signal line 153a-''157
a, is multiplied by the original image data 151a input from one side, and is output. ? As mentioned above, the black level and white level are corrected based on various factors such as the black level sensitivity of the image input system, the dark current variation of the CCD, the sensitivity variation between each sensor, the optical system light amount variation, and the white level sensitivity. Image data B uniformly corrected for each color, both white and black, in the scanning direction. , ■101, Go, T102, RooTl03 are obtained. The white and black level-corrected color separation image data obtained here are processed by detecting pixels on the image having a specific color density or a specific color ratio according to instructions from an operation unit (not shown). The data is sent to a color conversion circuit B which converts the data into another color density or color ratio specified by the unit. Color Conversion> FIG. 7 is a block diagram of color conversion (gradation color conversion and density color conversion). The circuit in FIG. 7 uses an 8-bit color separation signal R IN
+ A color detection unit 5b for determining an arbitrary color set in the register 6b by the CPU 20 for G INI B IN (lb to 3b), an area signal Ar4b for performing color detection and color conversion for a plurality of locations, ? A line memory lOb that performs processing to spread a signal indicating that the color is a specific color (hereinafter referred to as a hit signal) outputted by the color detection unit in the main scanning and sub-scanning directions (in the example of FIG. 7, only the sub-scanning direction).
-1lb, OR gate l2b, expanded hit signal 3
4b and non-rectangular signals (including rectangular) Color conversion enable signal 33b generated from BHi 27b, enable signal 33b and input color separation data (R IN+ GIN+
BIN 1b-3b), line memory 13b-16b for synchronizing area signal Ar4, delay circuit 1
7b to 20b1 enable signal 33b, synchronized color separation data (RIN'lGIN,
B IN' 2lb to 23b), area signal Ar
24b and the CPU 20, the color conversion unit 25b performs color conversion based on the color data after color conversion set in the register 26b.1 Color separation data (R
out. G OUT , B OLJT 2
8b-30b), ROIJT + GOUT +
Hit signal H output in synchronization with BOU■. U■3lb
It consists of Next, we will outline the algorithms for gradation color determination and gradation color conversion. Here, gradation color judgment and gradation color conversion mean that when performing color judgment and color conversion, color conversion should be performed by saving density values for colors of the same hue. It is to perform color conversion. It is known that for the same color (certain hue), for example, the ratios of the red signal R, the green signal G, and the blue signal B1 are equal. Therefore, data M of one of the colors to be converted (maximum value color, hereinafter referred to as principal color) is selected, and the ratio between it and the data of the other two colors is determined. For example, and the input data R+
, G+, Bl, M, X γ1 ≦
R1≦M, X γ2However, α1, β,, γ1≦1 α2. A pixel for which β2, γ2 ≧1 is satisfied is determined to be a pixel to be color-converted. Furthermore, the data after color conversion (R21 G21 B2) is also
Data M of the main color (in this case, the maximum value color) within that data
2 and the data of the other two colors. For example, when G2 is the main color, it is M2-62, and for the main color M of input data, if the data is a color conversion pixel, if it is not a color conversion pixel, then (R+, G+, B+ )
Output. As a result, all parts of the same hue with gradation are detected,
It becomes possible to produce color conversion data according to gradation. FIG. 8 is a block diagram showing an example of a color determination circuit. This part is a part that detects pixels to be color-converted. In this figure, 50b is R,,J bl,G,
b2, B, N b3 is a smoothing section that smooths the input data, 5lb is one of the outputs of the smoothing section (
selector 52bR, 52bo52b8 for selecting the main color)
are the output of selector 5lb and the fixed value R. , selector for selecting one of GoBo, 54bR, 54bo54b8
is an OR gate, 63b, 64b R, 64b
664b8 are area signals ArlO, Ar
Selector 5lb, 52bR, 52bo, based on 20
a selector for setting a select signal to 52b8;
56bR, 56b,, 56b8 and 57bR, 57
b,, 57bB are multipliers that calculate the respective upper and lower limits. Further, upper limit ratio registers 58b R, 58bo, 58b B, and lower limit ratio registers 59bR, 59b are set by the CPU 20, respectively. , 59bB can each set data for color detection for a plurality of areas based on the area signal Ar30. Here, ArlO, Ar20, and Ar30 are signals created based on Ar4b in Fig. 7, and each has the required number of stages of D.
Contains F/F. Also, 6lb is an AND gate,
62b is an OR gate, and 67b is a register. Next, we will explain the actual movement. R,N blG,,l
One of the data R' and G'B' obtained by smoothing l b2 and BIN b3, respectively, is sent to the CPU 2.
The selector 5lb is set by the select signal S1 set to 0.
Select to select the main color data. Here, C.P.
U20 sets different data A and B in registers 65b and 66b, and selector 63b selects either A or B according to the ArlO signal and inputs it to selector 5lb as an S1 signal. In this way, prepare two registers, 65b and 66b,
Input different data to A and H of selector 63b,
With the configuration in which the area signal ArlO selects one of them, separate color detection can be performed for a plurality of areas. This area signal ArlO may be a signal for not only a rectangular area but also a non-rectangular area. Next selector 52bR, 52b. ．． In 52bB, CP
R set by U20. , Go, Bo are selectors 5lb
Any of the raw color data selected in is selected by a select signal generated from the outputs 53ba to 53bc of the decoder 53b and the fixed color mode signal s2. Note that the selectors 64bR, 64bo, and 64b8 are
By selecting either A or H according to the area signal Ar20, it is possible to detect different colors in a plurality of areas, as in the case of the selector 63b. Here, Ro, Go, and Bo are selected when the main color is in conventional color conversion (fixed color mode) and gradation color determination, and the main color data is selected when it is a color other than the main color in gradation color conversion. . Note that the operator can freely select between fixed color determination and gradation color determination from the operation section. Alternatively, it is also possible to change it by software using color data (color data before color conversion) input from an input device such as a digitizer. These selectors 52bR, 52b(,, 52
b8 output and the upper limit ratio registers 58bR, 58bc.b8 set by the CPU 20. 58b8, lower limit ratio registers 59bR, 59bG, and 59b8, the upper and lower limit values of R'G' and B' are input to multipliers 56b, 56bG, 56b8, and 57bR, respectively.
, 57b, , 57b8 and set as upper and lower limit values in the window comparators 60bR+60bo and 60b8. Window converter 60bR, 60bG,
At 60b8, it is determined by AND gate 6lb whether the data of the main color falls within a certain range and the two colors other than the main color fall within a certain range. The register 67b can set "1" regardless of the determination signal by the enable signal 68b of the determination section. In that case, the color to be converted exists in the portion marked with "1". The above configuration enables fixed color determination or gradation color determination for a plurality of areas. FIG. 9 is a block diagram of an example of a color conversion circuit. ? The circuit selects the color-converted signal or the original signal based on the output 7b of the color determining section 5b. In FIG. 9, the color conversion unit 25b includes a selector lllb, registers II2bR+, 112bR■, which set the respective ratios of the converted color to the principal color data (maximum value here),
112bo,, 112b,2, ll2b8
, ll2bB■, multiplier 113bR, 113b,,
113b8, selector l14bR, l14b,,1
14b8, selector 115bR, l15bo, 115b
8. AND gate 32b1 FIG. 7 Area signal Ar' 2
Ar50, Ar60, Ar70 generated based on 4
The data set by the CPU 20 by the selector I
llb, multiplier 113bR, 113bo, ll3b8,
Selector 1] Set to 4bR, 114bo, 114b8 Selector 117b, 112bR, 112b6,
112bB, 116bR, 116bo, 11
6b8 and a delay circuit 118b. Next, we will explain the actual movement. The selector lllb receives input signals R I N 2lb,
One (primary color) of G, N' 22b, B, N' 23b is selected according to the selection signal S5. Here, the signal S5 indicates that the area signal Ar40 switches the selector l17b to A, for the two data set by the CPU20.
This occurs by selecting either B. In this way, color conversion processing for multiple areas becomes possible. The signal selected by selector lllb is sent to multiplier 113.
Multiplication with the register value set by the CPU 20 is performed in bR, ll3b, , 113b8. Here again, the area signal Ar50 has two register values 112
bR, -+12bR2, l12b,, -112b
,2,112b8,・1l2b. 3. By selecting , respectively, using the selectors tt2bR, 112b6, and 112b8, different color conversion processing can be performed for a plurality of areas. Next, selectors 114bR, 114bo, 114
At b8, the result of multiplication and the two fixed values set by the CPU 20 Ro' ・Ro Go -GO BO' ・BO
Area signal A'70 selector 116bR,
One of the fixed values selected in 116b, , 116b8 is selected by mode signal S6. Is this also a mode? The signal S6 is selected by the area signal Ar60 in the same manner as S5. Finally, using the select signal 88' in selectors l15bR, l15bo, and 115b8, RINGIN,
BIN (RIN'. GIN, BIN delayed and timing adjusted) and selector 114bR,
Either the output of ll4b6 or 114bB is selected and output as ROUT+GOU■+BOUT. Also hit signal I]. U■ is also R. 0■, GOIJT+
It is output in synchronization with BOtjT. Here, the selector signal SB' is a delay product obtained by ANDing the color determination result 34b and the color conversion enable signal BHi34b. If a non-rectangular enable signal such as the dotted line in FIG. 10 is input as the B H i signal, color conversion processing can be performed on a non-rectangular area. In this case, the area signal is an area like the one-dot chain line, that is, the uppermost left corner (Fig. 10a) determined from the dotted line.
), top right (Figure 10b), bottom left (Figure 10C)
, is generated by the coordinates of the leftmost position (Fig. 10d). Further, the non-rectangular area signal B H i is input from an input device such as a digitizer. When performing color conversion using this non-rectangular enable signal,
Since the enabled area can be specified along the boundary of the area to be converted, the threshold for color detection can be expanded compared to conventional color conversion using rectangles. Therefore, the detection ability is further improved, and an output image subjected to gradation color conversion with high accuracy can be obtained. From the above, color conversion with brightness according to the main color of the color judgment unit 5b (for example, when converting red to blue, light red is converted to light blue and dark red is converted to dark blue) or fixed value color conversion You can freely perform any of the following for multiple areas. Furthermore, as will be described later, the hit signal H. Mosaic processing based on UT only for specific color areas (non-rectangular or rectangular),
Texture processing, l/rimming processing, masking processing, etc. can be performed. Then, as shown in FIG. 2, the output 103 of the color conversion circuit B,
104 and 105 are a logarithmic conversion circuit C for converting image data proportional to reflectance into density data, a character image area separation circuit ■ for determining character areas, halftone areas, and halftone areas on a document; The system is sent to an external device interface M for communicating data with external devices via cables 135, 136, 137. Next, the color image data proportional to the input light amount is
The signal is input to a logarithmic conversion circuit C (FIG. 2) which performs processing to match the luminosity characteristics of the human eye. Here, the image sources that are converted as much as white = OOH + black FF, and are further input to the image reading sensor, such as a normal reflective original and a transparent original such as a film projector, and even the same transparent original as negative film, positive film or Since the input gamma characteristics differ depending on the sensitivity of the film and the exposure condition,
As shown in (b), there are a plurality of LUTs (look-up tables) for logarithmic conversion, which are used depending on the purpose. Switching is performed by signal lines 1gO, lgl, and Ig2, and is performed by inputting an instruction from an operation unit or the like as an I/O port of the CPU 22 (FIG. 2). Here each B
The data output for , G, and R corresponds to the density value of the output image, and the data output for each signal of B (blue), G (green), and R (red) corresponds to the Y (yellow) signal. , M (magenta), and C (cyan), subsequent image data will be associated with yellow, magenta, and cyan. Next, the color correction circuit D performs color correction as described below on each color component image data from the original image obtained by logarithmic conversion, that is, yellow component, magenta component, and cyan component. As shown in Fig. 13, the spectral characteristics of the color separation filters arranged for each pixel in the color reading sensor have unnecessary transmission areas such as the shaded areas, and on the other hand, for example, the color transferred to the transfer paper Toner (Y, M, C)
It is also well known that the fluorophore also has unnecessary absorption components as shown in Figure 14. Therefore, each color component image data Yi, Mi,
Masking correction is well known in which color correction is performed by calculating a linear equation for each color for Ci. Furthermore, by Yi, Mi, Ci, Min (Yi, Mi, Ci) (Yi,
Mi, Ci (minimum value of Mi, Ci) is calculated, this is used as a smear (black), and then black toner is added (smear removal), and undercolor removal is performed to reduce the amount of each coloring material added according to the added black component. (OCR) operations are also performed. Figure 12(a)
A color correction circuit D that performs masking, smearing, and UCR
The circuit configuration is shown below. The characteristics of this configuration are: ■ It has two masking matrices and can be switched at high speed with one signal line "I/O". ■ It has one signal line "I/O" with and without UCR. /O" can be used to switch at high speed. (2) It has two circuits for determining the sumi m, and can be switched at high speed using "I/O." First, prior to image reading, a desired first matrix coefficient M1 and a desired second matrix coefficient M2 are set via a bus connected to the CPU 22. In this example, M1 is connected to resistors 87d to 95d, and M2 is connected to resistors 966 to 104.
It is set to d. Also, 111d to 122d, 135d, 131d, 13
6d is a selector, and when S terminal = “B”, A
Select , and select B when “O”. Therefore matrix M
, when selecting the matrix M2, the switching signal MAREA364 is set to "o゜゜" when selecting the matrix M2. Further, 123d is a selector and a selection signal C. ,C
, (366d), 367d), Figure 12 (
Outputs a, b, and c are obtained based on the truth table of b). Selection signal C. , C1 and C2 correspond to the color signals to be output, for example, in the order of Y, M, C, Bk (C2
．． CI, CO) = (0, 0. 0), (0
, 0. 1), (0, l, O), (1,
0. 0), and further as a monochrome signal (0, 1
, l), a desired color-corrected color signal is obtained. Now (Co, c,, C2) (0, 0.
0) and MAREA-“l”, selector 12
3d output (a, b, c), Resisku 87d
, 88d, 89d, therefore (ay+, −
bM+, Cc+) are output. On the other hand, the input signal Yi,
Min from Mi, Ci (Yi, Mi, Ci)
The black component signal 374d calculated as =k is 137d
It undergoes a linear transformation of Y=ax-b (a, b are constants) at , and is input to the B inputs of subtracters 124d, 125d, and 126d. Each subtractor! 24d-126d, Y=Yi-(ak-b), M=
M i − (ak − b), C =
C i - (ak - b) is calculated and sent to multipliers 127d, 128dl2 for masking calculations via signal lines 377d, 378d, 379d.
9d. The multipliers 127d, 128d, and 129d each have eight inputs (a y+ , − b Ml
, −C c+ ), and the B input has the above-mentioned [Yi
- (ak-b), Mi - (ak-b), Ci
- (ak-b)) = [:Yi, Mi,
Ci] is input, so as is clear from the figure,
Output D. For UT, the condition of C2=0 (Y or M
Or C) and YOU Ding? iX (av+) +Mi
X (-bMe) +cix (-Cc+) is obtained, and yellow image data that has been subjected to masking color correction and undercolor removal processing is obtained. Similarly, MO U1 = YiX(-aY2)+MiX(-bM2
)+CiX(-CC2)CO U 7 =YiX(
-av 3)+MiX (1b+M3) 10CiX
(-CC3) is D. Output to U■. Color selection is
According to the order of output to the color printer (Co
, CC2) according to the table in FIG. 12(b).
2. Registers l05d-107d,
+08d to +110d are registers for monochrome image formation, and based on the same principle as the masking color correction described above,
MONO=k, Yi+. It is obtained by weighted addition for each color using f', Mi+ml Ci. In addition, when outputting Bk, C2 (368) is input as a switching signal to the selector 131d, and C2-1, therefore, the primary converter 133d undergoes a primary conversion such that Y=cx-d, and the signal is output from the selector 131d. . Also, Bk
MJ110 is a black component signal output to the outline of a black character based on the output of a character image area separation circuit I, which will be described later. Color switching signal C. C, , C2' 366 to 368 are the CPU bus 22
MARE
A364 is output from the area signal generation circuit 364. The gate circuits 150d to 153d output a signal C when DHi-“L” is determined by a non-rectangular area signal DHil22 read from a binary memory circuit (bitmap memory) L537, which will be described later. ,C,,C2 −“l, 1, O”
This is a circuit that controls so that data for m o n o images is automatically output. <Character image area separation circuit> Next, the character image area separation circuit ■ uses the read image data to determine whether the image data is a character or an image, and whether it is chromatic or achromatic. This is a circuit that determines whether The flow of the process will be explained using FIG. 15. Red (R) 103, green (G) 104, blue (B) input from color conversion B to character image area separation circuit ■
)l{)5 is the minimum value detection circuit M, N(R, G, B)1
011 and maximum value detection circuit Max (R, G,
B) Input to 1021. In each block, the maximum value and minimum value are selected from the three types of input luminance signals R, G, and B. A subtraction circuit 1041 calculates the difference between the selected signals. The difference is large,
In other words, if the input R, G, and B are not uniform, this indicates that the signal is not an achromatic signal that indicates black and white, but is a chromatic color that is biased towards some color. Naturally, if this value is small, it means that the R, G, and B signals are at approximately the same level, and it can be seen that the signal is an achromatic signal and not a signal that is biased towards any color. This difference signal is output to the delay circuit Q as a gray signal GR124. In addition, this difference is stored in register 111I by the CPU.
It is compared with a threshold value arbitrarily set in the comparator 1L2I, and the comparison result is output to the delay circuit Q as a gray determination signal GRBil26. These GR125, GR
After the signal of Bil26 is matched in phase with other signals in a delay circuit Q, it is input to a character image correction circuit E, which will be described later, and is used as a processing determination signal. The minimum value signal obtained by M, N (R, G, B) IOII is also input to the edge emphasis circuit 1031. The edge emphasis circuit performs the following calculation using the front and rear pixel data in the main scanning direction. Edge enhancement is performed. DOUT ・Image data Di after edge enhancement
: i-th pixel data Note that edge enhancement is not necessarily limited to the above method, and other known techniques may be used. The image signal edge-enhanced in the main scanning direction is then
The average value within the 3×3 window is calculated using a 5×5 average of 1091 and a 3×3 average of 1101. Line memories 1051 to 108I are delay memories in the sub-scanning direction for performing averaging processing. The 5×5 average value calculated by 1091 is then calculated by C, which is also not shown.
Offset values and adders 1151, 1191, 124 independently set in the offset section connected to PUBUS
It is added by I. The added 5×5 average value is the limiter
It is input to l13I, limiter 2 1181, and limiter 3 1231. Each limiter is connected to a CPU bus (not shown), and is configured so that a limiter value can be set independently. If the 5×5 average value is larger than the set limiter value, the output is clipped at the limiter value. The output signals from each limiter are transmitted to comparator l 1161 and comparator 2 1, respectively.
Second, it is input to comparator 3 1261. First, in converter 1 1161, limiter l 1
The output signal of 131 and the output from 3×3 average 1101 are compared. The output of the converted converter l 1161 is input to a delay circuit 1171 in order to match the phase with an output signal from a halftone area discriminating circuit 1221, which will be described later. This binarized signal has MT
In order to prevent distortion and skipping due to F, binarization is performed using the average value, and in order to prevent the halftone dots of the halftone image from being detected by binarization, the high frequency components of the halftone dot image are cut. , through a 3×3 low-pass filter. Next, the output signal of the converter 2 (121I) is binarized with the through image data to detect high frequency components of the image so that it can be discriminated by the halftone dot area discriminating circuit 122 in the subsequent stage. Since the halftone dot image is composed of a collection of dots, the halftone dot area discrimination circuit 122I detects the dots by confirming that they are dots from the direction of the edge and counting the number of dots around them. There is. A detailed explanation of the halftone area determination circuit 1221 will be omitted since it is not the gist of this patent. The results determined by the steel point region discriminating circuit in this way and the signal from the delay circuit 117 are used in an OR gate 129I.
After removing the erroneous judgment, the erroneous judgment removal circuit 130I removes the erroneous judgment and outputs it to the AND gate 132l. This false judgment removal circuit 1301 first narrows the image area of the binary signal to take advantage of the characteristics that characters, etc. have a wide area, and then take isolated image areas. . Specifically, for the center pixel xij, the surrounding 1 m
When even one pixel other than the image exists within the m-square area, the central pixel is determined to be outside the image. After removing the image area of the isolated point in this way, thickening processing is performed to restore the thin image area to its original size. Similarly, halftone discrimination circuit 1 22
The output of 1 is directly input to the erroneous determination removal circuit 1311, where thinning processing and thickening processing are performed. The mask size for the thinning process is the same as the mask size for the fattening process, or if the mask size for the fattening process is set larger, the judgment results when fattening will cross ing. Specifically, the false determination removal circuit 1301. 1311 and 17
After thinning with a mask of 17 pixels, further thinning is performed with a mask of 5×5, and then thickening processing is performed with a mask of 34×34 pixels. The output signal SCRN signal 127 from the misjudgment removal circuit 1311 is sent to a character image correction circuit E, which will be described later.
This is a discrimination signal for performing smoothing processing only in the halftone dot determination section and preventing moiré in the read image. Next, the output signal from the comparator 3 1261 is used to extract the outline of the human image signal in order to sharpen the characters at a later stage. The extraction method involves thinning and fattening the output of the binarized comparator 3 126I in 5 x 5 blocks, and contouring the difference area between the fattened signal and the thinned signal. shall be. The contour signal extracted by such a method is passed through a delay circuit 1281 in order to match the phase with the mask signal outputted from the erroneous judgment removal circuit 1301, and then an AND gate 132I converts the contour signal into an image with a mask signal. The contour signal in the determined portion is masked, and only the contour signal in the original character portion is output. The output from the AND gate 132■ is then output to a contour regenerating section 133■. <Contour regeneration section> The contour regeneration section 133■ performs processing to convert pixels that are not determined to be character contours into character contours based on information of surrounding pixels, and as a result, M j A r ] 2 4 is sent to the character image correction circuit E to perform the processing described later. Specifically, as shown in Figure 16, bold letters ((a) in the same figure)
, the character determination unit determines the dotted line part in (b) as a character and performs the processing described below.
Regarding C)), the character part becomes as shown in the dotted line part in FIG. 10(d), and if the processing described below is performed, it may become unsightly due to misjudgment. In order to prevent this, processing is performed to treat parts that are not determined as characters based on surrounding information. Specifically, by making the diagonal line part the character part, the character part becomes as shown in the dotted line part (e) in the same figure, which reduces misjudgments even for characters that are so thin that they are difficult to detect, leading to improved image quality. . FIG. 17 is a diagram showing how surrounding information is used to regenerate a pixel of interest into a character portion. (a) to (d) are 3 x 3 blocks, and when the vertical, horizontal, and diagonal directions of the pixel of interest are both text parts (both Sl and S2 are "bi"), the pixel of interest is set as the text part regardless of the information of the pixel of interest. On the other hand, (e) to (h) are 5 x 5 blocks, with the pixel of interest as the center, and both the vertical, horizontal, and diagonal directions are character parts (“l” in both Sl and S2) of the pixel of interest. The pixel of interest is treated as a character section regardless of the information on the pixel.By having this two-stage structure (multiple types of blocks), it is possible to deal with a wide range of errors.Figures 18 and 19 The figure shows a circuit for realizing the process shown in Fig. 17.The circuits shown in Figs. 18 and 19 include a line memory 164i = l67i, and a D / F I O 4 i
= 1 2 6 i , AND gates 1461 to 1531 and O for realizing FIGS. 17(a) to (h)
It is composed of an R gate 154i. Figure 17 (
The information of S, , S2 in a) to (h) is extracted. Furthermore, l 4 6 i-1 5 3 i is (a) ~ (h)
Registers corresponding to each process of
Enable and disable can be controlled independently by f52i. AND circuit 1 4 6 i to l 5 3 i and the 17th
The correspondence relationships in FIGS. (a) to (h) are as follows. Figure 20 shows line memory l 6 4 i-1 6 7
It is a timing chart of WE (ENI) and RE (EN2) of i. This means that ENI and EN2 appear at the same timing when the size is the same, or when it is enlarged (for example, from 200% to 300%).
%) causes WE to be written once in two thinned lines. This expands the size of FIGS. 17(a) to (h). This is because when enlarging, the information that enters here is an image enlarged only in the sub-scanning direction, so by increasing the size of (a) to (h), processing is performed using the same size image even when enlarging. I'm going to Character Image Correction Circuit> The character image correction circuit E performs the following processing on black characters, color characters, halftone images, and halftone images, respectively, based on the determination signal generated by the character image area separation circuit I described above. [Processing 1] Processing related to black characters (1-13 Signal Bk obtained by ink extraction as video
Using Mjll2 (1-2) Y, M, C data are multivalued achromatic chromaticity signals GR
125 or according to the set value. On the other hand, Bk
The data is added according to the multi-value achromatic chromaticity signal GR125 or the set value (1-3) Edge emphasis is performed (1-4) Black text is printed out at 400 lines (400 dpi) (1-5) Color Perform residual removal processing [Process 2] Process related to colored characters [2-1] Perform edge emphasis (2-2) Print out colored characters at 400 lines (400 dpi) [Process 3] Process related to halftone images (3-1) Smoothing to prevent moiré (main scan
[Processing 4] Processing related to halftone images [4-1] Enables selection of smoothing (two pixels at a time in the main scanning direction) or through. Next, a circuit that performs the above processing will be explained. FIG. 21 is a block diagram of the character image correction section E. The circuit of FIG. 21 uses the video input signal 111 or BkM
a selector 6e that selects 112, an AND gate 6e that generates a signal that controls the selector, a block 16e that performs color residual removal processing (described later), an AND gate 1/16e that generates an enable signal for the same processing, and a GR signal 125.
and a multiplier 9e that multiplies the I/O port setting value 10e.
', selector lle that selects the multiplication result 10e or the set value 7e of the I/O port, multiplier 15e that multiplies the output +3e of selector 6e and the output 14e of lle, XOR
Gate 20e, AND game} 22e, adder/subtractor 24e,
a line memory 26e for delaying l-line data;
28e, edge emphasis block 30e, smoothing block 31e, selector 33e for selecting through data or smoothing data, delay circuit 32e for synchronizing control signals of the selector, selector 42 for selecting edge enhancement result or smoothing result.
e, delay circuit 36e and OR gate for synchronizing control signals of the selector} 39e, AND gate 4
1e, 400 line (dpi) signal (“
Inverter circuit 44e, A for outputting low output)
ND circuit 46e, OR circuit 48e and video output 11
3 and a delay circuit 43e for synchronizing the LCHG 49e. In addition, the character image correction section E is an I/O
It is connected to the CPU bus 22 via port 1e. Below is [l] Color residual removal processing that removes color signals remaining around the edges of black text areas, and subtraction at a certain rate for Y, M, and C data in the black text area determination section, and a certain rate for Bk data. [2] Edge enhancement for the text part, smoothing for the halftone judgment part, and part where through data is selected for other gradation images, [3] L for the text part.
The process is divided into three parts, each of which is a part where the CHG signal is set to "L" (printed at 400 dpi), and each part will be explained. (1) Remaining color removal processing and addition/subtraction processing In this case, the processing is performed on the area where both the signal GRBil 26 indicating that it is an achromatic color and the signal MjAR 124 indicating that it is a text area are active, that is, the edge area of the black character and its surrounding area, The Y, M, and C components protruding from the edges of black characters are removed, and the edges are filled in. Next, a detailed explanation of the operation will be given. This process is subject to character part determination (MjAR+24-“l”
), this is performed only when the mode is black (GRBil26-“1”) to the color mode (DHil22-“0”). Therefore, ND (black and white) mode (DH
i-“1”) and colored characters (GRBi="0"). When scanning a document for recording color Y, M, or C, the video manual 111 selects it with the selector 6e (I/O-
6 (5e) is set to “0”). 15e, 20e,
22e and 17e generate data to be subtracted from the video 8e. For example, if "0" is set in I/O-312e, selector output data 13e
Multiplying by the value set in I/O-17e is performed by multiplier 1.
It takes place in 5e. Here, data 18e is generated that is O-1 times as large as data 13e. By setting 1 to registers 9e and 25e, the two's complement data of 18e becomes 17e
, 20e, 22e. Finally, since the addition 23e of 8e and 23e in the adder/subtractor 24e is a two's complement, the subtraction of 17e-8e is actually performed and output from 25e. 1/0-312 When "l" is set in e, B data is selected in selector lie. At this time, the value set in I/O-210e is set at 90 for the multi-valued achromatic color signal GR125 (a signal that takes a large value if it is close to an achromatic color) generated by the character image area separation circuit I. The multiplied value is used as the multiplier of 13e. When this mode is used, the coefficients can be changed independently for each of the colors Y, M, and C, and the amount of subtraction can be changed depending on the achromatic degree. When scanning recording color Bk, selector 6e selects BkMj1.
12 is selected (“l” set to I/O-65e). 15e, 20e, 22e, and 17e generate data to be added to video 17e. Above Y, M
, C is different from I/O-4 and 9e by setting "0" to 1. As a result, 23e=8e, Ci=O, and 17e+8e is output from 25e. Coefficient 14e
The method of generation is the same as for Y, M, and C. Also, I/
In the mode in which "l" is set in O-312e, the coefficient changes depending on the degree of achromatic color. Specifically, when the degree of achromatic color is high, the amount of addition is large, and when the degree of achromatic color is small, the amount of addition is small. This process is illustrated in FIG. 22. (a) and (c) are enlarged views of the shaded portion of the black letter N. For Y, M, and C data, subtraction from the video is performed where the character signal part is "l" (Figure (b)), and for Bk data, where the character signal part is "l". is added to the video ((d) in the same figure). In this figure, 13e=1
In this example, the Y, M, and C data of the 8e text portion are 0, and the Bk data is twice that of the video. Through this processing, the outline of black characters is printed in almost a single black color, but the Y, M, and C data outside the outline signal (see Figure 22 (b)
) The * mark shown in ) remains around the letters as residual color, making it unsightly. The color removal process removes the remaining color. This processing extends to the area of the text area,
In addition, for pixels where the video data 13e is smaller than the conversion value set by the CPU, that is, outside the text area, where there is a possibility of color remaining, the process takes the minimum value of 3 or 5 pixels before and after. be. Next, the explanation will be supplemented using a circuit. Figure 23 shows a character area expansion circuit that works to expand the character area.
ND gate 69e, 71e, 73e, 75e,
It is composed of an OR gate 77e. I/O ports 70e, 72e, 74e, 76
When e is all set, M j A r 1 2 4
is “l”, the signal expanded by two pixels on the front and rear in the main scanning direction is “O” at the I/O ports 70e, 75e,
71e, 73e 'l'', a signal expanded by l pixels in the front and rear directions in the main scanning direction is output from Sig2 +8e.Next, the color residual removal processing circuit 16e will be explained. FIG. 24 shows the color residual removal processing. 24. In FIG. 24, 57e is a 3-pixel min select circuit that selects the minimum value of a total of 3 pixels, including the pixel of interest and 1 pixel before and after it, for the input signal 13e, and 58e is the input signal 13.
For e, select the maximum value of a total of five pixels, including the pixel of interest and two pixels before and after it. 5 pixel min select circuit, 55e
is a comparator that compares the magnitude of input signal 13e and I/O-18 (54e), and if 54e is larger, 1
Output. 61e, 62e are selectors, 53e,
53'e is an OR gate, 63e is a NAND gate 1.
It is. In the above configuration, the selector 60e selects 3 pixels min or 3 pixels based on the value of I/O-19 from the CPU
Select 5 pixels min. The effect of color residual removal is greater when the number of pixels is 5 pixels min. This can be selected by manual setting by the operator or automatic setting by the CPU. The selector 62e is configured so that the output of the NAND gate 63e is “0”.
", that is, the video data 13e is determined to be smaller than the register value 54e by the comparator 55e, and is within the range of expanding the character part signal, and if 17'e is 1, the A side is The B side is selected. (However, at this time, the registers 52e and 64e are "BI" and the register 52'e is "0") When the B side is selected, through data is output as 8e. The EXCON 50e can be used in place of the comparator 55e, for example, when a signal obtained by converting a luminance signal into a binary value is generated manually. FIG. 25 shows the area where the above two processes have been applied. FIG. 25(a) shows the black character N, and FIG. 25(b) shows the area determined as a character in the Y, M, and C data, which is the density data of the shaded area, that is, the character determination part (%2,
%3, +6, +7) becomes 0 by subtraction processing, +
1, %4 is cloudy due to color residue removal process 1←40,
64←Ku5, resulting in O, Figure 25 (C)
is required. On the other hand, for B and data as shown in Figure 25(d),
Only addition processing is performed in the character determination section (Ao 8, Ax 9, Ku 10, Ku 11), resulting in an output with a black ring as shown in FIG. 25. Note that no changes are made to the colored characters, as shown in FIG. 25(f). [2] Edge emphasis or smoothing processing Here, for the character determination section. Processing is performed to emphasize the edges of the image, to smooth the halftone area, and to output through the other areas. Character part. Since MjARl24 is “l”, 25e,
3 generated from the 3 line signals of 27e and 29e
The output of the x3 edge enhancement 30e is selected by the selector 42e and output from 43e. Note that the edge enhancement here is obtained from a matrix and calculation formula as shown in FIG. Halftone part → SCRN35e is "l", M j A R 2
Since 1e is "0", the smoothing 31e applied to 27e is the selector 33e, 42
It is output at e. Note that smoothing is the 27th
As shown in the figure, when the pixel of interest is vN (vN + VN + 1
)/2 as VN data, that is, smoothing of two main scanning pixels. This prevents moiré that may occur in the halftone dot area. Other portions 1. Other portions are areas that are neither character portions (character outlines) nor halftone dot portions, specifically, processing for halftone portions. At this time MjAR124 and SCRN35
Since both e are "O", the data of 27e is output as is from the video output 43e. When the characters are colored characters, the above two processes are not performed even in the character determination section. In the embodiment, an example was shown in which color residual removal was performed only in the main scanning direction, but color residual removal processing may be performed in both the main scanning and sub-scanning directions. [3] Text section 400 lines (dpi) output processing video output 1
13, LCHG140 is output from 48e. Specifically, the inverted signal of MjARl24 is output in synchronization with 43e. In the case of a character part, LCHG=01, and in other parts, it becomes 200/400-"1". As a result, the character part determination part, specifically the character outline part, is 4
00 line (dpi), and the others are printed at 200 line (dpi). Next, the character image synthesis circuit F will be explained. FIG. 28(a) is a block diagram of a circuit for processing and modifying images using binary signals in this apparatus. The color image data 138 inputted from the image data input section is inputted to the V input of the 3tol selector 45. For the other two-man power A and B of the 3tol selector 45f,
The lower part (A,
, B , ) Of 555f, A has An and B has B
, is latched by VCLK117 in latch 44f and inputted. Therefore, the output Y of the selector 45'
Select Jinriki X. , X l+ Jl,
Either V, A, or B is output based on J2 (
+14). In this embodiment, data Xn is the top two data in memory.
This bit is a mode signal that determines processing and modification. 139 is a code signal output from the area signal generation circuit.
It is controlled to switch in synchronization with 117, and the memory 43f
The address is human-powered. That is, for example, (X
10・A 10・B+o)=(01・A 10・B10
) is written in the code signal 139 in synchronization with the scanning of line l in the main scanning direction, as shown in FIG. 29(b).
If we give "lO" from point to point Q and '0' from point Q to point R, data X0 (0.1) will be read between P and Q, and at the same time (An, Bn) (AI.,B+
The data o) is latched and output. The truth table of the 3tol selector 45f is shown in FIG. 28(c).
, (X I+ X o) one (0, l) is (B)
In the case of
(2) The input is set to Y, which means that the input color image data is output as is to the output 11.1. In this way, for example, so-called tweezers character synthesis of a character portion having a value of (A+o) is realized for a color image of an apple as shown in FIG. 29(b). Similarly, (X +.Xo
) = (1, O), and enter J in Figure 29 (C) for binary input.
A signal like l is human-powered and FTFO47f ~4
9f and the circuit 46f (detailed in Fig. 28(b)), a signal as shown in J2 in the same figure is generated, and according to the truth table in Fig. 28(C), it appears in the apple image as shown in the same figure. Characters will be output with frames (outline or envelope characters). Similarly, in FIG. 28(D), the rectangular area inside the apple is (
Bn), and the characters inside are output with a density of (A,). In the same figure (A), (X,, xo) = (
0. 0), that is, any Jl, J2
Depending on the binary signal, there is a control that does nothing even with respect to changes in . The signal with expanded width input to J2 is shown in Fig. 28(b).
According to , it is an expansion of 3×3 pixels, but it is easy to make it even thicker by adding a hardware circuit. Additionally, Co, CI (366, 367) output from the 1/O port 501 in FIG. 2 in association with the output colors (Y, M, C, Bk) to be printed are stored in the memory 4
It is input to the lower 2 bits of the address of 3f, and therefore "0, 0", corresponding to the output of Y, M, C, Bk.
It changes as "o, i", "1, 0", "l, bi", so for example when yellow (Y) is output, it changes as 0, 4, 8, 1.
2. 16...Address, magenta (M) is l, 5,
9, 13.17...The address, cyan (C) is 2,
6, 10, 14. 18... Address, black (Bk) is 3, 7, 11, 15. 19・
...The address is selected. Therefore, according to an operation instruction on the operation panel, which will be described later, an address corresponding to the area code signal 139 that determines the area and the corresponding memory address within the area is set to, for example, XI-X4-"1.1" (At, A2, A3
, A4) = (αI, α2, α3, α4), (B1,
B2, B3, B4) = (βl, β2, β3, β
4), and when the moon signal changes as shown in Fig. 29 (D), the section where Jl is “Lo” becomes (YM
, C, Bk) = (αl, α2, α3.α4), and when Jl is “H1”, (Y, M, C
, Bk) = (βl, β2, β3, β4). In other words, the output color can be arbitrarily determined based on the memory contents. On the other hand, on the operation panel described later, Y, M,
C and Bk are each adjusted or set in percent (%). That is, since each gradation has 8 bits, the numerical value is 00 to 255, so a 1% fluctuation is a digital value of 2.55. The setting value is (Y, M, C, Bk) = (Y%, m%C%,
k%), the values to be set (i.e., the values written to memory) are (2.55M2.55m,
2.55c, 2.55k), and in reality, an integer rounded off to the nearest whole number is written to a predetermined memory. Furthermore, if the adjustment mechanism is used to adjust in %, an addition of 2.55△ will be added (
It is sufficient to write the value obtained by a) or subtraction (diminishing) into the memory. In the truth table of FIG. 28(c), the i column contains characters, image gradations, and resolution switching signals L C H G 1 4
9 input/output table, when A or B is output to output Y by X+, XO+ Jl, J2, it becomes "0", and V becomes Y
When outputting to , the input is output as is. L.C.H.G.
149 is a signal for switching the print density during printing, for example, when LCHG="0", for example, 40
When 0dpi and LCHG-“l”, print at 200dpi. Therefore, when A or B is selected L C H
G = O means that the inner area of the synthesized characters is printed at 400 dpi, and the area other than the characters is printed at 200 dpi, so that the characters maintain high resolution, sharpness, and high gradation for halftone areas. It is controlled to output smoothly. As mentioned above, this is why the LCHG 140 outputs the output from the character image correction circuit E based on MJAR, which is the output from the character/image separation circuit (2). <Image processing/editing circuit> Next, image signal 1 after undergoing color balance adjustment at P
15 and gradation resolution switching signal L C H G141
is input to the image processing/editing circuit G. A rough schematic diagram of the image editing processing circuit G is shown in FIG. Input image signal 115, gradation resolution switching signal LC
HG+41 is first input to the texture processing section 101g. The texture processing section is roughly divided into a memory section 103g that stores texture patterns, memories RD and WR that control them, an address control section 104g, and an arithmetic circuit 105g that performs modulation processing on input image data according to the stored pattern. has been done. The image data processed by the texture processing section 101g is then subjected to scaling, mosaic, and taper processing section 1.
02g. The scaling, mosaic, and taper processing section 102g has double buffer memory 105g, 10
6g and a processing/control unit 107g, various processes are independently performed and output by the CPU. Here, the texture processing section 101g and the scaling, mosaic, and taper processing section 102g perform processing on independent areas using enable signals GHil (119) and GHi2 (149) for each process sent from the switching circuit N.
It is configured to perform texture processing and mosaic processing. Furthermore, the gradation resolution switching signal LCHG signal 141 input together with the image data 155 is processed in various processes while matching the phase with the image signal. The image processing/editing circuit G will be explained in detail below. <Texture processing section> Texture processing is a process of cyclically reading out a pattern written in memory and applying modulation to the video. For example, the image shown in FIG. The output image shown in FIG. 2(c) is generated by modulating the image in a pattern such as that shown in FIG. FIG. 32 is a diagram illustrating the texture processing circuit. Below, modulation data 2 to texture memory 113g
18g writing section and 113g texture memory
216g of data and 215g of image data (
Texture processing) will be explained separately. [Data writing section to texture memory 113g] When writing data, masking, undercolor removal, and smearing are performed, and data is input from 201g. This data is selected by selector 202g. On the other hand, selector 208
Data 220g is selected in g, and memory 11Lg
correction and input to the enable signal of the driver 203g. The memory address is generated by the vertical counter 212g that counts up in synchronization with the horizontal synchronization signal HSYNC and the horizontal counter 211g that counts up in synchronization with the image clock and VCK.
is selected and input to the address of the memory 113g. In this way, the density pattern of the input image is stored in the memory 113.
written to g. Typically, this pattern is located and written by an input device, such as a digitizer. [Writing of data by CPU] CPU data is selected by the selector 202g. On the other hand, A is selected by the selector 208g, and the memory 11
3g and the enable signal of the driver 203g. As the memory address, A is selected by the selector 210g and inputted to the address of the memory 113g. thus,
An arbitrary density pattern is written into memory. [Calculation unit for texture memory 113g data 216g and image data 215g] This calculation is realized by a calculation unit 215g. This arithmetic unit here consists of a multiplier. Data 216g and 201 only where enable signal 128g is active
An operation with g is performed, and when the disable is enabled, the signal 201 becomes a through state. Also, 300g and 301g are XOR and OR gates, respectively, and register 304 is a part that generates an enable signal using MJ signal 308g, that is, a character synthesis signal.
When "0" is set in the g "1305g" register, texture processing is applied to areas other than those containing composite character signals.On the other hand, "0" is set in the registers 304g "0" and 305g.
When set in the register, texture processing is applied only to the part where the composite character signal is included. 302g is a portion that generates an enable signal using a GHil signal 307g, that is, a non-rectangular signal. When the register 306g is "0", texture processing is applied only to areas where the GHil signal is enabled. At this time enable 12
If 8 is kept active, non-rectangular texture processing is performed that is not affected by non-rectangular signals, that is, synchronized with HSNC, and if enable signal GHil and enable 128 are made the same, it is synchronized with non-rectangular signals. Texture processing. For example, if a 3 lb bit signal is used for GHil, texture processing can be performed only on a certain color. The LCHGIN signal 141g is a gradation resolution switching signal, and is delayed by the amount of delay in the arithmetic unit 215g.
Output from U7 350g. <Mosaic, scaling, and taper processing unit> Next, the general operation of the mosaic, scaling, and taper processing unit G12 of the image processing/editing circuit G will be described using FIG. 33. The image data 126g and the LCHG signal 350g input to the mosaic, scaling, and Taber processing section 102g are first input to the mosaic processing section 401g. The mosaic processing unit 401g uses the Mj signal 145 output from the character synthesis circuit F and the area signal GHi 2149 from the switching circuit N.
, after the mosaic clock MCLK from the mosaic processing control unit 402g determines the presence or absence of mosaic processing, the size of the mosaic in the main scanning direction, the composition of characters, etc.
It is input to the o2 selector-403g. Here, the main scanning direction size for mosaic processing is the mosaic clock MCL.
It is made variable by controlling K. Control of the mosaic clock MCLK will be explained in detail later. 1 to2 selector-403g, HSYNC118
The input image signal and LCHG signal are output to either Y1 or Y2 by the line memory select signal LMSEL whose frequency is divided by the D flip-flop 406G. The output from Y1 of 1to2 selector-403g is output from line memory A404g and 2

[Ol selector-407g
is connected to A of Also, the output from Y2 is line memory 8405g and 2tol selector 407g.
is connected to B of Line memory 8 selector
When an image is sent from 403g, line memory A4
04g is in write mode and line memory B4
05g is the read mode. Similarly, when an image is sent from the selector 403g to the line memory B 405g, the line memory B is in the write mode and the line memory A 404g is in the read mode. In this way, the image data read out alternately from the line memory A 404g and the line memory E 405g are output as continuous image data while being switched by the 2tol selector 407g by the inverted signal of the output LMSEL signal of the D flipflop 406g. 2t01 selector-4
The output image signal from 07g is then sent to the enlargement processing section 414g.
After a predetermined enlargement process is performed, the image is output. Next, write/read control of these memories will be described. First, when writing or reading, line memory A
404g. The address given to the line memory 8405g is synchronized with HSYNC, which is the reference for one scan, and is
Up/down counters 409g, 41 to increment and decrement in synchronization with LK.
It is composed of 0g. A counter enable signal output from the line memory address control unit 413g,
The operation of the address counters (409g, 410g) is controlled by a control signal WENB for controlling a write address and a control signal RENB for controlling a read address generated from the scaling control section 415g. These controlled address signals are input to 2tol selectors 407g and 408g, respectively. The 2 to 1 selectors 407g and 408g provide a read address to the line memory A 404g and a write address to the line memory 8405g when the line memory A 404g is in the read mode, using the aforementioned line memory select signal LMSEL. Line memory A404g
When in write mode, the opposite operation is performed. Next, memory write pulses WEA and WEB to line memory A and line memory B are outputted from the variable magnification control section 415g. Memory write pulses WEA and WEB are used when reducing the input image and when the mosaic processing control unit 4
Mosaic processing is controlled by a mosaic length control signal MOZWE in the sub-scanning direction output from 02g. Next, a detailed explanation of these operations will be given below. Mosaic Processing> Mosaic processing is basically realized by repeatedly outputting one image data. This mosaic processing operation will be explained using FIG. 34. First, a mosaic processing control unit 402g independently performs main scanning and sub-scanning mosaic processing control. First, set the variable corresponding to the desired mosaic size to CPU
The CPU sets the latch 501g (for main scanning) and the latch 502g (for sub-scanning) connected to US. First, for mosaic processing in the main scanning direction, the same data is written continuously to multiple addresses in the line memory, and for mosaic processing in the sub-scanning direction, writing to the line memory is performed at a specified line within the mosaic processing area. This is done by thinning out each time. (Main scanning direction mosaic processing) A variable corresponding to the mosaic width in the main scanning direction is set in the latch 501g by the CPU. The latch 501g is connected to the main scanning mosaic control counter 504g,
The setting value is loaded by the HSYNC signal and the ripple carry of the counter 504g. The counter 504g loads the value set in the latch 501g for each HSYNC, counts a predetermined value, and outputs ripple carry to the NOR gate 502g and AND gate 509g. Mosaic clock MCL from AND gate 509g
K is a signal obtained by multiplying the image clock CLK by the ripple carry from the counter 504g, and MCLK is output only when the ripple carry occurs. MCLK output from AND gate 509g is then input to mosaic processing section 401g. The mosaic processing unit 401g has two D flip-flops and an I
510g, flip-flop 51 regardless of Mj signal
Outputs 0g. When the GHi2 signal 149 is 1, Mj
When the signal is 0, a signal from the flip-flop 511g controlled by the mosaic clock MCLK is output. When the Mj signal is 1, the output is the flip-flop 510
Outputs the signal from g. With this control, it is possible to output a part of the mosaic-processed image in the main scanning direction without performing the mosaic process. In other words, it is possible to perform mosaic processing on only the image without performing mosaic processing on the characters that have been synthesized into an image by the preceding character synthesis circuit F as shown in FIG. The output from the selector 512g is input to the 2to1 selector 403g shown in FIG. 33 mentioned above. As described above, mosaic processing in the main scanning direction is performed. (Sub-scanning direction mosaic processing) Similarly to the main scanning direction, the sub-scanning direction is also controlled by a latch 502g connected to CPUBUS, a counter 505g, and a NOR gate 503g. The sub-scanning mosaic width control counter is the ITOP signal 144, 511g, selector 512g, AND gate 514g, and inverter 513.
It is composed of g. Flip flop 510g, 5
11g contains a gradation resolution switching signal LC in addition to the image signal.
HG is connected, the flip-flop 510g holds the image clock CLK, and the flip-flop 511g holds the image data inputted by the mosaic processing clock MCLK and the LCHG signal. In other words, the gradation resolution switching signal L C H G corresponding to one pixel is
Flip flop 510g, 511 when the phase is matched
G is held during each cycle of CLK and MCLK. Each retained image signal and LCHG
The signal is manually input to the 2tol selector-512g. The output is switched by the mosaic area signal GHi2 and the binary character signal Mj signal. Selector-512g
generates ripple carry pulses by counting HSYNC118. The ripple carry pulse is applied to the mosaic area signal GHi to the OR gate 508g.
2149 inverted signal G H i 2 and character signal Mj
is input. Sub-scanning mosaic control signal MOZWE41
The NAND gate 1-515g controls the write pulse generated by a line memory write pulse generation circuit (not shown). The line memory write pulse generation circuit is a circuit whose output clock rate is variable, such as a rate multi-briar which is generally used for variable magnification control. In this embodiment, detailed explanation will be omitted since it differs from the gist of the invention. The WR pulse controlled by the above MOZWE signal then becomes H
WR pulses are alternately output from the lto2 selector to WEA and WEB by the switching signal L M S E L signal in which the switching pulse changes every SYNC18. With the above control, the mosaic area signal G H i 2
Even when the signal 149 is "1", writing to the memory is performed when the Mj signal becomes "1", so a part of the mosaic-processed image in the sub-scanning direction can be output without being mosaic-processed. is possible. FIG. 35(a) is a diagram showing the distribution of density values for each pixel for recorded colors when mosaic processing is actually performed. In the mosaic processing shown in FIG. 35, each pixel in a 3×3 pixel block is set to a representative pixel value. In this process, the mosaic process is not performed on the character A1, that is, the pixels in the shaded area, based on the character signal Mj. In other words, when a composite character and a mosaic processing area overlap, priority can be given to the character. Therefore, even when mosaic processing is performed, an image can be formed so that only the characters can be read. Note that the mosaic area is not limited to a rectangular shape, and mosaic processing can also be performed on a non-rectangular area. (Italics, Taber Processing) Next, the italics processing will be described first with reference to FIGS. 33 and 36. FIG. 36 shows the inside of the line memory address control section 413g in FIG. 33. This line memory address control unit 413g has write and read counters 409g, 4
10g enable signal is controlled, and movement, italics, etc. are possible by controlling an address counter to determine which part of the main scanning line is to be written into or read from the line memory. First, using Figure 36,
The enable control signal generation circuit will be explained. Counter 701g has a counter output of 0 at HSYNC.
Then, the image clock 117, which is the clock of the counter 701g, is counted. counter 701
The output Q of g is the equisurface comparator 706g, 708g, 7
09g and 710g are powered manually. Comparator 70
The A input side of each comparator other than 9g is connected to an independent latch (not shown) connected to CPUBUS, and any set value and counter 701g are connected to each other.
A pulse is output when the output J and the output J match. The output of the equilateral comparator 706g is connected to the J of the J-K flip-flop 708g, and the comparator 707g is connected to the K input, and the J-K flip-flop is connected from the time when the comparator 706g outputs a pulse until the time when the comparator 707g outputs a pulse. The tube flop 708g is configured to output l. This output is used as a write address counter control signal, and the write address counter is activated only in the section where it is 1, and generates an address for the line memory. Similarly, the read address counter control signal controls the read address counter. Here, the converter 709
The input signal g to A is connected to a selector 703g in order to make the input value to the comparator different depending on whether or not italic processing is performed. Here, when the italic processing is not performed, the value set in the latch connected to the CPUBUS (not shown) is input to the 8 inputs of the selector 703g, and the 8 inputs are similarly output by the select signal output from the latch (not shown). It is output from the selector 703g. The subsequent operation is performed by the aforementioned comparator 706g,
The operation is similar to that of 707g. Next, when performing italics, the value input to A of selector 703g is also input to selector 702g as a preset value. When the select signals of selectors 702g and 703g select the B input, the output of selector 702g is sent to adder 70.
At 4g, addition is performed with a value set in a latch, also not shown. Here, this value indicates the amount of change per line due to the oblique angle, and if the desired angle is θ, then t
It is determined by anθ. The addition result is input to a flip-flop 708g clocked by HSYNCll8, and
The value is retained during the main scan. flip flop 705
The output of g is connected to the B input of selector 702g and the B input of selector 703g. By repeating this addition operation, the output value from the selector to the comparator 709g changes at a constant rate for each scan, so that the start of the read address counter can be varied from HSYNC at a constant rate. As a result, reading from the line memories A 404g and 8405g is shifted with respect to HSYNC, and italicization processing becomes possible. In addition, the amount of change mentioned above can be either positive or negative, and if it is positive, HSYNC
The readout shifts away from the target, and if negative, H
As it approaches SYNC, it shifts in the direction of Further, by changing the select signals of selectors 702g and 703g in synchronization with HSYNC, italicization of part of the text becomes possible. Regarding enlargement processing methods, generally 0-order, 1-order, SINC
There are methods such as interpolation, but since they are different from the gist of the present invention,
Explanation will be omitted. Taber processing is made possible by changing the magnification in the main scanning direction in synchronization with HSYNC for each scanning line while performing diagonal processing. In addition, in these processes, the input gradation resolution switching signal is processed while matching the phase with the image signal, output image data +14, output gradation resolution switching signal LCHG.
142 is output to the edge emphasizing circuit. The conceptual diagram of the italic processing and taper processing explained above is shown in the 35th page.
Shown in Figures (b) and (C). FIG. 37(a) is a block diagram showing details of the mask bitmap memory 573L and its control for restricting an area of arbitrary shape. This memory has a shape as shown in FIG. 37(e), for example, and is used for various image processing operations such as the aforementioned color conversion, image cropping (non-rectangular trimming), and image filling (non-rectangular painting).
It is used as a switching signal between N (process) and OFF (not process). That is, in FIG. 2, BHil23, DHil22,
F Hill21, G Hill9, P H i 1 4
5. Supplied via the AHil48 signal line. As shown in Fig. 38, the mask is constructed so that 4x4 pixels constitute one block and one bit of the bitmap memory corresponds to one block, so for example, 16
For an image with a pixel density of p e I / m m, 2 9
For 7 mm x 420 mm (A3 size),
(297X420X16X16)÷16#2Mbit,
That is, for example, IMBit's dynamic R
It can be configured with AM, 2 chips. The signal 132 input to the FTFO 559L in FIG. 37(a) is a data input line for mask generation as described above. When input as , first, 4×
Count the number of "1"s in the block of 4 (1 bit x 4 line buffers 559L, 560L, 561L
, 562L. FIFO559L~562L
As shown in the figure (output of 559L is input to 56OL,
The output of 560L is connected to the input of 561L, and so on, and the output of each FIFO is latched in 4 bits in parallel.
~565L is latched by VCLK (see the timing chart in FIG. 37(d)). FIFO output 615L and latch 563L, 56
4L, 565L outputs 616L, 617L, 61
8L are added by adders 566L, 567L, and 568L (signal 602L), and the CPU 22 compares the magnitude with the value (for example, "12") set via the I/O port 25L in the comparator 569L. . That is, here, it is determined whether the number of 1's in the 4×4 block is greater than a predetermined number. In FIG. 37(d), the number of "l"s in block N is "14" and the number of 1's in block (N+1) is "4", so the output of comparator 569L in FIG. 37(a) 603L is larger than "l2" when the signal 602L is "l4", so when the signal 602L is "1" and "4", it is smaller than "l2", so "
Therefore, the latch pulse 6 in FIG. 37(d)
05L, the latch 570L latches one 4×4 block once, and the Q output of the latch 570 is stored in the memory 573.
This is the DIN input of L, that is, the mask creation data. 580L is an H address counter that generates the address in the main scanning direction of the mask memory, and 1 in a 4×4 block.
Since the address is assigned, the pixel clock VCLK
Counting up is performed using a clock obtained by dividing 608 into 4 by a frequency divider 577L. Similarly, 575L is an address counter that generates an address in the sub-scanning direction of the mask memory. , ■ The operations of the addresses are controlled in synchronization with the counting (addition) operation of "1" in the 4×4 block. Also, ■lower 2 bits of address counter 1/output, 61
0L and 611L are NOR'd by a NOR gate 572L, and a signal 60 which gates a clock 607L with a frequency divided by 4 is obtained.
6L is generated, and the latch signal 605L is generated by the AND gate 571L so that latching is performed only once in a 4×4 block, as shown in timing chart FIG. 37(c).
is created. In addition, 616L is the CPU bus 22 (second
Similarly, 613L is an address bus, and a signal 615L is a write pulse WR from the CPU 22. Memory 5 from CPU 22
During WR (write) operation to 73L, the write pulse is "
Lo”, the gates 578L, 576L, and 581L are opened, and the address bus and data path from the CPU 22 are connected to the memory 573L, and predetermined data is randomly written. (write), RD read, gate 5 is connected to I/'0 port 25 by control lines of gates 576'
76'L, 582L is opened and sequential addresses are provided to memory 573L. For example, the output 421 of the binarized output 532 or the CPU
22, if a mask as shown in FIG. 39 is formed, images can be cut out and synthesized based on the area within the bold line frame. Further, the bitmap memory shown in FIG. 37(a) can be read by thinning out or interpolation in both the H direction and the ■ direction. That is, as shown in FIG. 40, the details of the V address counter (580L, 575L) or the V address counter (580L, 575L) are shown in FIG.
For example, when reducing, the B input of the selector 634L should be selected and the MULSEL 636L is set to "ON." 635L is the thinning circuit (rate multiplier) for the human clock 614L, and is shown in FIG. 41 (timing diagram).
As shown in FIG. 3, for example, C L K is thinned out so that it is output once every three times (the setting is based on the I/O port 641L) (637L). On the other hand, 630L is set to "2", for example, and only when the thinned out output 637L is output, the address counter 632L outputs 638L and 63OL
The value set (for example, "2") is added and the result is loaded into the counter. Therefore, as shown in Fig. 41, the clock advances by +2n every 3 clocks as l → 2 → 3 → 5 → 6 → 7 → 9, etc., resulting in a reduction of 80%.On the other hand, when enlarging, MULSEL = "B". , A human power 614L is selected, so the address count is l → 2 → 3 → 3 → 4 → 5 → 6 → 6, as shown in the timing chart of FIG.
→ Proceed as follows. Figure 40 shows the 11 address counter 5BOL in Figure 37,
(2) Details of the address counter 575L, and since the hardware circuit is the same, the explanation will be limited to FIG. 37 only. As a result, as shown in Fig. 42, enlargement 2 and reduction 1 are generated for the input non-rectangular area l, so once the non-rectangular area is input, no new input work is required. Furthermore, with one mask brain, it is possible to change the magnification according to various magnifications. Next, the binarization circuit (532 in FIG. 2) and the high-density binary memory circuit 2 will be explained. In FIG. 43(a), the binarization circuit 532 is a circuit that compares the video signal 113 output from the character image correction circuit E with a threshold value 141k and obtains a binarized signal. It is set in conjunction with the operation panel. In other words, the threshold value is M for the input data amplitude value = 256.
(midpoint), it is "128", and as the scale moves in the ten directions, it changes by -30" from the midpoint, and as it moves in one direction, it changes by "+30". Therefore, "
Corresponding to weak → -2 → -l → M → ten l → +2 → strong 7, the threshold value is “218 → 188 → 158 → 128 → 98 → 68 →
38''. Also, as shown in FIG. 43(a), CPUBU3
From 22, two threshold values are set, and the selector 35
At k, it is switched by the switching signal 151 and set as a threshold value in the comparator 32k. For the switching signal 151, a different threshold value is set only within a specific area set by the Digitiger 58. For example, the threshold value is relatively low for a monochromatic area of the original, and relatively high for a mixed color area. Settings can be made so that a uniform binary signal is always obtained regardless of the color of the original. The memory circuit K is a memory that stores the signal in which the binarized signal 421 is output to 130 for one page of images, and since this device handles images at A3 and 400 (dpi), approximately 3 It has 2 Mbit. Details of the memory circuit K will be explained in FIG. 43(b). The input data D and N130 are gated by the enable signal HE52B when writing to the memory, and are further gated by the IO port 23k controlled by the CPU 20 when writing. /R
When the 1 output is "Hi", it is input to the memory part 37k. At the same time, synchronization signal HSYNCl18 in the main scanning (horizontal scanning) direction is transmitted from the synchronization signal ITOP144 in the vertical direction of the image.
to generate a vertical address. ■ Count VCLK 117 of image transfer from address counter 35k and HSYNCI18,
Count horizontal addresses. The H address counter generates an address corresponding to storage of image data. At this time, a clock having the same phase as the clock VCLK117 is input as a strobe to the memory WP input (write timing signal) 551k, and the input data D
i is sequentially stored in the memory part 37k (timing diagram, FIG. 44). When reading data from the memory 37k, set the control signal W/Rl to "Lo" and read all the output data D using the same procedure. U■ is read out. However, data writing and reading are both HE5
For example, as shown in Fig. 44,
2B as input timer of D2. If you raise it to "Hi" at the input timing and lower it to "Lo" at the input timing of Dm,
Only images D2 to Dm are input to the memory 37k. , D, and Dm++ are not written, and data "0" is written instead. The same goes for reading, and data "0" is read except for the section where HE is "old". HE is output from an area signal generation circuit 17, which will be described later. In other words, for example, when a character original as shown in FIG. Value images can be loaded into memory. Similarly, unnecessary characters can also be erased and written into the memory. Furthermore, since the address counters 35k and 36k that read data from the main memory 37k have the same configuration as in FIG. 40 and operate at the same timing as in FIG. 41, the binary data read from the main memory 37k is can be scaled. Therefore, when synthesizing the binary character image shown in (B) of the same figure, which has been previously stored in this memory as shown in Fig. 46, with the image of (A), both of them are reduced as shown in (C). or create a sketch ((A) as shown in (D)).
It is possible to perform composition by enlarging only the character part to be composited without changing the size of the part ). FIG. 47 shows the data stored at +00 dpi as described above.
Binary bitmap memory L for non-rectangular masks (Figure 2) and 400 dpi binary memory K for characters and line images (Figure 2)
Each image processing block of data from A, B, D,
This is a switching circuit for switching between distribution to F, P, and G and distribution of binarized video images to memories L and K. The mask data for limiting the non-rectangular area stored in the memory is, for example, the color conversion circuit B described above.
(B 14 i l 2 3 ), and color conversion is applied only to the inside of the shape as shown in FIG. 48(B), for example. In FIG. 47, 1n is an I/O port connected to the CPU bus 22, and 8n to 13n are 2to
l selector, A input when switching manually S-“9”;
It is configured to output the B input to Y when S- is "0". Therefore, for example, in order to send the output of the loOdpi mask memory L to the color conversion circuit B as described above, A is selected in the selector 90, that is, 28n-''1
", AND game}3n, input 21n may be set as "bi. Similarly, other signals are also determined by 16n to 31n.
Can be controlled arbitrarily. Output of I/O port nl, 30n,
31n is a control signal 30 which determines which of the binary memories L and K the output of the binarization circuit 532 (FIG. 2) is stored.
When n-“1”, the binary human power 421 is input to the 100 dpi memory L, and when 31n=-1”, it is input to the 400 dpi memory K. By the way, when AHi148-“l”, the binary human power 421 is input from the external device. The image data of the B II i l
2 3 When “1”, perform color conversion as described above, and
When H i122-“l”, monochrome image data is calculated and output from the color correction circuit. Below FHi 121
, PHi145, GHi119, GHi2 1
49 are used for character composition, color balance change, texture processing, and mosaic processing, respectively. In this way, it has two binary memories, 100 dpi memory L and 400 dpi memory K, and stores character information in high-density 4-bit memory.
By inputting region information (including rectangular and non-rectangular shapes) into the 100 dpi memory K, character synthesis can be performed in a predetermined region, especially in a non-rectangular region. Furthermore, by having a plurality of bitmap memories, color mudding processing as shown in FIG. 62 is also possible. FIG. 49 is a diagram for explaining the area signal generation circuit J. The area refers to, for example, the shaded area in FIG. 49(e), which refers to the timing chart AREA in FIG. 49(e) for each line in the section in the sub-scanning direction A-B.
It is distinguished from the pond area by signals such as . Each area is designated by digitizer 58 in FIG. Figure 49(a)-(d)
), the generation position, section length, and number of sections of this area signal are C
This shows a configuration that is programmable and can be obtained in large numbers by the PU 20. In this configuration, one area signal is generated by one bit of a CPU-accessible RAM, and for example, in order to obtain n area signals AREAO to AREAn, two RAMs each having an n-bit configuration are provided. (Figure 49(d) 60j, 61j). Now, Figure 49 (
If we obtain area signals AREAO and AREAn as shown in b), we set "l" in bit 0 of RAM address Xl+X3, and all bits O of the remaining addresses are
0". On the other hand, the RAM addresses l, x,, x2,
Set "I" to X4, and set all bits n of other addresses to "0". When the data in the RAM is sequentially read in synchronization with a constant clock 117 using HSYNC 118 as a reference, data "l" is read out at addresses X and X3, for example, as shown in FIG. 49(C). . This read data is shown in FIG. 49(d).
62j-0~62j-n J-K flip-flop J
, K are connected to both terminals, so the output toggles,
In other words, when "1" is read from the RAM and CLK is input, the output changes from "0" to "l" and from '1' to "0", generating an interval signal such as AREAO, and therefore an area signal. Furthermore, if data is set to "0" over all addresses, no area section is generated and no area setting is performed. FIG.
j is the aforementioned RAM. For example, while reading data from RAMA 60j line by line, in order to switch the area interval to 'high distance',
1j, the CPU 20 (FIG. 2) performs memory write operations for setting different areas, and alternately switches between section generation and memory write from the CPU. Therefore, if you specify the shaded area in Figure 49(f), RAMA and RAMB
is switched, which is shown in FIG. 49(d) as (C
3, C4, C5) = (o, l, O), the counter output counted by VCLKll7 is given as an address to the RAM 60j through the selector 63j (Aa), and the gate 66j is opened and the gate 68j is closed. Read from RAMA60J, total bit width, n
Bits are J-K flipflop 62j-0~62
AREAO ~ according to the value input and set to j-n
An interval signal of AREAn is generated. During this time, writing from the CPU to B is via the address bus A-B.
, data node D-Bus and access signal R/W
This is done by Conversely, when generating section signals based on data set in RAMB61j (C3, C4, C
5)" (1,0.1), it can be done in the same way and data can be written from the CPU to the RAM 60j. 58 is a digitizer for specifying the area, and the CPU
The coordinates of the specified position are input from U20 via the I/O boat. For example, in FIG. 50, when two points A and B are specified, the coordinates of A (XI, Y2) and B (X2, Yl) are input. FIG. 51 shows an interface circuit M for bidirectional communication of image data with an external device connected to this image processing system. lm is an I/○ port I connected to the CPU bus 22, and each data bus AO to CO, A
Signals 5m to 9m for controlling the directions of 1 to C1 and D are output. 2m and 3m are pass buffers having an output dry state control signal E, and 3m can change its direction by inputting D. For 2m and 3m, when E input = “B”,
A signal is output, and when it is "0", the output is in a high impedance state. tOm has 3 parallel inputs A, B,
3t to select one from C by selection signals 6m and 7m
ol selector. In this circuit, basically 1. (
AO, BO, Co) → (AI, Bl, CI), 2.
There is a bus flow of (AI, Bl, CI)→D. CP as shown in the truth table in Figure 52.
Controlled by U20. In this system, as shown in Fig. 53, images input from external equipment through Al, A2, and A3 are rectangular, (
B) Both non-rectangular and non-rectangular configurations are possible. When inputting in a rectangular shape as shown in FIG. 53 (A), a control signal is sent from the I/O port 501 in order to set the switching input of the selector 503 in FIG. Outputs 147. Corresponds to the area to be combined at the same time. Area signal generation circuit J
The rectangular area signal 129 is generated by writing predetermined data from the CPU to predetermined addresses in the RAMs 60j and 61j (FIG. 51), as described above. In the area where the image input 128 from the external device is selected by the selector 507, not only the image data 128 but also the gradation and resolution switching signals 140 are switched at the same time. That is, in an area where an image from an external device is input, a character area signal is generated based on the MIAR 124 (FIG. 2), which is detected from the color separation signals of the image read from the document table. Stop the gradation and resolution switching signals and forcefully “
I-1 i", the image area from the inserted external device is outputted smoothly with high gradation. Also, as explained in Figure 51, the bits from the binary memory L When the map mask signal A 11 i 1 4 8 is selected by the signal 147 in the selector 503, the fifth
Image synthesis from external equipment as shown in FIG. 3(B) is realized. <Outline of Operation Section> FIG. 54 shows an overview of the main body operation section 1000 of this embodiment. Key 1100 is a copy start key. Key 1101 is a reset key that returns all settings on the operation unit to the values at power-on. A key 1102 is a clear stop key, which is used to reset input values such as specifying the number of copies and to cancel a copy operation. A group of keys 1103 is a numeric keypad and is used to input numerical values such as the number of copies and magnification input. Key l104 is a document size detection key. Key l105 is a center movement designation key. A key 1106 is an ACS function (black original recognition) key. When ACS is ON, a monochrome black original will be copied in monochrome black. A key 1107 is a remote key, and is a key for passing control to a connected device. Key 1108 is a preheat key. A liquid crystal screen 1109 displays various information. The surface of the screen is a transparent touch panel, and when you press it with your finger, the coordinate values are captured. In the standard state, the magnification, selected paper size, number of copies, and copy density are displayed. While setting various copy modes, the screens necessary for mode settings are displayed one after another. (The copy mode is set using the keys displayed on the screen.) Also displays the self-diagnosis display screen on the guide screen. A key 1110 is a zoom key, and is an enter key for entering a mode for specifying the magnification of magnification. A key 1111 is a zoom program key, and is an enter key to a mode in which a magnification ratio is calculated from the original size and copy size. Key! Reference numeral 112 is an enlarged continuous shooting key, which is an enter key for entering enlarged continuous shooting mode. A key 1113 is a key for setting inset composition. A key 1114 is a key set for character composition. key 1
115 is a key for setting color balance. key 1
Reference numeral 116 is a key for setting a color mode such as single color, negative/positive inversion, etc. Key 1117 is a user's color key, and can set any color mode. key l11
8 is the pane 1 key, which allows you to set the paint mode. Key 1119 This is a key for setting the color conversion mode. Key 1120 is a key for setting the contour mode. The key 1l21 sets the mirror image mode. Keys 124 and 1123 specify trimming and masking. It is possible to specify an area using the key 1122 and set the internal processing to be different from that of the pond. key 112
9 is an enter key for entering a mode for performing operations such as reading texture images. Key l128 is an enter key for entering a mosaic mode such as changing the mosaic size. Key 1127 is an enter key to a mode that adjusts the edge sharpness of the output image. The key 1126 is a key for setting an image repeat mode in which a specified image is repeatedly output. A key 1125 is a key for applying italic/taper processing, etc. to an image. Key 1135 is a key for changing the movement mode. The key 113=1 is used to make settings such as page quick copying and arbitrary division, and the key 1133 is used to make settings related to the projector. Key 1132 is an enter key to a mode for controlling optional connected equipment. The key 1131 is a recall key that allows you to recall the settings up to three times ago. Key 1130 is an asterisk key. Keys 1136 to 1l39 are mode memory recall keys.
Used when recalling a registered mode memory. Keys 1140 to 1143 are program memory call keys, which are used to call up registered operation programs. <Color Conversion Operation Procedure> The color conversion operation procedure will be explained using FIG. 55. First, when the color conversion key 1119 on the main body operation section is pressed, the display section l109 is displayed as P050. Place the original on the digitizer and use the pen to specify the color before conversion. When the input is completed, the screen of PO51 appears. Here, use the touch keys 1050 and 1051 to adjust the width of the color before conversion, and after completing the settings, press the touch key 1052.
Press. The screen changes to P052, and the user selects whether or not to add shading to the converted color using touch keys 1053 and 1054. If you select shading, the color after conversion will have gradation to match the shading of the color before conversion. That is, the above-mentioned gradation color conversion is performed. On the other hand, if you select no shading, the specified color will be converted to the same density. When you select whether or not to have shading, the screen of PO53 appears, and you can select the type of color after conversion. When 1055 is selected in PO53, P
054, the operator can specify any color. Further, when the color adjustment key is pressed, the screen moves to PO55, and color adjustment can be performed in 1% increments for each of Y, M, C, and Bk. Further, if 1056 is pressed in P053, the process moves to P056, and the desired color of the document on the digitizer is specified using the point ben. Next, the color shading can be adjusted using PO57. Furthermore, if 1057 is pressed at P053, the screen moves to P058, where a predetermined registered color can be selected by number. <1-Procedure for specifying the rimming area> Below, using Fig. 56 and Fig. 57, trimming (
The same goes for masking, and how to specify areas.
The same procedure applies to partial processing, etc. ) Explain the procedure for specifying an area. Press the trimming key 1124 on the main unit operation unit l000, and when the display unit 1109 shows POOI, input two diagonal points of the rectangle using the decimizer, and the POO2 screen will appear, allowing you to continue inputting the rectangular area. can. Also, if you specify multiple areas, press the previous area key fool and then area key 1002 to select POO.
As shown in 2, each designated area in the X-Y coordinates can be confirmed. On the other hand, in this embodiment, it is possible to specify a non-rectangular area using the bitmap memory. While displaying the POOI screen, press the touch key 1003 to move to POO3. Select the shape here. For circles, ellipses, R-rectangles, etc., when the necessary coordinate values are input, the shape is expanded into the hit map memory by calculation. In the case of a free shape, coordinate values are continuously input by tracing the desired shape with a point pen using a digitizer, and the values are processed and recorded on a bitmap. Each non-rectangular area specification will be explained below. (Circular area designation) When key 1004 is pressed at P003, the display section 1109 shows P.
Moving to 004, a circular area can be specified. The circular area designation will be explained below using the flowchart of FIG. 58. In S101, the center point is input from the digitizer 58 in FIG. 2 (POO4). Next, the display unit 1109 moves to POO5, and in S103 inputs one point on the circumference of a circle having the radius to be specified from the digitizer 58. In S105, the CPU 20 calculates the coordinate values of the input coordinate values on the bitmap memory L (100 dpi binary memory) shown in FIG. Further, in step 5107, coordinate values of another point on the circumference are calculated. Next, in step 3109, a node in the bitmap memory L is selected, and in Sll, the above calculation result is input to the bitmap memory L via the CPU bus 22. Figure 37 (a
), it is written from CPU DATA 616L to bitmap memory from 604L via driver 578L. Address control is the same as described above, so it will be omitted. This is repeated for all points on the circumference (St13) to complete the circular area designation. In addition, instead of inputting information while calculating it on the CPU 20 as described above, template information for two pieces of information input in advance is stored in RO~ill, and these two pieces of information are stored in RO~ill.
It is also possible to write the point directly into the bitmap memory L without calculation by specifying the point with a digitizer. (Oval area designation) When the key 1005 is pressed in P003, the process moves to POO7. The process will be explained below using the flowchart shown in FIG. First, 5202 is the diagonal 2 of the largest rectangular area inscribed in the ellipse.
A point is designated by the decimeter 58. Below, for the circumferential part, do 8206 in the same way as in the case of specifying the circular area above.
~S2] Write to the hit map memory L according to the procedure of 2. Next, the straight line portion is written into the memory L through steps S2+4 to S220, and the area designation is completed. As in the case of a circular shape, it can also be stored in the ROM 21 in advance as template information. (R rectangular area designation) The method of designation is the same as in the case of an ellipse for memory writing, so the explanation will be omitted. Incidentally, although the cases of a circle, an ellipse, and an R rectangle have been explained above as examples, it goes without saying that other non-rectangular areas can also be specified based on the same template information. In POO6 POO8, Polo, P102,
By pressing the clear key (1009 to 1012) after inputting each shape, a portion of the bitmap memory can be erased. Therefore, even if a mistake is made in the designation, only the two points can be quickly cleared and the two points can be designated again. It is also possible to specify multiple areas in succession. When multiple areas are specified, priority is given to processing of the area specified later when processing each of the overlapping areas. However, the one specified first may be given priority. FIG. 57 shows an output example obtained by trimming with an ellipse using the above settings. Operational Procedures for Character Synthesis> The operation and setting procedures for character synthesis will be described below with reference to FIGS. 60, 61, and 62. When you press the character synthesis key 1114 on the main body operation section, the liquid crystal display section 1109 displays P.
It is displayed as 020. When the character original l201 to be synthesized is placed on the aforementioned original table and the touch key 120 is pressed, the character original is read, binarized, and the image information is stored in the aforementioned bit map memory FIG. 2. The specific means of processing has been described above, so duplication will be avoided. To specify the range of the image to be stored at this time, press the touch key 1021 in PO20 to go to the screen of PO21, place the text original 1201 on the digitizer 58, and use the point pen of the digitizer to mark the range with two points. specify. When the specification is completed, the display section changes to P022, and the user selects whether to read within the range specified by the touch keys 1023 and 1024 (+-rimming) or to read outside the specified range (masking). Furthermore, depending on the text document, it may be difficult to extract the character portion of the text document during the above-mentioned binarization process. In this case, the touch key 1022 in PO20 moves to the screen of PO23, and the slice level of the binarization process can be adjusted using the touch keys 1025 and 1026. Since the slice level can be adjusted manually in this way, appropriate binarization processing can be performed depending on the color, thickness, etc. of the characters on the document. Furthermore, press the touch key 1027, PO24'PO2
By specifying an area with 5', it is possible to partially change the slice level with PO26'. In this way, by specifying an area and changing the slice level only for that part, even if there is, for example, yellow text in a part of the black text document, separate appropriate slice levels can be set for each of the black and yellow text. By doing so, it is possible to perform good binarization processing on the entire character. When the reading of the character original is completed, the display section 1109 becomes as shown in FIG. 61, P024. To select color blank processing, touch key 10 in P024
Press 27 to move to the screen of P025, and select the color of the characters to be combined from among the displayed colors. It is also possible to partially change the color of the text, in which case the user presses the touch key l029 to move to the screen P027, specifies the area, and then selects the color of the text on the screen P030. Furthermore, it is also possible to add color border processing to the edges of the characters to be synthesized, in which case PO30
Use the touch key 1031 inside to move to the PO32 screen and select the color of the border. At this time, color adjustment can be performed in the same way as in the case of color conversion described above. Furthermore, touch key 1033
Press to adjust the border width on the PO41 screen. Next, a case in which color number processing is added to a rectangular area containing characters to be synthesized (hereinafter referred to as square processing) will be described. PO2
Press the touch key 1028 in 4 to move to the PO 34 screen and specify the area. The processing will be performed within the range specified here. When the area designation is completed, the character color is selected at PO37, and the touch key 1032 is pressed to move to the screen at P039, where the color of the tomato is selected. In the above color selection, for example, on the screen PO25, by pressing the color adjustment key of the touch key 1030, the screen moves to P026, where it is possible to change the tone of the selected color. Character synthesis is performed according to the procedure described above. FIG. 62 shows an example of the output when the settings are actually made. In addition to specifying a rectangular area, the area specification can also specify a non-rectangular area as described above. <Texture processing setting procedure> Next, texture processing will be explained using FIG. 63. When the texture key 1129 on the main body operation section 1000 is pressed, the display section 1109 displays something like PO60. When applying texture processing, touch key 1060 is pressed to highlight this key. When reading the image pattern for texture processing into the aforementioned texture image memory (Fig. 32, 113g), press the Tatsuji key 106.
Press 1. At this time, if the pattern is already in the image memory, as in PO62, if it is not displayed, P
O61 will be displayed. The image data is stored in the texture image memory by placing the document with the image to be read on the document table and pressing the touch key 1062. At this time, in order to read any part of the manuscript,
Press the touch keys 1 0 6 3 and make a designation using the digitizer 58 on the PO 63 screen. The specification is the reading range, l
This can be done by inserting a pen at one point in the center of 6 mm x 16 mm. Reading of a texture pattern by specifying one point as described above can be performed as follows. Without reading the pattern, press touch key 1060 to set texture processing, copy start key 1100, other mode keys (1110 to 1143),
Alternatively, if the user attempts to escape from the P064 screen using the touch key 1064 or the like, the display unit issues a warning as shown in PO65. Further, the length and width of this range can be specified by the operator. <Mosaic processing setting procedure> FIG. 64 is a diagram explaining the procedure of mosaic processing setting. When the mosaic key 1128 on the main body operation section is pressed, the display section displays something like PIOO. To apply mosaic processing to a document, touch key 1400 is pressed to highlight this key. Furthermore, when performing mosaic processing, the mosaic size is changed by pressing the touch key 1401 on the PIOI screen. The mosaic size can be changed independently in both the vertical (Y) direction and the horizontal (X) direction. <About the blue mode operating procedure> FIG. 65 is a diagram illustrating the blue mode operating procedure. When the hard key 1l30 on the main body operation section 1000 is pressed, the hard mode is entered, and the display section 1109 is displayed as PIIO. Touch key l500 is painted user's color. Color conversion. Enters color registration mode for registering color information used in color text, etc. A touch key 1501 turns on/off a function for correcting image defects caused by the printer. Touch key 1502 is a key for entering mode memory registration mode. Touch key 1503 enters a mode for specifying the manual feed size. Touch key 1504 enters program memory registration mode. Touch key 1505 is a key for entering a mode for setting default values of color balance. (About color registration mode) When the touch key 1500 is pressed when PIIO is displayed, the color registration mode is entered. The display section looks like Pill, and the type of color to be registered is selected. To change the palette color, press the touch key 1506, select the color you want to change on the screen of P116, and select yellow, yellow, etc. on the screen of P117.
The values of magenta, cyan, and black components can be adjusted in 1% increments. Also, if you want to register any color on the document, touch key 1.
Press 507, select the registration number on the screen of [Pl]8,
Specify using the digitizer 58, set the original on the original table when the screen of P120 is displayed, press the touch key 1510,
Register. (About manual feed size specification) As shown on page 112, manual feed size can be specified as either standard or non-standard size. For irregular shapes, both the horizontal (X) direction and the vertical (Y) direction can be specified in units of 1 mm. (Regarding mode memory registration) The set mode can be registered in the mode memory as shown in PI 13. (Regarding Program Memory Registration) As shown in P114, a series of programs for specifying an area or performing predetermined processing can be registered. (Regarding color balance registration) As shown in P115, color balance can be registered for each of Y, M, C, and Bk. <Regarding program memory operation procedure> The registration operation in the program memory and its usage procedure will be explained below with reference to FIGS. 66 and 67. Program memory is a memory function that stores operating procedures related to settings and reproduces them. It is possible to connect the necessary modes and make settings that go beyond unnecessary screens. As an example, let's program memory the procedure for changing the magnification of a certain area of a document and repeating the image. Press the mode key 1130 on the operation section of the main body to display the screen P080 on the liquid crystal display section, and press the program memory key of the touch key 1200. In this embodiment, four programs can be registered. Select the number to register on the PO81 screen. After this, move to program registration mode. In the program registration mode, for example, the screen shown in FIG. 68 1300 in the normal mode becomes as shown in l301. The skip key of the touch keys 1302 is designated when the user wants to skip the current screen. The clear key of the touch keys 1303 is used when canceling the current registration in the middle of program memory registration and redoing the registration from the beginning. The En1-key of the touch keys 1304 exits the program memory registration mode and registers in the memory of the first determined number. First, press the trimming key 1124 in the main unit operation section,
Specify the area with the dentizer. The display unit is displaying PO84, but if no further area settings are to be made at this point, touch key 1202 is pressed to designate skipping this screen. (The screen becomes P085) Next, when the zoom key 1110 on the main body operation section is pressed, the display section becomes PO86. Here, the magnification is set and when the touch key 1203 is pressed, the display changes to PO87. Finally, press the image repeat key l126 on the main body operation section, make settings related to image repeat on the screen P088, and then register to number 1 in the program memory using the touch key l204. To call up the program registered in the above procedure, press the program memory 1 call key 1140 on the main body operation section. The display section displays P091 and waits for area input. If you input the area using a digitizer,
The display section displays P092 and then moves on to the next P093. After setting the magnification here, if the touch key 12]0 is pressed, the display section becomes P 0 9 =1 and image repeat can be set. When the touch key 1211 is pressed, the mode in which the program memory is used (referred to as trace mode) is exited. Note that from the time the program memory is called until the program is terminated,
Each key (1110 to 1143) in the edit mode is disabled, and operations can be performed according to the registered program. FIG. 69 shows the program memory registration algorithm. Screen turning in S301 means changing the display on the display unit using keys or touch keys. If you press touch key l302 and specify to skip the currently displayed screen (S303), that information will be set on the recording table when the next screen is turned (S303).
305). Then, in S307, a new screen number is set in the recording table. If the clear key is pressed, the record table is completely cleared (S309, S311); otherwise, the process returns to S301 and moves to the next new screen. FIG. 71 shows the format of the recording table. FIG. 70 shows an algorithm representing the operation after calling the program memory. If there is a screen turn in S401, it is determined whether the new screen is a standard screen (S, 103). If it is a standard screen, the process moves to S411 and sets the next screen number from the recording table, and if it is not a standard image, the new screen number is compared with the scheduled screen number in the recording table (S405).
), if they are equal, the process moves to S409, and if there is a skip flag, S411 is skipped and the process returns to S401. Equal《
If not, a recovery process is performed (S407) and the screen is turned over. Next, the contour extraction circuit 127I in FIG. 15 will be explained. In this embodiment, the contours are extracted from the difference area between the thickened and thinned images. Therefore, the thinning process and the fattening process will be specifically explained below. Narrowing Process> The narrowing process is composed of a circuit as shown in FIG. 72. An AND circuit 7003 performs an AND operation on the lbit data from L1 to L17, which are delayed one line at a time in FIFO (first-in, first-out) memories 7001 and 7002. The result is A for all lbit data from P1 to Pl7 delayed by flip-flops 7004 to 7020 in the main scanning direction as well.
By performing an AND operation in the ND circuit 7021, thinning processing is performed using a 17×17 mask. That is, the 73rd
As shown in the figure, if even one 0 exists in the 17×17 mask, the center data is output as 0. for example,
If all 17X17 are 1 and the others are 0, only the center of the 17X17 mask is 1, and all others are replaced by 0. By performing such thinning processing, dust and noise in the image can be removed. Incidentally, here we took the AND of the binary data of all the pixels of 17x17, but rather than AND, if there are more than a certain number of 0s, the central data (data of the pixel of interest) is
It is also possible to do something like this. Furthermore, the matrix size can be freely set. Thickening process> Thickening process is the same concept as thinning process, and the 74th
It consists of a circuit as shown in the figure. FjFo memory 8001. Ll delayed by one line at 8002
-OR circuit 80 for each 1-bit data up to L17
Take OR with 03. The result is similarly delayed by flip-flops 8004 to 8020 in the main scanning direction.
By ORing all the lbit data up to I-P17 with an OR circuit 802l, fattening processing is performed using a 17×17 mask. The thickening process is the opposite of the thinning process, if there is even one l in the 17Xl7 mask,
The center data is output as l. As in the case of thinning processing, if there are a certain number of 1's, the center data can be set to 1. Moreover, the matrix size can also be made variable. That is, an appropriate matrix size can be automatically or manually set so as to minimize false determinations. Further, in the above embodiment, the thinning process and the fattening process were performed on a binary image, but such processing can also be performed on a multivalued image by setting a predetermined threshold value. As explained above, according to this embodiment, the circuit size is reduced by binarizing the signal generated based on color separation data and generating the character area signal from the signal that enlarges or reduces the area. Reliable character image discrimination results can be obtained, and the quality of output images is improved. That is, a means for inputting image data (such as FIG. 2A),
a first processing means (
(Fig. 72), and a second processing means (Fig. 74) that performs fattening processing on the output of the first processing means, thereby ensuring reliable image area discrimination without being affected by noise etc. be able to. [Effects of the Invention] As explained above, according to the present invention, image area separation for images containing mixed characters can be performed with high accuracy. Fig. 2 is a circuit diagram of image processing according to an embodiment of the present invention, Fig. 3 is a diagram showing a color reading sensor and driving pulse, Fig. 4 is a circuit diagram for generating ODRV118a and EDRV119a, and Fig. 5 is a black correction Figure 6 is a shading correction circuit diagram, Figure 7 is a color conversion block diagram, Figure 8 is a color detection unit block diagram, Figure 9 is a color conversion circuit block diagram, and Figure 10 is a diagram explaining the operation. A diagram showing a specific example of color conversion, Figure 11 is a diagram explaining logarithmic conversion, Figure 12 is a circuit diagram of a color correction circuit, Figure I3 is a diagram showing an unnecessary transmission area of a filter, and Figure 14 is a diagram showing a specific example of color conversion.
The figure shows unnecessary absorption components of the filter, Figure 15 is a circuit diagram of a character image area separation circuit, Figure 16 is a diagram explaining the concept of contour regeneration, and Figure 17 explains the concept of contour regeneration. Figure 18 is a contour regeneration circuit diagram, Figure 19 is a contour regeneration circuit diagram, Figure 20 is a timing chart of ENI and EN2,
Figure 1 is a block diagram of the character image correction section, Figure 22 is an explanatory diagram of addition/subtraction processing, Figure 23 is a switching signal generation circuit diagram, Figure 24 is a circuit diagram of color residual removal processing, and Figure 25 is color residual removal processing. , Figure 26 is a diagram showing edge emphasis, Figure 27 is a diagram showing smoothing, Figure 28 is a diagram explaining processing and modification processing using binary signals, Figure 29 is a diagram explaining text, Figure 30 is a block diagram of the image editing circuit, Figure 31 is a diagram showing texture processing, Figure 32 is a circuit diagram of texture processing, Figure 33 is a diagram of mosaic, scaling, and tapering processing. A circuit diagram, FIG. 34 is a circuit diagram of mosaic processing, FIG. 35 is a diagram explaining mosaic processing, etc., FIG. 36 is a circuit diagram of the line memory address control section, FIG. 37 is an explanatory diagram of the mask bit memory, Fig. 38 is a diagram showing addresses, Fig. 39 is a diagram showing a specific example of a mask, Fig. 40 is a circuit diagram of an address counter, Fig. 41 is a timing chart for enlargement and reduction, and Fig. 42 is a diagram for enlargement and reduction. Figure 43 is an explanatory diagram of the binarization circuit, Figure 44 is a timing chart of the address counter, Figure 45 is a diagram showing a concrete example of bit/map memory writing, Figure 46 is a character , a diagram showing a specific example of image synthesis, FIG. 47 is a circuit diagram of distribution switching, FIG. 48 is a diagram showing a specific example of a nonlinear mask, FIG. 49 is a circuit diagram of a region signal generation circuit, and FIG. 50 is a digitizer 51 is an interface circuit diagram with external equipment, FIG. 52 is a selector truth table, FIG. 53 is a diagram showing examples of rectangular areas and non-rectangular areas, and FIG. 54
55 is a diagram explaining the procedure of color conversion operation, FIG. 56 is a diagram explaining the procedure of specifying the trimming area, FIG. 57 is a diagram explaining the procedure of specifying the trimming area, Figure 58 is a diagram showing the algorithm for specifying a circular area.
Figure 9 is a diagram showing the algorithm for specifying areas of ellipses and R rectangles, Figure 60 is an explanatory diagram of the operating procedure for character composition, Figure 61 is an explanatory diagram of the operating procedure for character composition, and Figure 62 is an illustration of the operation procedure for character composition. Figure 63 is a diagram explaining the procedure of texture processing, Figure 64 is a diagram explaining the procedure of mosaic processing, Figure 65 is a diagram explaining the procedure of yellow mode operation, Figure 66 is a diagram explaining the procedure of operation procedure.
Figure 67 is a diagram explaining the program memory operation procedure. Figure 68 is a diagram explaining the program memory operation procedure. Figure 69 is a diagram explaining the program memory registration algorithm. Figure 70 is a diagram showing the algorithm of the operation after calling the program memory; Figure 71 is a diagram showing the format of the recording table;
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Claims (1)

[Claims] (1) means for inputting image data; first processing means for performing thinning processing on the input image; second processing means for performing fattening processing on the input image; An image processing device comprising: means for extracting a contour signal based on an output signal and an output signal of the second processing means.