JPH02294737A - Information processor - Google Patents

Abstract

PURPOSE:To shorten the time required for process switching by executing background processing for plural processes in an information processor so as to be overlapped to a current process. CONSTITUTION:When an instruction is decoded by a decoder 2, a unit 20 obtains information indicating whether the contents of registers are to be loaded/stored in/to a logical register address background and outputs a register address signals 21-23 for a current process and a register address signal 24 for non-current processes. The registers inherent in non-current processes are decided by the address signal 24, successively selected one by one, the data of the register for the last process are saved and the data of the register for the succeeding process are loaded. Consequently, the loading, storage, address information, etc., of process data for the current process can be executed in the background, efficient operation can be attained and the time required for process switching in a CPU can be minimized up to the vicinity of zero.

Description

[Detailed Description of the Invention] [Configuration of the Invention (Industrial Application Field) The present invention relates to an information processing device having a large-capacity register file, and relates to an information processing device that performs multi- or parallel processing by time division, etc. It is something.

(Prior Art) In this type of information processing device, processing associated with calls/returns within a process (work) is generally solved by overlapping windows. However, the load associated with process switching (saving register contents, etc.) has not been resolved much, and the time required for context switching, that is, process switching, tends to increase due to saving/loading large register files, etc. ．． Figure 3 is a block diagram showing this and only the parts related to the register file are shown. 1 in the figure is the instruction. 2 is the decoder, 3 is the destination. 4 is the address register of the first source register, 5 is the address register of the second source register, 6 is the window control device, and 7 is the current window? 8 is a register file, 9 is a decoded instruction, IO is a destination data line, 1 is a first source data line, and 12 is a second source data line.

(Problem to be solved by the invention) Immediately, in the context switch of register file 8 in the IE3 diagram, global registers, local registers,
In/out registers, floating in some cases? Saving or storing a large number of registers, such as intra-registers, takes time in proportion to the number of registers.

SUMMARY OF THE INVENTION Therefore, it is an object of the present invention to provide an information processing device that can increase the efficiency of register use and increase the effective time of use of the register.

[Structure of the Invention] (Means and Effects for Solving the Problems) The present invention provides: (1) an information processing device for arithmetic processing that processes a plurality of processes in time division or in parallel, which stores a plurality of process identifiers; The process identifier storage means can contain a certain number or more of current process identifiers and past process identifiers, and is configured to allocate registers to a plurality of processes overlappingly in time. This is an information processing device. Further, the present invention provides the information processing according to (1) above, characterized in that: (2) the information processing according to the above item (1) includes means for determining registers unique to a non-current process among the processes and sequentially selecting registers one by one; It is a device.

In other words, the present invention can be applied to CPUs operating in time division or in parallel.
Also, special registers are provided that contain identifiers of the current process (currently being executed) and non-current processes such as the last process before it.

Also, for this special register,
When a register file area is allocated, for a register file area that has already been allocated to the last process, etc., the task of selecting and saving a certain register is processed in the back ground. . At this time, a memory management mechanism for the last process is used so that it can be saved to the cache, main memory, disk, etc. Then dynamically fill the empty register with the next (next)
7' Allocate it to a non-current process such as the process. In this way, the above object is achieved as a result of the fact that background processing can be performed in a plurality of processes.

(Example) An example of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram of the same embodiment, and parts corresponding to those in FIG. 3 are given the same reference numerals.

tljJ1 In the figure, 20 is a register memory management unit, 21 is a destination. register address M
No. % 22 is the first source register address signal, 23 is the second source register address signal, 24 is the non-current process register address signal, 25 is the back ground data load/store data signal line, and 26 is the back ground This is a data load/store (evacuation) data node.

Here, unit 20 converts the register address of the current process (generating signals 21 to 23), generates the address of the non-current process register (signal 24), etc. The register file 8 has a structure in which registers of multiple processes (last process, current process, etc.) coexist. The data signal line 25 and data path 26 are used to save data in the last process register and connect
This is for loading data of the access v register. In FIG. 1, the instruction. When the signal is decoded, the unit 20 obtains the logical register address and information on whether to load/store the register to the background, and the unit 20 outputs the register address signals 21 to 23 for the current process and the register address signals 21 to 23 for the non-current process. Outputs register address signal 24. At this time, normal register access Iθ~12 by the current process
In addition, data is loaded/stored using the signal line 25 and path 26. In other words, registers unique to the non-current process are determined based on the address 24, and they are selected one by one in sequence, data is saved in the register of the last process, and data is loaded in the register of the next process.

FIG. 2 shows the register memory management unit 2.
This is a specific example of 0. In the figure, 50 is a process identifier storage means, 5 is a register resource control device, 52 is a register request control device, 53 is a used register management device, 54 is an unused register management device, 55 Fi. a used register address management device; 56 is an unused register address management device;
57 Current process register address generator, 5
8 is a non-current process register address generator fll
, s 9 is an unused register addition device, 60 is a register mounting device, ffLez is a current process register puncture address generation device, 62 is a non-current process register puncture address generation device, 63 is an unused register addition device, 64 is a register It is a punk mount device. The storage means 50 sends a current process identifier 71 and a non-current process identifier 72 to the device 5:5, also sends a register release request signal 79 to the device 52, and sends a register release request signal 75 to the device 51. From this, a release completion signal 76 is obtained. Device 55 sends an address signal 73 to device 57, from which it obtains a register logical address 92, and sends an address signal 82 to device 5J, and from device 56 obtains a register physical (real) address signal 8.
1 is obtained, and a resosta puncture release signal 87 is obtained from the device 59. The system fl57Fi% obtains the register logical address group 90 and sends out the register real address group 74 (corresponding to signals 21 to 23 in FIG. 2). Device 58 sends out register real address 9 (corresponding to address 24 in FIG. 2). The device 5 sends a register release request code 77 to the device 58 and also sends a free register addition request signal 78.
is sent to the device 56. Device 52 sends a register mount request signal 80 to device 60. The device 56Fi sends an empty register addition request signal 83 to the device 59, from which a real address signal 84 is obtained, and also sends a register puncture mount signal 86 to the device 60, from which a register puncture mount request signal 85 is obtained. Device 59 sends a register puncture release signal 87 to device 55 and also outputs a release error signal 88 to h. The device 89 sends and receives a mount error signal 89. In FIG. 2, Karen 1.1 identifier 7 has been input from the process identifier storage means 50 to the register management device 53 of the registers currently in use (including those other than the current process), and the address In the management device 55h, the real address 73 of the puncture is obtained for the logical address 92Vc in order to generate a physical address by inputting the register logical address group 90. This can be loaded in advance into the current process register puncture address generator e61. This and the lower bits of the register logical address give the register's physical address. In order to generate the physical address here, it is possible that it is some part of the physical address of the address and the register logical address. Address 90.74 is actually the address of the source register, destination register, etc. In the identifier storage means 50, an unnecessary derosse identifier (non-current process identifier 72) is stored as
When the register puncture release request signal 75 comes to the register release control device 51, the register release request signal 7
7 is the non-current process of the used register management device 53 (
Register address generation device 62 for R identifier 72 )
Sent to. At this time, the real address 91 is sequentially generated using the puncture address 82. At this time, the address signal
82 can be previously populated into the non-current process address generator 58.

These sequentially generated address signals 9 are input to the unused register adding device 59 of the unused register management device 54. At this time, an empty register addition request signal 78 is output from the register release control device 51, and an empty register addition request signal 8 is output from the unused register address management device 56.
3 is out.

At this time, the real address signal 84 registers the real address of the puncture in the unused register address management device 56, and the register puncture release signal 87 notifies that it has been registered in the unused register, and the used register management device 55
will be deleted from When all the addresses of the puncture unit are sent from the register address 9I, the error signal 8 is sent.
8 is sent. When a register is required for a non-current process, the register puncture request signal 7 is sent.
9 is sent to the register request controller 52. Similarly, the register mount request signal 80 is transmitted to the register mount device 60.
1/C sent. Register puncture mount request signal 85
is sent to the unused register management device 56. When then l punctures have been taken in the device 56, the register i4 link mount signal 86 causes the register mount device 60 to
In addition, the actual register puncture address is sent by the register physical address signal 81 and registered in the used register address management device 55. If the mounting is not successful, an error signal 89 will be output. According to the above-mentioned embodiment κ, register puncture registration for each process, abandonment, loading and storing of process data by path 26, address 9 address generation, etc. can be performed in the pack ground for the current process, while efficient Can perform calculations. Basically, the time required for the process switch described above can be made close to zero in terms of CPUVc.

[Effects of the Invention] As explained above, according to the present invention, the background processing in the multiple processes of the information processing device can be performed in an overlapping manner, so that the process switch (
This allows the time required for context switching to be minimized.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an embodiment of the present invention, FIG. 2 is a diagram showing a part of the same structure in more detail, and FIG. 3 is a block diagram of a conventional device. DESCRIPTION OF SYMBOLS 1... Instruction register, 2... Decoder, 8... Register file, 20... Register memory management unit, 25... Pack ground data load/store data signal line, 26... Pack Grand Data Loot 0/Store Pass. -zb Figure 1 Figure 2

Claims (2)

[Claims] (1) An information processing device for arithmetic processing that processes a plurality of processes in a time-sharing or parallel manner, and has means for storing a plurality of process identifiers, and the process identifier storage means includes an identifier of a current process and a past process. What is claimed is: 1. An information processing device that can include a certain number or more of identifiers, and has a configuration in which registers are allocated to multiple processes overlapping times. (2) The information processing apparatus according to claim 1, further comprising means for determining registers unique to a non-current process among the processes and sequentially selecting the registers one by one.