JPH02293983A - Eliminating method for fine grain in binary image - Google Patents

Abstract

PURPOSE:To eliminate fine grains caused by binarization, etc., by a hardware and to secure the high speed property of the subsequent processing by checking the connectivity extending from the center part to the outside peripheral part and changing a picture element in a prescribed range to a state that there is connectivity, when there is no connectivity. CONSTITUTION:Four masks I - IV having overlap parts which extend from the respective four corners of an inspection range constituted of (m + 2) X(n + 2) picture elements and superposed mutually in the center part of its inspection range are set, and one arbitrary picture element in the overlap part is set to a reference picture element. In this state, when any mask has no connectivity extending from the reference picture element to the outside periph ery, the picture element in the range of (m) X (n) of the center part is converted to a state that there is connectivity. When it is decided that each mask has no data connectivity to the picture element of the periphery, it is decided that the range of (m) X (n) centering around the reference picture element is fine grains generated by binarization. Therefore, by converting its part to a state that there is connectivity, fine grains whose size is less than (m) X (n) are eliminated. In such a way, high speed processing can be executed.

Description

[Detailed Description of the Invention] [Industrial Application Field] This invention provides a method for removing particulates in a binary image, which removes particulate matter (hereinafter referred to as particulates) from noise components mixed into a video signal. It is related to.

[Prior art] -a, when converting an image of an analog signal into a digital signal and importing it into a memory, the analog signal is converted into a digital signal by binarizing it and stored. Fine particles are likely to be generated at the time of binarization.These fine particle components may appear as dots in areas where there is no signal around, or may appear as holes in parts of areas that are displayed in a planar manner. Ru. If such particles can be removed in real time, subsequent processing speed can be increased.

As a method to remove points or holes of size 1 caused by the error using hardware, a 3 pixel x 3 pixel (hereinafter referred to as
A method has been proposed in which a binary image is scanned with a mask of 3×3, n×n, rnXm, m×n, etc., and removed in real time.

[Problem to be solved by the invention] However, if the size is larger than that, it is necessary to use methods such as repeatedly expanding and contracting with hardware or labeling with software and then determining the size and removing it. Therefore, it was difficult to remove it in real time.

[Means for Solving the Problems] In order to solve these problems, the present invention provides (m-t
-2) Set four masks that extend from each of the four corners of the inspection range consisting of One pixel is set as a reference pixel, and when there is no connectivity from the reference pixel to the outer periphery in any mask, the pixels in the m x n range in the center are converted to a state with connectivity. be.

[Operation] When it is determined that each mask has no data connectivity with surrounding pixels, the m×n range centered on the reference pixel is determined to be fine particles generated by binarization. Therefore, by converting that portion into a connected state, fine particles having a size of m×n or less are removed.

[Example] Fig. 1 is a circuit diagram of a device to which the present invention is applied, Fig. 2 is a circuit diagram showing the internal configuration of delay circuit B denoted by symbol 3 in Fig. FIG. 2 is a circuit diagram showing the internal configuration of a delay circuit C represented by symbols 41 to 48 in the figure. Figure 4 is a diagram to explain the range of particulate removal determination with this device.
A 5×5 range is shown as an example. With respect to this image, the pixel located at the coordinate C3 is used as a reference pixel, and it is determined whether the same data (L or 0) is connected from the reference pixel to the outer periphery. For this reason, as shown in FIGS. 5 to 8, 3×3 masks ① to M including the coordinate C3 are set at the four corners, and each of the ranges is investigated separately. In other words, in mask ■, the range is from row A to row C, and
Check whether columns 1 to 3 are connected.

FIG. 9 is a diagram showing, for example, a state in which masks I are connected, and FIG. 10 is a diagram showing a state in which they are not connected. In the figure, connectivity with respect to coordinate C3 is discussed, and the case where the same data is connected from coordinate C3 to A row or column 1 is defined as connected, and the case where it is not connected is defined as connected. Defined as a state in which there is no Figure 9 (a>
is locus aC3-83-A3 or CB-C2-82-
It is continuous on route A2. Figure 9(b) shows CB-83
-82-B L or C3-C2-B2-B Continuous on the path 1. FIG. 10 is an example in which the lines are not continuous in either row A or column 1.

Whether or not they are connected is determined for each mask, and this determination is made by supplying 3×3 pixel data to a determination unit prepared for each mask, for example, composed of a ROM or the like.

The determination unit stores 512 states of each pixel within a 3×3 range, and when input data is supplied to the determination unit as an address signal, comparison with data read out using the address signal is performed. It is designed to output the judgment result of whether to concatenate or not. Therefore, when pixel data such as those shown in Figures 9 (a) to (C) are supplied, it is determined that they are all connected, and data such as those shown in Figures 10 (a) to (C) are supplied. In some cases, the decision is made not to connect.

Once the judgment results for masks ① to ① are obtained in this way, the judgment results are then subjected to AND processing. If even one of the judgment results is connected, the image data at coordinate C3 is connected to the outer periphery, that is, row A, row E, column 1, or column 5, and can be considered to be regular data. ，
Furthermore, if the result is that they are not connected, there is a possibility that the data at coordinate C3 is an error. Therefore, when it is determined that all four masks are not connected and the level of the coordinate C3 is "IJ", all the 3x3 pixels in the center of the 5x5 are changed to the "O" level. Conversely, when the level of the coordinate C3 is "0", it is changed to the "1" level in the same way.

This process completes the removal of points and holes within the size of 3×3.

? However, when removing and filling the holes at the same time, if the stranded portion C3 becomes an isolated point as shown in FIG. 11, it becomes impossible to judge whether to remove that portion or fill the holes. In this case, only that pixel must be processed in advance. All pixels are shifted through the mask ■, so
If this processing function is provided to the mask (■), there will be no need to make a decision.

FIG. 1 shows an example of hardware for performing the above operations. In the figure, ■ is an input terminal to which image data is supplied, and symbols 2■ to 2 and 6 labeled as delay A are input terminals that temporarily converge the input signal by one bit in synchronization with a clock signal (not shown). It is a shift register that stores data (hereinafter referred to as
(referred to as delay circuit A). As shown in Figure 2, the circuit with symbol 3 labeled as delay B includes an inverter 3■, an AND circuit 3■
, an OR circuit 3, and a register 34, and acts as a circuit for removing undeterminable isolated points as described above in FIG. 11 (hereinafter referred to as extension circuit B).
．． Symbols 41-48 written as delay C? As shown in FIG. 3, the circuit is composed of an inverter 5, an AND circuit 52, an OR circuit 53, and a register 54, and it takes in only one bit of the input signal in synchronization with the clock signal, and as described above, it takes in only one bit of the input signal. According to the judgment result of mask ■,
The entire 3x3 pixel located in the center of 5x5 is r. I
It controls whether to change to the J level or to the "0" level (hereinafter referred to as delay circuit C).

Incidentally, the Roman numerals D to ■ written on each delay circuit indicate that the output of the delay circuit is supplied to the mask corresponding to the Roman numeral. In other words, this indicates that D is supplied to mask ■, and the * mark written in the output specifically represents this connection. 6. -64 are 1-line memories for temporarily storing data in the scanning line direction, and 7-74 are masks for determining whether or not the 9-bit data supplied to each mask is connected, as described above. When each mask is connected to the pixel at coordinate C3, both terminals a and b output signals at the "?" level regardless of the level at coordinate C3.

However, when it is not connected, the level of coordinate C3 is "1".
”, output an 11-level signal from terminal a,
Terminal b outputs a signal with a level of 0.Also, when not connected, the level at coordinate C3 is r.
(2), a "0" level signal is output from terminal a, and a "1" level signal is output from terminal b.

In addition, in mask l, when the center pixel data is "0" and all the surrounding pixel data are "1", a signal of "1" level is output from terminal C, and when the opposite is the case, a signal of level rQ is output. If the conditions are not met,
The output signal of the previous stage, that is, the pixel signal of the center portion of the mask f, is output to the terminal C as is. Symbols 8, , 8■ are AND circuits, and 9 is an output terminal.

If the above functions are summarized, the functions of masks 2 to 2 (mask 2 excluding terminal C) are as shown in Table 1.

When the level of the center pixel and the surrounding pixels adjacent thereto are the same, the level of the center pixel is output as is from the terminal C of mask (2) in Table 1, but when the levels are different, the output is as shown in Table 2.

Table 2 The operation of the device thus constructed is as follows. The image signal supplied to the input terminal 1 is taken into each delay circuit in synchronization with a clock signal, and the explanation will be given assuming that data is taken into all the delay circuits.

Each delay circuit output is applied to a predetermined mask. At this time, the reference for supplying the delay circuit output to each mask corresponds to the arrangement of each delay circuit in FIGS. 5 to 8. In other words, the nine delay circuits 2t to 2 near the left corner of FIG.
、． 26, 3, 4. , 28. 43+ 44 is a mask■
The same goes for the pond mask.

Masks f to mask (2) basically all have the same function, and only mask (2) also has an isolated point processing function, which will be described later. Register 3 of delay circuit B
The output of mask (2) is supplied to the mask (2), but if there is no isolated point, the signal is output as is from the output terminal (C) of the mask (2), so the delay B operates in the same way as the delay C.

Next, the operation in each state will be explained.

A. Behavior when there is connectivity between masks ■ and ■.

At this time, as can be seen from Table 1, one of the outputs of the four masks is at the "0" level regardless of the level of the coordinate C3. For this reason, the signals output from terminals a and b of each mask are supplied to AND circuits 8 and 9, respectively, but since at least one of the supplied signals is at "0" level, AND circuits 8 and 9
Both output signals are at the "0" level. Therefore, the AND circuits 32 and 52 in FIGS. 2 and 3 output the output of the register 34 or 54 as is. Therefore, if even one of the masks has connectivity, the signal from the second stage is output as is.

B. Behavior when all masks have no connectivity.

Image data generally has a low probability of being discontinuous, so 4
When all of the two masks have no connectivity, the coordinate C3 can be regarded as a particle. The processing at this time is performed separately for when the data at the coordinate C3 is at the "1" level and when it is at the "0" level.

Bl. Operation when the data at coordinate C3 is at "1" level In this case, each mask's terminal a to "1" level, terminal b
A signal of "0" level is output from. Therefore, the AND circuit 8 outputs a signal at the "1" level, but the AND circuit 82 outputs a signal at the "O" level. Among these signals, the [11 level signal is connected to terminal b of each delay circuit as "0".
” level signal is supplied to terminal C. As a result, the second
Since AND circuits 32 and 52 in FIGS. 2 and 3 output "0" level signals, terminals d in FIGS. 2 and 3 output "0" level signals.

That is, delay circuits B and C all output "0" level signals. Therefore, the data at coordinate C3 is “
1'' level, when it is determined that none of the masks 2 to M are connected to this data, it is determined that there is no relationship between the data at the coordinate C3 and the surrounding data. The fact that there is no relation to the surroundings means that the coordinate C3 is noise when converted into a binary value, and the central 3x3 part of the 5x5 is all converted to 01 level.In other words, it is a binary value. This means that the fine particles generated by oxidation have been removed.

B2. Operation when the data of seat WC3 is "0" level.

? When , each mask has a "0" level from terminal a, and a "0" level from terminal b.
Since a "1" level signal is output from the AND circuit 8l, the AND circuit 8l outputs a "0" level signal.
2 outputs a "1" level signal. The signal output from the AND circuit 8■ is the terminal C in Figures 2 and 3.
Therefore, the terminal d in FIGS. 2 and 3 unconditionally outputs a "1" level signal. This means 5×5
This means that the entire 3x3 area in the center of is changed to the "1" level. In other words, the data at coordinate C3 is "0"
If there is no connectivity with the surroundings at the level, the 3 x 3 part is 2
Since there is a high possibility that the particles were lost during digitization, if that part is filled in, the particulates during binarization will have been removed.

C. Behavior when there is an isolated point.

As mentioned above, an isolated point is one in which the data of a certain pixel is in a different state from that of the surrounding pixels, as shown by the thick line in FIG. In this case, all pixels surrounding the coordinate C3 within the thick frame are "0" or "1". As an explanation of the isolated point, in Fig. 11, C3, which is the center of 5 x 5,
However, the data for locus lfic3 is the first
In the circuit shown in the figure, as a result of sequentially shifting the input signals,
It has been shifted to that position. For this reason, the first
There must have been a time when the data 03 in Figure 1 passed through the coordinate B2. Therefore, when there is an isolated point, when the data in the state indicated by the thick line in Fig. 11 passes through the position of the mask ■,
If the data at the coordinate B2 in the center of the mask ■ is rewritten so that it is the same as the data for the pixels surrounding that pixel, no isolated point will occur even if the data is shifted to the position C3. It turns out.

The data of the coordinate B2 supplied to the mask 2 is different from the other coordinates and is the output signal of the register 34 in FIG.
For example, when an isolated point occurs in the mask ■, the coordinates B
The data of 2 is at the "0" level, and all surrounding data are "1"
When the level is high, a "1" level signal is output from the terminal C of the mask ■. Since this output signal is supplied to the terminal f in FIG. 2, even though a "0" level signal is supplied from the register 34, a "1" level signal is supplied to the AND circuit 52. become. The operations from here on are the same as those in FIG. Therefore, locus 1fiB2
Although the data is actually at the "O" level, the AND circuit 3z processes it as a "1" level and passes the processing result to the next stage. This means that the isolated point at coordinate B2 has been removed. Furthermore, when the data at the coordinate B2 is at the "1" level, a signal at the "0" level is output from the terminal C, so this is supplied to the AND circuit 32 and the isolated points are similarly removed.

In the above example, the entire pixel was explained as 5×5, so there was only one isolated pixel, but if the size of the pixel changes, the pixel size of the isolated point also changes as shown in Table 3. .

Table 3? Therefore, in reality, it is necessary to be able to process isolated points according to the overall pixel size. For this reason, the first
In the example shown in the figure, only one delay circuit B is provided, but the third
The number of delay circuits B that matches the size of the isolated point in the table may be provided. For example, if the size to be removed is 4x3, the isolated point will be 2x1, so in the example of Figure 1, both delay circuit 3 and delay circuit 4■ may be set as delay circuit B (However, Figure 1 shows the entire Since the size is 5×5, it is also necessary to change the overall size to 6×5.

In the masks r to M, for example, when mask ■ is used as a reference, masks ■ and ``are line symmetrical with the border of the third column as a boundary, and masks ■ and ■ are point symmetrical with the boundary of the pixel at coordinate C3. This means that one type of mask can be prepared, and data can be input into the mask using mask 1 as a reference, for example. For example, to explain the mask ■ and mask ■, in mask I, input terminals 1 to 9 are sequentially At, A2, A3, Bl, B2, B3, CL, C2,
When pixel data of C3 is supplied, in mask ■, A5, A4, A3, B5, B4, 83, C
It is sufficient to supply pixel data of 5, C4, and C3. In this way, the types of mask data can be reduced.

The above embodiment has been explained in terms of a 3 x 3 pixel range, but the point is that a mask is set that extends from each of the four corners of the inspection range and has overlapping parts that overlap each other in the center of the inspection range, and One arbitrary pixel is set as a reference pixel, and when there is no connectivity from the reference pixel to the outer periphery in any mask, pixels in an m×n range at the center may be converted to a state with connectivity.

[Effect of the invention 1 As explained above, this invention examines the connectivity from the central part to the outer peripheral part, and when there is no connectivity, changes the pixels in a predetermined range to a state where there is connectivity. This has the effect that fine particles caused by digitization can be removed by hardware, and subsequent processing can be performed at high speed.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is a circuit diagram showing details of delay circuit B in FIG. 1, and FIG. 3 is a circuit diagram showing details of delay circuit C in FIG. 1. , Figure 4 is 5×5
Figures 5 to 8 are diagrams showing the relationship between 5 x 5 pixels and masks ■ to ■. Figure 9 is a diagram showing the connection of masks ■, and Figure 10. is a diagram showing an unconnected state, and FIG. 11 is a diagram showing an isolated point. 1
...Input terminal, 2...Delay circuit A, 3...
Delay circuit B, 4...Delay circuit C, 6...1 line memory, 7...Mask, 8...AND circuit, output terminal.

Claims (1)

[Claims] In a method for removing fine particles in a binary image that removes fine particles when an image signal is binarized, an inspection consisting of (m+2)×(n+2) pixels, where m and n are integers. There is a range, and four masks are set that extend from each of the four corners of the inspection range and have overlapping parts that overlap each other in the center of the inspection range, and any one pixel of the overlap part is set as the reference pixel, and eventually A method for removing particulates in a binary image, characterized in that when the mask also has no connectivity from a reference pixel to the outer periphery, pixels in an m×n range in the center are converted to a state with connectivity.