JPH02292630A - Memory control circuit - Google Patents

Abstract

PURPOSE:To shorten the memory control time by disposing a signal generation circuit constituted of first-third conversion circuits which convert parallel data into serial data or serial data into parallel data and a counter circuit, etc. CONSTITUTION:The first conversion circuit 11 converts a command and an address with respect to EEROM 20 from parallel data into serial data Da, and supplies it to ROM 20 as input data Dc through an OR circuit 15. The second conversion circuit 12 converts data to be written into ROM 20 from parallel into serial data Db, and supplies it to ROM 20 as input data Dc through the circuit 15. The third conversion circuit 13 converts serial data Dd which is read from ROM 20 into parallel data and outputs it to a bus 30. The signal generation circuit 14 counts clocks by a counter circuit 140 and forms an enable signal, etc. Thus, the control load of an arithmetic processor, etc., using the memory can be reduced by allowing a memory control circuit 10 to convert serial data into paralled data.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a memory control circuit that writes and reads serial data, and particularly relates to a memory control circuit that reduces the control load on the memory of an arithmetic processing unit. .

[Conventional technology]

An example of this type of memory in which serial data is written and read is an electrically data-erasable read-only memory IJ (EEFROM) that can be used with serial data. Such serial type EEPROMs are used by arithmetic processing devices such as microprocessors. Here, when using an EEPROM, which is a serial type memory, the microprocessor executes a write process to convert parallel data to serial data when writing, and executes a series of processes to convert serial data to parallel data when reading. ing.

[Problem to be solved by the invention]

When using the above-mentioned conventional EEPROM, the microprocessor synchronizes the clock signal with the address and data for the EEPR○M, converts and writes data serially, and converts the read data in parallel for use. Therefore, there is a drawback that it takes a long time to use the EEPROM.

The present invention has been made in order to eliminate the above-mentioned drawbacks, and an object of the present invention is to provide a serial memory control circuit that shortens memory control time.

[Means to solve the problem]

The serial memory control circuit of the present invention converts commands and addresses for the memory from parallel data to serial data in a control circuit that can write and read data to and from a memory where data is input and output using serial data. A first conversion circuit that supplies data to the memory, a second conversion circuit that converts data to be written into the memory from parallel data to serial data and supplies it to the memory, and converts serial data read from the memory into parallel data and outputs it. 3rd to do
The present invention is characterized in that it includes a conversion circuit and a signal generation circuit that counts clocks and generates an enable signal and the like.

In the present invention, since the memory control circuit converts serial data to parallel data, it is possible to reduce the control load on an arithmetic processing device or the like that uses this memory.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a circuit diagram showing an embodiment of the memory control circuit of the present invention.

The memory control circuit 10 shown in FIG.
Data can be written to and read from 0, and the first conversion circuit 1l and the second conversion circuit 1
2, a third conversion circuit 13, and a signal generation circuit 14.

Further, the memory control circuit 10 is connected so that human power information from the bus 30 can be supplied to the first conversion circuit 11 and the second conversion circuit 12, and output information can be supplied to the bus 30.

Here, the first conversion circuit 11 converts the command and address for the EEPROM 20 from parallel data to serial data D.
Convert it to EEPROM20 as manual data Dc.
can be supplied through the OR circuit l5. The second conversion circuit 12 converts the data to be written into the EEPROM 20 from parallel data to serial data Db, and outputs the data to the EEPROM 20 as manual data Dc using an OR circuit l.
It can be supplied via 5. The third conversion circuit 13 is configured to convert the serial data Dd read from the EEPROM 20 into parallel data and output it to the bus 30. The signal generation circuit l4 is a counter circuit 14
0 and a clock generating circuit l4l, the counter circuit 140 counts the clocks and generates an enable signal EN.
a, ENbENc, etc. can be formed. In addition, the clock signal (CLK) of the clock generation circuit 141
is connected directly to the EEPROM 20 and the counter circuit 140, to the first conversion circuit 11 via the OR circuit 16, to the second conversion circuit 12 via the OR circuit 17, and to the third conversion circuit 13. can be supplied to each via the OR circuit l8. In addition, Light Ichiburu WE
a, 'vVEb, and WEc are supplied to the first conversion circuit l1, the second conversion circuit l2, and the signal generation circuit 14. Further, the third conversion circuit 13 is supplied with a signal ○E. Furthermore, the first conversion circuit 1l and the second conversion circuit l2 may be configured as parallel-to-serial conversion circuits. Further, the third conversion circuit l3 may be configured by a serial/parallel conversion circuit.

The operation of the embodiment configured in this way will be explained.

FIG. 2 is a timing chart when data is written to the EEPROM 20 according to the same embodiment.

As shown in FIG. 2, a clock pulse signal (CLK) is output from the clock generator circuit 141. Here, when the enable signal ENa (ENB) becomes "o" (after the fall of the clock signal T) and at the same time (To), the enable signal ENb of the counter circuit 140 becomes "0", the first conversion circuit Command (
C OM ) and address (A.'''''A3) are given. As a result, the manual terminal DI of EEFROM20
As shown in FIG. 2, serial data Dc such as an address signal is applied to N via an OR circuit 15 (T o
"'- T s). Then, since the enable signal ENc from the counter circuit 140 becomes "0", data (Do = Di) is input to the input terminal DI of the second conversion circuit l2.
is given (T6 ~”r,.). This gives EE
The PROM 20 is supplied with manual data Dc as write data via the OR circuit 15 as shown in FIG. This will be written into the EEPROM 20.

FIG. 3 is a timing diagram when data is read from the EEPROM 20 according to the same embodiment.

As shown in FIG. 3, a clock signal (CLK) is output from a clock generation circuit 141. Here, the enable signal ENa (ENB) becomes "0" (from the fall of the clock signal T. to T3), and at the same time (To), when the enable signal ENb of the counter circuit 140 becomes "0", the first A signal is applied to the human power terminal DI of the conversion circuit 11.

As a result, the input terminal DIH of the EEPROM20 is given serial data Da as an address signal via the OR circuit 15 as shown in FIG.
To "Ts). Then, the enable signal ENc from the counter circuit 140 becomes "0", so EEFRO
Data from output terminal DOUT of M20 (DO ~ Dt)
is read out as serial data Dd (T6 to T13)
. As a result, the third conversion circuit l3 converts the DIN of FIG.
The data (Do-D7) output from
Output to 0.

〔Effect of the invention〕

As explained above, in the present invention, the memory control circuit
Since serial data/parallel data is converted, there is an effect that the control load on the arithmetic processing unit, etc. that uses this memory can be reduced.

[Brief explanation of drawings]

Fig. 1 is a circuit diagram showing an embodiment of the present invention, Fig. 2 is a timing diagram when data is written to the memory according to the same embodiment, and Fig. 3 is a timing diagram when data is read from the memory according to the same embodiment. be. 0...Memory control circuit, l...First conversion circuit, 2...Second conversion circuit, 3...Third conversion circuit, 4...Signal generation circuit. 20...EEPROM (memory),? )2 figure

Claims (1)

[Scope of Claims] A control circuit capable of writing and reading data to and from a memory in which data is input and output using serial data, the control circuit converting commands and addresses for the memory from parallel data to serial data and supplying the converted data to the memory. a first conversion circuit that converts data to be written into the memory from parallel data to serial data and supplies the converted data to the memory; and a second conversion circuit that converts the serial data read from the memory into parallel data and outputs the converted data. 1. A memory control circuit comprising: a third conversion circuit that counts clocks and generates an enable signal and the like;