JPH04336346A - Memory access system - Google Patents

Abstract

PURPOSE:To expand memory capacity with the same software by processing operation bits, address bits, and data by specific bit respectively. CONSTITUTION:When one address of an EEPROM consists of 16 bits, the address should be synchronized with a clock signal at the time of input from a serial input terminal 11. Then eight clocks from the beginning are prescribed as operation bits. Following eight clocks are prescribed as address bits. Further, following eight bits and eight bits following them are prescribed as data. A function for 'write' is executed and the input data are stored in a memory array 7. When a function for 'read' is executed, the input signal consists of an address bit following the operation bits and data in the memory array 7 corresponding to an address as the input signal inputted in synchronism with the clock signal from the serial output terminal 12 is outputted.

Description

[Detailed description of the invention]

0001

[Industrial Field of Application] The present invention relates to an EEPROM (El
electrically Erasable and
Programmable Read Only M
This is related to the memory access method of ``emory''.

0002

2. Description of the Related Art In recent years, the field of application of semiconductor ICs has been expanding, and in particular, the progress of products based on one-chip microcomputers has been remarkable. In this context, the role of EEPROM, which is used as a component with microcomputers, is gradually becoming larger. EEPROM requires a relatively high voltage to be applied to the memory cells, so
In the early days, a dedicated high-voltage terminal was required, but recently, by incorporating a booster circuit, it has become possible to operate with a single power supply, and it is being used in a variety of fields.

However, (especially in the consumer field) the data stored in the EEPROM in the system still has a capacity of about 1K bits to 2K bits, and more importantly, in order to reduce the burden on the microcomputer, The goal is to reduce the number of interfaces as much as possible. Therefore, E with serial input/output
EPROM will naturally become a required specification.

FIG. 4 shows a conventional serial input/output type EEPRO.
FIG. 2 is a block diagram showing the configuration of M. In FIG. 4, 1 is a start timing circuit that outputs a processing start timing signal, 2 is a timing circuit that generates a timing signal (clock signal) to each component, and 3 is a function operation mode for writing or reading data. 4 is an address register that stores address bits indicating the address to which data is to be written or read; 5 is a data register that stores data; 6 is a mode register 3 and a data register 5; Sense circuit that amplifies the output; 7 is a memory array that stores data; 8
is a decoder that decodes the output of address register 4,
11 is a serial input terminal to which operation bits, address bits, data, etc. are serially input; 12 is a serial output terminal to which data is serially output; and 13 is a clock terminal to which a clock signal is input.

FIG. 3 shows the serial input/output type EEPRO shown in FIG.
FIG. 3 is a waveform diagram showing the function operation mode of M.

Next, the operation of the conventional example will be explained with reference to FIGS. 3 and 4. The basic functional operation modes of EEPROM are "reading" and "writing".
etc., but in order to recognize them, one start bit is first inputted from the serial input terminal 11 as an input signal. Next, input the operation code that determines the basic function operation mode to the serial input terminal 11.
Input 2 to 4 bits from . These start bits and operation bits are input in synchronization with the rising or falling edge of the clock signal. The start bit is input to the start timing circuit 1, drives the start timing circuit 1, and generates a timing signal (clock signal) from the timing generation circuit 2.
to occur. Further, the operation bit is stored in the mode register 3.

Next, an address is input as an input signal from the serial input terminal 11. For example, if the ROM capacity is 102
If it is 4 bits (if one address of the EEPROM has a 16-bit configuration), 6 bits of the address are input as shown below.

When the operation bit indicates "read", the data is transferred from the memory array 7 to the data register 5 and then to the serial output terminal 1 in synchronization with the rising or falling edge of the clock signal after the above processing.
2 is serially output as output data. When the operation bit indicates "write", data is further input from the serial input terminal 11 as an input signal following the address. The data is then stored in the memory array 7. Note that when inputting an address or data, the LSB and MSB of the bits may be reversed.

[0009]

[Problem to be Solved by the Invention] By the way, if the conventional operating specifications as mentioned above are used, the EE
If you try to expand the PROM capacity (for example, from 1K bits to 2K bits), the number of bits at the address shown above will increase, and the property of the software (program) created with the 1K bit capacity will be lost. There was a problem that it could not be used.

The present invention was made to solve the above-mentioned problems, and it is a storage device such as a serial input/output type EEPROM that has software compatibility even when memory capacity is expanded. The purpose is to provide a memory access method.

[0011]

A memory access method according to the present invention processes operation bits, address bits, and data for each predetermined bit.

0012

[Operation] Since operation bits, address bits, and data are each processed with the same number of bits, software compatibility can be achieved with expansion of memory capacity.

[0013]

Embodiment FIG. 2 is a block diagram showing the structure of a serial input/output type EEPROM employing a memory access method according to an embodiment of the present invention. In FIG. 2, components corresponding to those shown in FIG. 4 are designated by the same reference numerals, and their explanations will be omitted. In FIG. 2, 9 is an input buffer circuit for each input of the mode register 3, address register 4, and data register 5, and 10 is an output buffer circuit for the output of the sense circuit 6.

FIG. 1 shows the serial input/output type EEPRO shown in FIG.
FIG. 3 is a waveform diagram showing the function operation mode of M.

Next, the operation of this embodiment will be explained with reference to FIGS. 1 and 2. What we will explain here is EEP
This is a case where one address of the ROM has a 16-bit configuration. When inputting an input signal from the serial input terminal 11, it must be synchronized with a clock signal. FIG. 1 shows an example in which the input signal is synchronized with the rising edge of the clock signal. Eight clocks from the beginning are defined as operation bits. The next eight clocks are defined as address bits. and then the next 8 bits and the next 8 bits
Bits are defined as data. In the example described above, the function "write" is executed and the input data is stored in the memory array 7.

When executing the "read" function, the input signals are up to the address bit following the operation bit, and the memory array corresponding to the address as the input signal input from the serial output terminal 12 in synchronization with the clock signal is input. 7 data is output as output data.

Since the bits corresponding to the address are 8 bits, they are input as follows, for example. If input in this way, it will indicate an EEPROM of 64 addresses * 16 bits. Therefore, considering this, 2 to 256 addresses can be expressed with the same 8 clocks, and all input signals have compatibility on software (programs).

[0018] In the above embodiment, processing is performed every 8 bits, but the number of bits is not limited to 8 bits and may be any other number of bits. For example, if you perform 4-bit processing (if one address is 16 bits)
2 addresses to 16K addresses can be processed with the same number of clocks, and if 16 bit processing is performed, 2 addresses to 64K addresses can be processed.

[0019]

[Effects of the Invention] As described above, according to the present invention, since the operation bit, address bit, and data are processed for each predetermined bit, the memory capacity can be expanded using the same number of clocks, that is, the same software. , Therefore, it is possible to easily change the system.

[Brief explanation of drawings]

FIG. 1 is a waveform diagram showing functional operation modes of a serial input/output type EEPROM using a memory access method according to an embodiment of the present invention.

FIG. 2 is a block diagram showing the configuration of an EEPROM according to this embodiment.

FIG. 3 is a waveform diagram showing functional operation modes of a serial input/output type EEPROM using a conventional memory access method.

FIG. 4 is a block diagram showing the configuration of an EEPROM according to this conventional example.

[Explanation of symbols]

11 Serial input terminal 12 Serial output terminal 13 Clock terminal

Claims (2)

[Claims] Claim 1: In synchronization with a clock signal, an operation bit that determines a function operation mode for writing or reading data, and then an address bit indicating an address to which data is to be written or read are serially connected to a serial input terminal. In a storage device configured to input data to the serial input terminal when writing, and output data from the serial output terminal when reading, the operation bit, the address bit, and the data are input. A memory access method characterized in that processing is performed for each predetermined bit. 2. The memory access method according to claim 1, wherein the predetermined bits to be processed are 1 to 16 bits.