JPS62250598A - Integrated circuit device - Google Patents

Abstract

PURPOSE:To reduce the data write time on an EPROM cell by providing a write means for writing simultaneously plural data from an input terminal to different addresses. CONSTITUTION:An address signal of an address (even-number address) to be written is applied to address signal input terminals A0, A1-A12 in an integrated circuit device incorporating a read-only memory (EPROM). The data signal to be written on the said addresses is applied to the 1st data signal terminals D0, D1-D7, a data signal written on an address increased by 1 from the said addresses is applied respectively to the 2nd data signal terminals D8, D9-D15. When an output L is applied to a write signal terminal PGM, a write circuit 141 reads the data of the 1st data signal terminals D0, D1-D7 via the 1st data signal input/output circuit 19 and a data signal line 20, written on the EPROM cell of an even-number address through a signal line P0, a write circuit 140 reads the data of the 2nd data signal terminals D8, D9-D15 via the 2nd data signal input circuit 21 and a data signal line 22 and written on the EPROM cell at the said even number + 1 address through the signal line P1.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an integrated circuit device, and particularly to an integrated circuit device incorporating an E F ROM.

[Conventional technology]

In recent years, the capacities of both single-chip micro combinators with built-in EPROMs and single FiFROMs have been increasing. Writing and reading of a conventional EPROM is performed using the configuration shown in FIG. FIG. 4 is a block diagram showing an example of a conventional integrated circuit device, in which an 8-byte EPROM cell array 41 and a row selection circuit (hereinafter referred to as an ) 42 and EP OM cell array 41
Column selection circuit (hereinafter referred to as Y decoder) 4 that selects the column of
3, the write/read circuit 44, and the address signal terminal A0. A
,~A.I.

, an address signal input circuit 45 , an address signal line 46 from the address signal input circuit 45 to the X decoder 42 ,
Address signal line 47 to Y decoder 43, data signal terminals (8 bits: 1 byte) Do, D, ...D, data signal input/output circuit 48, write/read circuit 44, and data signal input/output circuit 48 and a source terminal Vpp.

Next, the operation of this conventional example will be described with reference to FIG. 5 showing the write/read waveforms in FIG. 4. A high voltage, for example 21', is applied to the power supply terminal VPP, and the read signal terminal OB
, the input signal terminal PGNL has a logical value @1'' (hereinafter referred to as H). In this state, the write/read circuit 44 does not operate, and the data signal input/output circuit 48 is in an input state. For writing, address signal terminals A., A3. to A
1H to the address signal, data signal terminal D0. D.
, ~D7 respectively. When a logical value "01" (hereinafter referred to as "01") is applied to the write signal terminal PGM (while the read signal terminal OE remains applied with H), the write/read circuit 44 operates and the X decoder 42 and the X decoder 43 The address signal is decoded and the data is stored in the selected cell via the data signal input/output circuit 48.For reading, the write signal terminal PGM changes the H9 read signal terminal OE from H to L. The read circuit 44 starts the read operation,
The data signal input/output circuit 48 is set to an output state, and the X decoder 42 and the X decoder 43 decode the address signal and output the contents of the selected cell to the data signal terminal via the data signal line 49. , D7. Output to ~D.

[Problem that the invention seeks to solve]

In writing to the conventional EPROM described above, data is written to each address one by one. Since it takes a maximum of 50 m5 ec to write one piece of data, there is a drawback that it takes a very long time to write data to all addresses of an EPROM cell in the current situation where the capacity of EPROM has increased.

The present invention solves this problem, shortens the time to write data to all EPROM cells, and makes the GF more convenient to use.
An object of the present invention is to provide an integrated circuit device incorporating a ROM.

[Means for solving problems]

An integrated circuit device incorporating an EPROM according to the present invention includes an address signal input terminal, a decoder that decodes the address signal, a selection circuit that selects the EPROM cell based on the output of the decoder, and a plurality of data signal input terminals. It includes a plurality of write circuits and a write means for simultaneously writing a plurality of data from the data signal input terminal to different addresses.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram of an embodiment of an integrated circuit device of the present invention. This embodiment shows an example in which two pieces of data are written simultaneously.

In FIG. 1, reference numeral 11 is an E F ROM cell array, 12 is an X decoder, 13 is an X decoder, 14 is a write/read circuit, Ao, A, . . . -A1. are address signal input terminals, 15 is an address signal input circuit, 16.17.
18 is an address signal line, and 16 is the lowest address signal line, that is, the signal line of the address signal input terminal A0, which is input to the write/read circuit 14. Address signal line 17
is connected to the X decoder 13, and the address signal line 18 is connected to the X decoder. Also, reference numeral D0. Dl, ~D, are first data signal terminals, D, , Do, ~D1. is the second
19 is a first data signal input/output circuit, and 20 is a data signal line. Furthermore, reference numeral 21 is a second data input circuit, 22 is its data signal line, and the power supply terminal VPP is the same as that described in the conventional example.

The address signal line 16 inputs the lowest address signal to the write/read circuit 14, and the address signal line 17 to the X decoder 13 has one bit less than the address signal a47 in the conventional example, so the X decoder 12 and the 13
Two cells corresponding to two addresses are selected by. Connect the signal lines connecting these two cells to Po
,P,.

FIG. 2 is a circuit diagram showing an example of the write/read circuit shown in FIG. 1, and shows one bit for convenience.

In FIG. 2, write/read circuit 14 includes write circuit 140 .
141, readout circuit 142, NOR gates (hereinafter referred to as N) 143, 144, and field effect transistors (hereinafter referred to as T).
) 145, 146, and the signal line P. +PI is selected.

Next, FIG. 3 is a waveform diagram showing the write/read waveforms in FIG. 1.

Next, the operation of this embodiment will be explained using FIGS. 1 to 3.

Address signal input circuit person. , AI, -Apply the address signal of the address to be written (an even address) to Al1. The data signal to be written at this address is sent to the first data signal terminal, , D, , ~D, and the data signal to be written to the address +1 from the above address is sent to the second data signal terminal, ,
Apply to D, , to D□, respectively.

Since the read signal terminal og is at H, the outputs of both N143 and 144 are L, and T145 and 146 are off.

In the cells selected by the X decoders 12 and 13, the even address is connected to the signal line r0°, and the address obtained by adding 1 to the even address is connected to the signal line P1. Write signal terminal P
When G zdKL is applied, the write circuit 141 reads the data of the first data signal terminal D0゜Dl, ~D, via the first data signal input/output circuit 19 and the data signal line 20, and writes the data to the signal line P, all even address EPR (M cells are written, the write circuit 140 is the second data signal terminal, D, ~DIfi data is written to the second data signal input circuit 21 and the data signal line 22, and write it into the BFROM cell at the even address +1 address through the signal line P1.In this way, two pieces of data can be written to each address.Reading is different from writing, in which each address is Then, the contents of BPROflvl are outputted to the first data signal terminals D0.D, , ~D, via the first data signal input/output circuit 19.

The address is decoded by the X decoder 12. X decoder 13
and address signal line 16. N143,144°T145
, 146. J- to read signal terminal OE
If applied, the readout circuit 142 operates to read the selected E.
The contents of the P ROM cell are transferred to the first data signal terminal D0.
D, ,~D? is output to. First even address, then +
The address signal of the address that is set to 1 is applied and read out.

〔Effect of the invention〕

As explained above, the present invention allows two pieces of data to be written to different addresses at the same time, so that the writing time is reduced to half that of the conventional method. A single-chip microcomputer with a built-in EPROM has a large number of input/output terminals, but simply adding a write circuit has a great effect in shortening the write time with almost no additional hardware.

Note that if there is sufficient input/output terminal space, a write circuit can be added to shorten the overall write time.

[Brief explanation of drawings]

FIG. 1 is a block diagram of an embodiment of the integrated circuit device of the present invention, FIG. 2 is a circuit diagram showing an example of the write/read circuit in FIG. 1, and FIG. 3 shows the write/read waveforms in FIG. FIG. 4 is a block diagram showing an example of a conventional integrated circuit device, and FIG. 5 is a write/read waveform diagram in FIG. 4. 11.41...EPROM cell array, 12.
42...X decoder, 1143...X
Decoder, 14.44°°°°...Writing/reading circuit, 15
．． 45... Address signal input circuit, 19, 21
．． 48...Data signal input/output circuit, 140,1
41...Writing circuit, 142--Reading circuit, 143, 144...Nor gate (N), 1
45,146...Field effect transistor (T)
. Agent Patent Attorney Susumu Uchihara -1, -2゛

Claims (1)

[Claims] In an integrated circuit device incorporating a writable and erasable read-only memory (hereinafter referred to as EPROM), an address signal input terminal, a decoder that decodes the address signal, and a selection circuit that selects the EPROM cell based on the decoder output. An integrated circuit device comprising: a plurality of data signal input terminals; a plurality of write circuits; and a write means for simultaneously writing a plurality of data from the data signal input terminals to different addresses.