JPH02292613A - System and circuit for generating n-fold period clock and information processing system - Google Patents

Abstract

PURPOSE:To generate an N-fold period clock at the part of a logical circuit by generating the N-fold period clock having other phase using two phases of the whole phases of a basic clock and the phases of the N-fold period clock and subtracting the supply number of the N-fold period clocks. CONSTITUTION:A timing and a period when a basic stage signal K20 comes to a high level is decided by an exclusive OR at the timing of clocks T20 and T24 irrespective of the initial values of one bit counters CNTA and CNTB. Shift stage signals K21-K27 which are obtained by sequentially shifting the phases by one phase difference of the basic clock CLK by FF21-27 are generated based on the signal K20. An AND part 13 receives the total phase stage signals STG consisting of the signals K20-K27 and the basic clocks T0-T3. Consequently, respective AND circuits A20-A27 take the AND of two input signals and generate output two-fold period clocks T20-T27.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a clock generation method for a clock synchronous electronic circuit, and in particular, it is possible to reduce the number of N times cycle clocks supplied from a clock oscillation circuit as much as possible, and to The present invention relates to a system and a circuit capable of generating a clock with a period N times as long as all phases.

[Prior Art] Conventionally, in a clock synchronous electronic circuit, in addition to the basic clock from a clock oscillation circuit, a clock with a period N times the basic clock may also be required.

For example, when connecting a device with the latest technology that operates with a high-speed basic clock to a device with existing technology that operates with a clock N times the period of the basic clock (for example, the former is a newly designed memory control device and the latter is In the case of a pre-designed memory device), in order to exchange appropriate data with the latter device, the former device is generally provided with an M× It is necessary to supply an N-phase clock with N times the period.

A general method for supplying this N-times period clock is to use a clock distribution system similar to that of the basic clock to generate an N-times period clock of M×N phases from a clock oscillation circuit, and use the same clock distribution system as the basic clock to generate the N-times period clock. (hereinafter referred to as the first method).

Another method is to generate an N-time period clock from the basic clock by combining the outputs of shift registers initialized in the logic circuit, without the need to supply the N-time period clock from the clock oscillation circuit (hereinafter referred to as Two methods are known.

This type of system is disclosed, for example, in Japanese Patent Laid-Open No. 179814/1983.

[Problems to be Solved by the Invention] In the first conventional method described above, there is a problem in that it is necessary to supply all phases of the N times cycle clock as well as the basic clock, which places a heavy burden on the clock oscillation circuit and the clock distribution system. In other words, while the degree of integration of LSIs has increased due to advances in semiconductor technology, the degree of integration of LSIs has increased. The number of LSI pins and the degree of integration of cables, etc., have not increased so much, and as mentioned above, increasing the number of clock supply phases is due to the clock oscillation circuit and clock distribution system (cable wiring, clock receiving logic LSI, etc.)
This will increase the burden on people.

On the other hand, the conventional second method does not require the N times period clock supply from the clock oscillation circuit, so it is an effective method without the above problems, but it requires multiple parts that generate the N times period clock and needs to be distributed. No consideration has been given to such cases (such as large-scale computer systems), and a synchronization preset is required for clock synchronization control between each logic circuit.

However, in order to simultaneously preset a plurality of distributed logic circuits, special control means is required that takes into account variations in preset signal propagation.

In addition, when considering dynamic reconfiguration such as system maintenance or reorganization, partial power off/on is required, but when repowering on the parts that have been powered off, synchronization of the N times cycle clock is required. Therefore, it is necessary to re-reset the moving parts as well, which is a problem.

An object of the present invention is to reduce the number of N times cycle clock supply phases from a clock oscillation circuit to two phases, use a simple circuit, and do not require clock synchronization control between each logic circuit part. An object of the present invention is to provide an N times period clock generation method, a circuit, and an information processing device that can generate all phases of a period clock in each logic circuit part.

[Means for Solving the Problems] In order to achieve the above object, the N times period clock generation circuit according to the present invention includes a plurality of phase basic clocks and a plurality of phases N times period clocks having N times the period of the basic clock. A method for generating an N times period clock in a device using
In the device, based on all phases of the basic clock and two phases of the N-time period clock, at least an N-time period clock having a phase other than the two phases is generated.

From another point of view, the N-times clock generation method according to the present invention generates a clock of any phase among all M×N phases of N-times period clocks having a period N times that of the M-phase basic clock. An N times period clock generation method, based on the two phases of the N times period clock and the basic clock,
A clock having an arbitrary phase of the above-mentioned N times period clock is generated.

According to another aspect, the N-times clock generation method according to the present invention includes an M-phase basic clock and an N-times clock generation method of the basic clock.
An N-time period clock generation method that generates an N-time period clock of M×N phases based on two phases out of all M×N phases of an N-time period clock having a double period, the two-phase , the one having a phase difference of one period of the basic clock is selected, and the basic clock 1 is selected based on the two phases.
A basic stage signal having a pulse width corresponding to a period and a period N times that of the basic clock is generated, and the stage signal is sequentially shifted in units of phase difference of the basic clock to generate an M×N phase signal including the basic stage signal. generate a stage signal of
By performing the logical product of each stage signal of the M×N phase and the corresponding phase of the basic clock, an N times clock signal of the M×N phase is obtained.

Also. The N-time period clock generation circuit according to the present invention is an N-time clock generation circuit that generates a clock of an arbitrary phase among all M×N phases of the N-time period clock having a period N times that of the M-phase basic clock. and generates a basic stage signal having a pulse width including one pulse of the basic clock and a period N times that of the basic clock, based on two phases of the M×N phases of the N times period clock. a basic stage signal generating means, and a basic stage signal outputted by the basic stage signal generating means to one of the basic clocks;
The stage signal shifting means generates a plurality of shift stage signals phase-shifted in units of phase difference, and the logical product means performs a logical product of the specific stage signal and the basic clock of a specific phase.

In this N-time period clock generation circuit, the basic stage signal generation means includes, for example, a first holding means that holds a 1-bit input at a clock timing of one phase of the N-time period clock, and a J-th holding means. a second holding means for holding the 1-bit output at a clock timing of a different phase of the N times cycle clock; and an inverting means for inverting the 1-bit output of the second holding means and supplying it to the first holding means; and exclusive OR means for outputting the exclusive OR of both 1-bit outputs of the first and second holding means as the basic stage signal.

An information processing system according to the present invention is an information processing system including a device using an M-phase basic clock and a multi-phase N times period clock having a period N times that of the basic clock. A double period clock generation circuit is built in, and a clock oscillation circuit for generating all phases of the basic clock and two phases of the N times period clock to be supplied to the device is provided outside the device.

Another information processing system according to the present invention is an information processing system including a plurality of devices using an M-phase basic clock and a plurality of phases and N times the period clock of N times the period of the basic clock. Each of them has a built-in N times period clock generation circuit according to claim 3, and all phases of the basic clock and the N
A clock oscillation circuit is provided that generates two phases of a double-period clock and supplies them to each of the above devices.

The stage signal generation circuit according to the present invention has a total of M×N clocks with N times the period of the M-phase basic clock.
A stage signal generation circuit for an N-times period clock generation circuit that generates at least an N-times period clock other than the two phases based on two of the phases, the clock timing of one phase of the N-times period clock. So 1. a first holding means for holding a bit input; a second holding means for holding the 1-bit output of the first holding means at a clock timing of another phase of the N times cycle clock; and 1 bit of the second holding means. an inverting means for inverting the output and supplying it to the first holding means; an exclusive ORing means for outputting an exclusive OR of both 1-bit outputs of the first and second holding means as a basic stage signal; The stage signal shifting means generates a plurality of shift stage signals obtained by phase-shifting the basic stage signal outputted from the exclusive OR means by one phase difference unit of the basic clock.

[Function] According to the present invention, the problems of the first method of the prior art described above can be solved as follows.

Now, for the basic clock with phase number M = 4, double period (
When N=2) clocks are required, the number of N times cycle clock supply phases is M×N=8 in the first method, whereas in the present invention, “2” is sufficient. That is, the difference in the number of supplied phases is 8-2 = "6", and if the number of supply destination logic circuits is n, then the present invention reduces the number of clock supply phases by N times by 6Xn compared to the first method. be able to. This difference further increases as the number of phases M or the multiple N of the basic clock increases.

Therefore, regardless of the values of M and N, according to the present invention, where the number of N times period clock supply phases is tl 2 I+, it is possible to reduce the burden on the clock oscillation circuit and the clock distribution system as much as possible.

Furthermore, the problems of the above-mentioned conventional second method can also be solved as follows.

Each logic circuit section equipped with the N times period clock generation circuit of the present invention is directly synchronized with the N times period clock supplied from the clock oscillation circuit, and exclusive OR is used for clock generation. There is no need to consider the initial value of the generation circuit, and even if multiple logic circuit parts are distributed, it is easy to synchronize all the logic parts between each logic part without special clock phase synchronization control like the preset signal of the second method. A clock with a period N times the phase can be generated.

Therefore, even when the power is turned on again after a partial power-off due to dynamic reconfiguration or the like, the power can be turned on again without any procedure or circuit for clock synchronization.

(Hereinafter, blank space) [Embodiments] Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

FIG. 1 shows an embodiment of an N times period clock generation circuit according to the present invention. Now, the basic clock 4-phase (To-T3),
N=1: Then, the double period clock has all 8 phases (T2
0-T27).

This circuit is a clock oscillation circuit (see Figure 6 below)
From basic clock (CLK) all phases To~T3 and 2
Two phases of double cycle clock (NCLK) T20, T24
a stage signal generation unit 11 that generates an 8-phase stage signal STG in response to the stage signal STG; and a stage signal generation unit 11 that generates an 8-phase stage signal STG; Logical product part 1
It consists of 3.

The stage signal generation unit 11 includes two 1-bit counters (that is, flip-flops) CNTA and CNTB connected in series, and inverts the output of CNTB to generate CNT.
An inverter INV inputting feedback to A, an exclusive OR circuit FOR receiving the outputs of both 1-bit counters, and this E
It consists of Fritsop flops F21 to F27 that generate shift stage signals K21 to K27, respectively, in which the phase of the basic stage signal K20 outputted from the OR is sequentially shifted by one phase difference of the basic clock.

A double cycle clock T20 is applied to CNTA as its clock input, and a double cycle clock T24 is applied to CNTB as its clock input. Also, F21, F22, F23, F24, F25, F26
, F27 have basic clocks Tl, T2, T3, respectively.
, To, Tl, T2, and T3 are applied. In this example,
CNTA. CNTE, INV and EOR constitute means for generating the basic stage signal K20, and F21 to F27
constitutes means for shifting the basic stage signal K20.

The AND section 13 includes eight AND circuits A21 to A27 corresponding to the total number of phases of the double period clock. These AND circuits A21 to A27 are respectively (K2-0, T2), (K21, T3),
(K22, TO) , (K23, Tl) , (K2
4,T2) , (K25,T3) , (K26,T
o) , (K27, TI) and outputs double period clocks T22 to T27, T20, T21.8 FIG. 2 shows the waveforms of each part of the circuit in FIG. 1.

As shown in the figure, the basic clocks TO to T3 are sequentially 9
These are signals whose phases are shifted by 0 degrees. In addition, the input double period clocks T20 and T24 both have twice the period of the basic clock, but the phase of the clock T24 is
It is delayed by one period of the basic clock from the phase of 20. The CNTA in FIG. 1, which receives the clock T20 as a clock signal, outputs the INV output (
On the other hand, CNTB, which receives clock T24, takes in the output of CNTB at the clock timing. Therefore, C.N.
As shown in FIG. 2, the outputs of TA and CNTB both have a period twice that of the double period clock, and the outputs of C
The phase of the NTB output is delayed by one period of the basic clock from the phase of the CNTA output. At the rising time of clock T20, CNTAf. CNTB, the stage signal K20 which is the output of the exclusive OR circuit FOR is 11.
', and since CNTA=CNTB always holds at the rising time of clock T24, stage signal K20
becomes '0'. As a result, the waveform of the stage signal K20 is at a high level during the period when CNTA≠CNTB, that is, from the rising edge of the clock T20 to the rising edge of the clock T24. What should be noted here is that exclusive OR is used, so the timing and period (pulse width) when the basic stage signal K20 becomes high level is C
Regardless of the initial values of NTA and CNTB, the clock T20
This point is determined only by the timing of the clock T24. Based on this basic stage signal K20, F
21 to 27 generate shift stage signals K21 to K27 whose phases are sequentially shifted by one phase difference of the basic clock.

In the AND section 13, the full-phase stage signal STG consisting of the stage signals K20 to K27 and the basic clock TO to
In response to T3, each of the AND circuits A20-27 performs the AND of the two human input signals as described above to generate output double period clocks T20-27. For example, AND circuit A
In 2, the double period clock T22 can be generated by taking the AND of the stage signal K20 and the basic clock T2.6 In other AND circuits, the stage signals K21, K22, . . . , K27 are generated, respectively. 2 of the total phase by taking the AND with the basic clock of the appropriate phase.
Double period clock T23, T24,..., T27, T2
0,T21 can be generated.

What is important here is that the stage signal in each AND circuit controls the gate passage of the corresponding basic clock.
It functions as a window.

Therefore, as long as the target basic clock pulse is completely included within the window, the rise timing of the output double period clock is determined only by the basic clock, and even if the change time of the stage signal changes due to propagation delay etc., the output Clocks are not affected at all.

Therefore, a necessary condition for the window is that only the clock pulses that are intended to pass are contained within the width of the window. In this embodiment, since N=2, the window functions to pass one pulse every two pulses of each basic clock.

Further, the width of the window is one cycle of the basic clock, and the correspondence between the two operators in each of the AND circuits A20 to A27 is selected so that the target basic clock pulse is located approximately at the center of the window.

As can be easily predicted from the above explanation, the window width of the stage signal is not limited to that shown in FIG. 2. That is, if the 8-phase stage signal can extract the 8-phase double period clock, the CNTA. C.N.
The combination of the input clocks to the TB and FFs 21-27, or the input of two people to the AND circuits 20-27, is not limited to that shown in FIG. However, the wider the window, the better in order to deal with propagation delays of stage signals, etc. with sufficient margin. On the other hand, it must not be too wide so as not to accidentally pass the basic clock pulse that is intended to be blocked. Considering these contradictory conditions, the configuration of this embodiment can be said to be preferable.

Next, FIG. 3 shows the configuration of a second embodiment of the N times period clock generation circuit of the present invention. In this embodiment, the number of phases of the basic clock is "4" as in the embodiment of FIG. 1, but N
II 3 II, that is, a triple period clock generation circuit.

In this embodiment, the difference from FIG. 1 is that the total number of phases of the N times cycle clock signal is from Ll 8 I+ to u 1 2
As the stage signal generation unit 11 increases to I+, the stage signal generation unit 11
The number of flip-flops in (31) increases from 7 to 11, and the number of AND circuits in the AND section 3 3 (1 3) increases from 8 to 12. Also,
Two phases T30 and T34 of the 12 phases of the triple period clock are applied to CNTA and CNTB from the clock oscillation circuit. The phase of the basic clock applied to each FF31-3B and the phase 2 inputted to each AND circuit 30-3B
The combination of human forces is similarly selected according to the conditions detailed for the first embodiment.

FIG. 4 shows the waveforms of the main parts of this second embodiment. C.N.
Clocks T30 and T34 applied to TA and CNTB
The period is different from that of the first embodiment, but since both phase differences are one cycle of the basic clock, the window width of the basic stage signal K30 is one cycle of the basic clock, as in the first embodiment. Based on this basic stage signal 3o, based on the same principle as in the first embodiment, shift stage signals K31 to K3 whose phases are shifted by one phase difference of the basic clock are sequentially generated.
B is generated, and each stage signal extracts one Glock pulse every three clock pulses of each phase of the basic clock.

In this way, the 12-phase triple period clock T30-T
3B is generated.

Below, the changes to the configuration when N is 4 or more, as can be easily predicted, are simply to increase the number of flip-flops and AND circuits, and generate a clock with a period N times that number (N = arbitrary). The time chart is shown in FIG. Similar to the embodiment described above, in addition to the four-phase basic clock To-T3, there are two x (4×N) phase N times period clocks TN○,
A stage signal KNO-KNX-1 is generated only from TN4, and by using this stage signal, it is possible to cut out the N times cycle clocks TNO to TNX-1 from the basic clock.

FIG. 6 shows two devices 60 and 70 incorporating the double period clock generation circuit for N=2 described in the first embodiment.
The schematic configuration of the system including

However, N is not limited to 2, and may be 3 or more, and the values of N in the devices 60 and 70 may be different.

Devices 60 and 70 are, for example, newly designed memory control devices using the latest technology, and control memory devices (not shown) that have been designed using existing technology and operate with a clock that has a cycle twice the basic clock of the device. ing.

Basic clock CLK (T
o, Tl, T2, T3) are the stage signal generation section 61.71 and the AND section 63, 64, in each device 60.70.
All phases are supplied to all parts of the stage signal generators 61 and 74, but the double cycle clock (NCLK=T20, T24) is supplied only to the stage signal generators 61 and 71 for two phases. The stage signal generation section corresponds to the stage signal generation section 11 in FIG. 1, and the AND sections 63, 64, 73, and 74 correspond to the AND section 1 in FIG.
Corresponds to 3. However, in each AND section, it is not necessary to prepare all the AND circuits shown in FIG. 1, and it is sufficient to provide only the AND circuits corresponding to the required double cycle clock phase.

The stage signals STG65 and STG75 created in the stage signal generation units 61 and 71 are applied to each logical product unit 63, 64, 7.
3.74, and the corresponding phase of the basic clock and the stage signal are ANDed in each AND section to generate a double period clock of an arbitrary phase. In synchronization with this double cycle clock, devices connected to this device that operate using the double cycle clock are controlled. That is, each logic unit outputs data to or receives data from an existing technology device to be controlled in synchronization with this double cycle clock.

With such a system configuration, the clock oscillation circuit 80
It is possible to generate all phases of the double period clock by only supplying two phases of the double period clock from
The burden on the number of LKs, etc.) can also be reduced.

Further, the initial value of the counter in the stage signal generation unit 61.71 at the moment when the power is turned on again after the device 60 is temporarily turned off is the stage signal generation unit 61.71 of the device 70 in operation.
Although there is no guarantee that the value of the counter in Also, the double cycle clocks of the two devices can be constantly synchronized without any synchronization control.

In the above embodiment, for convenience of explanation, only the case where M=4, that is, the case where the basic clock has four phases, has been described, but the present invention is not limited to this. Further, those skilled in the art will easily understand that various changes can be made to the polarity of the clock signal or stage signal, the input/output polarity of the AND circuit, etc.

[Effects of the Invention] According to the present invention, by simply supplying a two-phase N times period clock from a clock oscillation circuit, it is possible to generate a full phase N times period clock in distributed parts without any special clock synchronization control. A designer can easily construct a system using an N times period clock using a simple generation circuit without considering the burden on the clock oscillation circuit or clock synchronization between parts.

In addition to not requiring any initial settings, there is no need to reinitialize the operating parts at all when a partial power-off/on occurs when dynamic reconfiguration such as system maintenance or reorganization is taken into consideration. A system with excellent operability and maintainability can be configured.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram of a double period clock generation circuit according to an embodiment of the present invention, FIG. 2 is an operation timing diagram of each part of the circuit shown in FIG. 1, and FIG. 3 is another embodiment of the present invention. 4 is an operation timing diagram of each part of the circuit shown in FIG. 3, and FIG. 5 is a circuit diagram of a triple period clock generation circuit according to still another embodiment of the present invention. FIG. 6 is a block diagram showing an example of a system including a device incorporating a double period clock generation circuit. 11, 31, 61.71... stage signal generation section,
13, 33, 63, 64, 73.74... logical product part,
60.70... Device, 80... Clock oscillation circuit, A20 to A27, A30 to A3B... AND circuit,
CNTA, CNTB...1-bit CNT flip-flop, EOR...exclusive OR circuit, F21-F2
7, F31-F3B... Flip-flop for stage signal shift, K20-K27, K30-K3B... Stage signal (each phase), STG... Stage signal (
all phases).

Claims (1)

[Scope of Claims] 1. A method for generating an N times period clock in a device using a plurality of phase basic clocks and a plurality of phase N times period clocks having a period N times that of the basic clock, comprising: An N-time cycle clock generation method that generates an N-time cycle clock having a phase other than at least the two phases based on all phases of the basic clock and two phases of the N-time cycle clock. 2. An N-time period clock generation method that generates a clock of any phase among all M×N phases of N-time period clocks having a period N times that of the M-phase basic clock, the N-time period clock as described above. An N-time cycle clock generation method, characterized in that a clock of an arbitrary phase of the N-time cycle clock is generated based on the two phases of the N-time cycle clock and the basic clock. 3. Generate an M×N phase N times period clock based on the M phase basic clock and two phases out of all M×N phases of the N times period clock having a period N times that of the basic clock. An N times cycle clock generation method in which the two phases have a phase difference of one period of the basic clock, and based on the two phases, the pulse width of one period of the basic clock and the basic clock are determined. generate a basic stage signal having a period N times that of the clock; shift the stage signal sequentially in units of phase difference of the basic clock to generate an M×N phase stage signal including the basic stage signal; An N-time period clock generation method characterized in that an N-times clock signal of M×N phases is obtained by logically multiplying each stage signal of M×N phases and the corresponding phase of the basic clock. 4. An N-times clock generation circuit that generates a clock of an arbitrary phase among all M×N phases of N-times period clocks having a period N times that of the M-phase basic clock, the circuit comprising: Basic stage signal generation means for generating a basic stage signal having a pulse width including one pulse of the basic clock and a period N times the basic clock based on two phases of the M×N phases; stage signal shifting means for generating a plurality of shifted stage signals obtained by phase-shifting the basic stage signal outputted by the stage signal generating means by one phase difference unit of the basic clock; and the specific stage signal and the basic clock having a specific phase. 1. An N-time period clock generation circuit comprising: AND means for calculating an AND of . 5. The basic stage signal generation means includes a first holding means for holding a 1-bit input at a clock timing of one phase of the N-time period clock, and a 1-bit output of the first holding means at a clock timing of one phase of the N-time period clock. a second holding means for holding at a clock timing of a different phase; an inverting means for inverting the 1-bit output of the second holding means and supplying it to the first holding means; 5. The N-time cycle clock generation circuit according to claim 4, further comprising exclusive OR means for outputting an exclusive OR of 1-bit output as the basic stage signal. 6. An information processing system comprising a device using an M-phase basic clock and a multi-phase N times period clock having a period N times that of the basic clock, wherein the device is provided with an N times period clock generation circuit according to claim 4. An information processing system characterized in that a clock oscillation circuit is built in and provided outside the device to generate all phases of the basic clock and two phases of the N times cycle clock to be supplied to the device. 7. In an information processing system comprising a plurality of devices using an M-phase basic clock and a plurality of phases and N times the period clock of N times the period of the basic clock, each of the plurality of devices is provided with the method according to claim 4. An N times period clock generation circuit is built in, and a clock oscillation circuit is provided outside the plurality of devices to generate all phases of the basic clock and two phases of the N times period clock and supply them to each of the devices. An information processing system characterized by: 8. N-time period clock generation for generating at least an N-time period clock other than the two phases based on two phases of all M×N phases of the N-time period clock having a period N times as long as the M-phase basic clock. A stage signal generation circuit for a circuit, comprising a first holding means for holding a 1-bit input at a clock timing of one phase of the N-time period clock, and a 1-bit output of the first holding means using the N-time period clock. a second holding means for holding at a clock timing of a different phase; an inverting means for inverting the 1-bit output of the second holding means and supplying it to the first holding means; Exclusive OR means for outputting the exclusive OR of both 1-bit outputs as a basic stage signal; 1. A stage signal generation circuit comprising: stage signal shifting means for generating a shift stage signal.