JPH02291791A - Television system converter - Google Patents

Abstract

PURPOSE:To monitor a high-vision video which have both sides cut and a high- vision video of the nearly entire screen by adding a circuit which performs scanning-line conversion by a vertical filter for vertical time compression to a conventional circuit and switching the inputs and outputs of those circuits by switches. CONSTITUTION:A scanning line converting circuit 19 interpolates a Y, an R-Y, and a B-Y signal of 252 lines per frame which are inputted from a luminance signal processing circuit 7 and a color difference signal processing circuit 8 to convert the number of scanning lines from 525 lines per frame to 350 lines per frame an then inputs the converted signals to a speed converting memory circuit 20. The memory circuit 20 converts them into signals which are time- compressed vertically and a blanking inserting circuit 21 further adds blanking by as many as 175 scanning lines to output a signal of 524/60Hz. A selector 18 selects the output signals of processing circuits 7 and 8 when a PLL selecting circuit 17 selects a PLL circuit 5 with the signal from an input terminal 15 and the output signal of the blanking inserting circuit 21 when the selecting circuit 17 selects a PLL circuit 16, thereby outputting the selected signal.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] This invention relates to a television system converter.

[Conventional technology]

FIG. 2 is a diagram showing a television receiver according to the prior art by the present applicant. In the figure, 1 is a first input terminal, 2 is an A/D converter, 3 is a de-emphasis circuit, and 4 is a diagram showing a television receiver according to the prior art.
1 is a first PLL circuit, 5 is a second PLL circuit, 6 is a scanning line conversion circuit, 7 is a luminance signal processing circuit, 8 is a color difference signal processing circuit, 9 is a D/A converter, 10 is a switch circuit, 11 is an inverse matrix circuit, 12 is a second input terminal, and 13 is a third input terminal.
14 is an NTSC decoder, and 22 is an output circuit.

Next, the operation will be explained. A high-definition signal band-compressed by the MUSE method is applied to the input terminal 1. The high-definition signal has 1125 scanning lines, a field frequency of 60 Hz, and a 2:1 interlace signal. In the MUSE method, the above high-definition signal is transmitted in a band of 8M.
It is compressed to Hz and transmitted over one channel using a broadcasting satellite. This compression is performed by offset subsampling, using inter-field and inter-frame offsets for still parts and inter-line offsets for moving parts. Further, the two color difference signals R-Y and B-Y are time-compression multiplexed during the blanking period of the luminance signal.

The high-definition signal based on the MUSE method (hereinafter referred to as the MUSE signal) applied to the input terminal 1 is converted into a digital signal by the A/D converter 2, and applied to the de-emphasis circuit 3 and the first PLL circuit 4, respectively. . The first PLL circuit 4 reproduces a correct sampling clock based on the phase information in the MtJSE signal.

This correct sampling clock is determined by the A/D converter 2.
The above MU sampled in the correct phase
The SE signal will be applied to the de-emphasis circuit 3. The de-emphasis circuit 3 corrects the frequency characteristics of the MUSB signal, and this corrected signal is applied to the scanning line conversion circuit 6.

The scanning line conversion circuit 6 discards 75 scanning lines from the 1125 scanning lines per frame of the MUSE signal,
Converting to 1050 scan lines per frame and increasing the write clock speed to M
The speed is set to be the speed obtained from the time axis of the USE signal, and the speed of the read clock is set to be the speed obtained from the time axis of the NTSC signal. Therefore, from this scanning line conversion circuit 6, a signal having 1050 scanning lines per frame, 2:1 interlace, and a field frequency of 60 Hz is obtained.

The output signal of the scanning line conversion circuit 6 is transmitted to the luminance signal processing circuit 7.
．． The signal is applied to each of the color difference signal processing circuits 8. The luminance signal processing circuit 7 performs field interpolation corresponding to line offset sampling to restore the band to its original value.
After this, interlaced conversion is performed and 52 pixels per frame.
5 bottles. 2:1 interlace, field frequency 60Hz
signal is obtained. On the other hand, the color difference signal processing circuit 8 time-expands (TCI decodes) the two time-compression multiplexed color difference signals R-Y and B-Y, and performs intra-field interpolation processing to restore the band to its original value.

After this, interlace conversion is performed and 52
It is converted into 5 interlaced signals.

A luminance signal and two color difference signals R-Y, which are output signals of the luminance signal processing circuit 7 and color difference signal processing circuit 8, respectively.
, B-Y are applied to the D/A converter 9 and converted into analog signals.

On the other hand, the NTSC signal applied to the third input terminal 12 is guided to the NTSC decoder 14. NTSC decoder 1
Reference numeral 4 includes, for example, means for separating a luminance signal and a color signal, and means for demodulating a color signal, and outputs a luminance signal and two color difference signals from the applied NTSC signal. D/ above
The output signal of the A converter 9 and the output of the NTSC decoder 14 are applied to a switch circuit 10. switch circuit 10
is configured to output one of two signals applied to this switch circuit 10, depending on a signal applied to a second input terminal 13, which will be described later. The output signal of the switch circuit 10 is the inverse matrix circuit 11
The signal is input to the input signal, and primary color signals of R, G, and B are generated. The inverse matrix circuit 11 is similar to that implemented in current television receivers.

The output signal of the D/A converter 9 becomes a screen with an aspect ratio of 4:3, which is obtained by cutting off both ends of a video with an aspect ratio of 16:9, as shown in FIG.

[Problem to be solved by the invention]

Since conventional television receivers are configured as described above, there is a problem in that video information at both ends of high-definition is discarded.

This invention was made to solve the above-mentioned problems, and its purpose is to provide a television format converter that can monitor both high-definition video with both ends cut off and almost the entire screen. shall be.

[Means to solve the problem]

The television system converter according to the present invention has two PLs.
A PLL selection circuit that selects the output of the L circuit, a means for converting the number of scanning lines from 1125 to 525, a means for converting the number of scanning lines from 525 to 350, and a means for converting the number of scanning lines from 525 to 350.
means for vertically time-compressing the signal converted to 50 lines; means for adding a blanking period to the time-compressed signal to increase the number of scanning lines to 525; and the signal converted to 525 lines. and an output selection circuit that switches between the signal converted from 1125 lines and the signal converted from 1125 lines to 525 lines. [Operation] The television format converter of the present invention converts the scanning lines from 525 to 350, compresses the time in the vertical direction, and adds a blanking period, so the aspect ratio is converted correctly and the screen is compatible with NTSC monitors. Almost the entire screen of Hi-Vigilon video can be displayed. In addition, the PLL selection circuit switches between two types of read clocks for the scanning line conversion circuit output from the two PLL circuits based on a signal input from the external input terminal, and the output selection selector uses a signal input from the external input terminal. Since the video whose aspect ratio has been correctly converted and the high-definition video with both ends cut off are selected, it is possible to monitor both the high-definition video with both ends cut off and almost the entire screen.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings.

In FIG. 1, the same symbols as in FIG. 2 indicate the same things. 15 is the fourth input terminal, 16 is the third PLL circuit, 1
7 is a selector CPL that selects either the clock output from the second PLL circuit 5 or the third PLL circuit 16;
L selection circuit), 18 is a selector (output selection circuit), 19
is the luminance signal. A scanning line conversion circuit converts scanning lines of color difference signals (R-Y, B-Y signals), 20 is a speed conversion memory circuit, and 21 is a blanking insertion circuit.

Next, the operation will be explained.

The MUSE signal input to input terminal 1 is sent to A/D converter 2.
The first PLL circuit 4 reproduces the clock. On the other hand, the frequency characteristics of the quantized signal are corrected by a de-emphasis circuit 3. The corrected signal is input to the scanning line conversion circuit 6, and 1050 of the 1125 scanning lines are written into the memory, and the writing is performed by the clock reproduced by the second PLL circuit 4 or the third PLL circuit 16. read at a slow speed, 105
0 pieces/frame. It is converted into a 2:1 interlaced signal with a field frequency of 60 Hz. The above conversion output is the luminance,
Processed using two color difference systems.

The luminance signal Y is subjected to intra-field interpolation processing and conversion from 1050 to 525 scanning lines in the luminance signal processing circuit 7. on the other hand,
Since the color difference signals R-Y and B-Y are time-axis compression multiplexed during the horizontal blanking period of the luminance signal, they are time-axis expanded (TCI decoder) in the color difference signal processing circuit 8, and further subjected to field interpolation processing and 1050 525 scanning lines are converted, and the color difference signal processing circuit 8 outputs R-Y and B-Y signals.

The signals Y, R-Y, B-Y outputted from the luminance signal processing circuit 7 and the color difference signal processing circuit 8 are 525 signals/frame. It is a 2:1 interlaced signal with a field frequency of 60 Hz, and the signal Y. When the PLL selection circuit 17 selects the clock output from the second PLL circuit 5, R-Y and B-Y are as shown in FIG. 3(a) as shown in FIG. 3(b). The image looks like the original video signal with both ends cut off. Further, the PLL selection circuit 17 is connected to the third PLL circuit 1.
If the clock output from 6 is selected, the 3rd
As shown in FIG. 3(C), it is a vertically elongated video obtained by compressing the entire screen of FIG. 3(a) in the horizontal direction on the time axis. PLL selection circuit 17
is for switching the clock output from the second PLL circuit 5 and the third PLL circuit 16, and the two PLL circuits are switched by the signal input from the fourth input terminal 15.
One of the clocks output from the circuit 5.16 is selected and the luminance signal processing circuit 7. The signal output from the color difference signal processing circuit 8 can be switched between an image with both ends cut off as shown in FIG. 3(b) and a vertically elongated image as shown in FIG. 3(C).

Signals output from the luminance signal processing circuit 7 and the color difference signal processing circuit 8 are input to the scanning line conversion circuit 19. The scanning line conversion circuit 19 includes a luminance signal processing circuit 7 and a color difference signal processing circuit 8.
The number of scanning lines is increased from 525 per frame to 35 per frame by interpolating the 525 lines/frame Y, R-Y, B-Y signals as shown in FIG.
Convert to 0 and output.

The speed conversion memory circuit 20 receives 350 lines/60 Hz signals Y, RY, BY from the scanning line conversion circuit 19 as shown in FIG. 4(b). The speed conversion memory circuit 20 is composed of, for example, a memory, and by reading at a faster speed than writing, converts it into a vertically time-compressed signal as shown in FIG. 4(C), and sends it to the blanking insertion circuit 21. Output. The blanking insertion circuit 21 adds blanking for 175 scanning lines to the diagonally shaded area shown in FIG.
Outputs 50 signals Y, RY, B-Y. The signals Y, RY, and B-Y become an image as shown in FIG. 3(d), which is obtained by correcting the vertically elongated image in FIG. 3(C). This signal is sent to selector 18. In the selector 18, Fig. 3(d)
The signals Y, R-Y, B-Y outputted from the blanking insertion circuit 21 as shown in FIG. ，
Select and output either R-Y or B-Y. Similar to the selection signal of the PLL selection circuit 17, the selection signal of the selector 18 is determined by the signal input to the fourth input terminal 15.
When the LL selection circuit 17 selects the clock output from the second PLL circuit 2, the signals Y and R output from the luminance signal processing circuit 7 and the color difference signal processing circuit 8 as shown in FIG. -Y, B-Y are output from the selector 18, and P
When the LL selection circuit 17 selects the clock output from the third P, LL circuit 16, the selector 18 selects the signal output from the blanking insertion circuit 21 as shown in FIG. 3(d), Configure it to output. With this configuration, the signal output from the selector 18 in response to the signal from the fourth input terminal 15 is as shown in FIG. 3(b).
Either a signal with both ends cut off as shown in FIG. 3(d) or a signal with corrected vertically elongated video as shown in FIG.

The above signals Y, RY, B output from the selector 18
-Y is converted into an analog signal by the D/A converter 9 and input to the switch 10. Also, the NTSC signal input from the second input terminal 12 is converted into Y, R by the NTSC decoder 14.
-Y, BY signals and input to the switch 10. The switch 10 connects the signal from the D/A converter 9 and the N
The signal from the TSC decoder 14 is selected by the selection signal input from the second input terminal 13 and output to the inverse matrix circuit 11. The signals Y, R-Y, B-Y inputted to the inverse matrix circuit 1l are converted into R, G, B signals and outputted from the output terminal 22.

〔Effect of the invention〕

As described above, according to the present invention, a circuit for converting scanning lines using a vertical filter and performing time compression in the vertical direction is added,
Since the input to these circuits and the output from them can be changed with a switch, the high-visigon image can be either an image with both sides cut off or a full-screen image with both sides cut off. It is effective in monitoring the

[Brief Description of the Drawings] Fig. 1 is a block diagram showing a television system converter according to an embodiment of the present invention, Fig. 2 is a block diagram showing a conventional television system converter, Figs. The figure is a diagram explaining the operation of FIG. 1. 6 is a 1125-1050 scanning line conversion circuit, 7 is a Y signal field interpolation, 525 line interlace conversion circuit, 8 is a C signal time axis expansion (TCI decoding), field interpolation circuit, and 15 is a third Input terminal, 4 is the first PL
L circuit, 5 and 16 are the second. Third (two sets) of PLL circuits, 17 is a PLL selection circuit, l8 is an output selection circuit (selector), 19 is a 525-350 scanning line conversion circuit, 20
2 is a speed conversion memory circuit (time axis compression circuit), and 21 is a blanking insertion circuit. Note that the same reference numerals in the figures indicate the same or corresponding parts.

Claims (1)

[Claims] (1) Means for converting 1125 scanning lines of the MUSE signal into 1050 lines, Means for performing intra-field interpolation processing on the above-mentioned scanning line-converted luminance signal, and Means for interlacing 525 lines of this luminance signal. Then, time axis expansion is performed on the above scanning line converted color difference signal, and R
- Means for outputting Y and B-Y color difference signals; Means for performing intra-field interpolation processing on these two color difference signals; Means for interlacing 525 lines of this color difference signal; Supplying clocks to each of the above parts. M
A television format converter that converts a USE signal to an NTSC signal includes two sets of PLL circuits that reproduce different clocks from each other, a PLL selection circuit that switches the clocks reproduced from these two sets of PLL circuits, and the above-mentioned interlace conversion. 525 scanning lines per frame were used for the luminance and chrominance signals, and 35
a scanning line conversion circuit for converting to 0 scanning lines; a time axis compression circuit for vertically compressing the output of the scanning line conversion circuit in the time axis; and a circuit for adding blanking to the output of the time axis compression circuit. , The video whose aspect ratio has been correctly converted that is output from the above-mentioned scanning line conversion circuit, time axis compression circuit, and blanking addition circuit, and the high-definition video input to these circuits with both ends cut off, are processed by the above-mentioned PLL circuit. A television system converter characterized by comprising an output selection circuit that selects in accordance with the selection.