JPH02290353A - Second channel modem - Google Patents

Abstract

PURPOSE: To make a sufficient channel separation between a quadrature- amplitude-modulated QAM signal and a frequency shift key FSK signal and minimize the noise and distortion in the QAM signal by modulating FSK data at the time of transmissions and separating it at the time of reception. CONSTITUTION: A 2nd channel FSK modem 141 is coupled with a transmitter 131 and a receiver 140, the transmitter 131 receives QAM data TD from an interface IF 139, and the receiver 140 sends the data and a carrier detection signal to the IF 139. The output 10 of the transmitter 131 is passed through a QAM channel filter 133 to become a main transmission channel and sent it to an adder 22. An FSK transmitter 132 receives the FSK data 15 from the IF 139 and sends them to the adder 22 through an FSK channel filter 134. The addition output becomes a transmit signal 137. A received signal 138 is sent to the receiver 140 through a QAM channel filter 135, the FSK channel is separated from the QAM main channel signal by an FSK channel filter 44 and the signal is sent as data and carrier detection signals 49 and 50 to the IF 139 through an FSK receiver 136.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to the field of data transmission, and more particularly to data transmission using a second channel FSK modem.

[Conventional technology]

Communication of data information over a voice network between a sender and a receiver is typically accomplished by a modem. Modems (modulators/demodulators) convert digital information by modulating it according to a known demodulation scheme. This modulated data is sent to the receiving modem,
At the receiving modem, the data is demodulated to yield the original information.

Modulation techniques available for digital transmission include frequency shift keying (FSK), differential phase shift keying (DPSK)
There are several types, such as quadrature amplitude modulation (QAM).

Half-duplex modems are used for one-way, high-speed data transmission. These modems are typically ψW modems, with transmission rates of g6oo bps or higher, requiring higher bandwidth overhead. Typically one-way, but with a second transmission to provide information in the main transmission.
It is often desirable to provide channels for This second
The channel is typically an FSK type transmission channel and is limited to a narrow band within the voice bandwidth. The transmission rate is significantly lower than the main channel, often on the order of 5-110 bps.

In the prior art, the main QAM channel has a separate
channels are often added. The disadvantages of such individual second channel FSK modems are high cost, low performance, and limited functionality. For example, group delay equalization is not implemented in band split filters due to price limitations and board size limitations. This results in severe distortion of the ΦM signal, degrading the performance of the ΦM modem to an unacceptable level for data rates greater than 9.6 kbps. Furthermore, the separation between the two types of carrier frequencies in conventional FSK systems is on the order of 60 Hz.

For this reason, a large bandwidth is required for transmission, and the efficiency of bandwidth utilization is low.QAM of 19.2 kbps
Its use in modems is prohibited.

[Problem to be solved by the invention]

It is therefore an object of the present invention to provide sufficient channel separation between the QAM and FSK signals while minimizing noise generation and distortion in the ψW signal.

Another object of the invention is to obtain a second channel FSK modem that constrains FSK signals to the 300-400 frequency band.

Another object of the invention is that the separation of the two carrier frequencies is 4Q
Hz second channel FSK modem.

Another modem of the invention features high performance FSK detection, i.e.
It is an object of the present invention to provide a second channel FSK modem that facilitates achieving a bit error rate of 10 with a 4 dB signal-to-noise ratio when receiving an FSK signal at -45 dBm.

Yet another object of the invention is to obtain a fully integrated second channel FSK modem.

[Means to solve the problem]

This specification describes a second channel FSK modem for use with a main channel QAM modem. The present invention provides main channel QA with a data rate of 19.2 bpsi.
Fully integrated 75bps available for M modems
A narrowband second channel FSK modem is provided. The invention applies a switched capacitor circuit to implement a band split filter and an FSK transmitter.

A micro-digital signal processing sensor is implemented to realize an FSK receiver to achieve higher performance, long-term stability, and flexibility. The present invention separates the two carrier frequencies by 40 Hz to improve bandwidth efficiency.

A modulation depth of 0.53 is used to constrain the FSK signal to a narrow band of 300-400 Hz. Depending on this modulation degree, 9
, 75 bpa can be separated by two carrier frequencies 't-40 Hz. This requires separating the two carrier frequencies by 60Hz, 19.
It represents an improvement over the traditional 75 bps FSK modem, which requires wider bandwidth to transmit and eliminates the use of a 2 kbps QAM modem.

To provide sufficient channel separation between the ΦM signal and the FSK signal, a high Q transmitter filter is used to band limit the FSK signal. This high Q filter distorts the FSK signal and changes the duty cycle of the data bits. To maintain evenly spaced data bits, a predistortion circuit is used before the FSK transmitter.

Each multiplier coefficient of a digital filter implemented in a microdigital signal processor is stored in its signed representation and is optimized to have no more than 3 non-zero bits.

The present invention applies a high pass (hereinafter the same) filter to suppress the FSK signal by 30 dB or more, and equalizes the group delay response within plus or minus 100 microseconds for the 600 to 3400 Hz of the Takagi filter. For this purpose, a delay equalizer realized with 6 biquads is applied. In order to minimize the broadband thermal noise generated in the switched capacitor circuit, the topology and implementation sequence of zero transmission in the Takagi filter and the pairwise combination and ordering of polarity and zero were performed.

- 45 dBm before envelope detection to facilitate fast carrier detection of the FSK signal at 5.0 dBm.
A gain stage of B is provided.

In operation, an FSK modulator and low-pass filter are used to convert the second channel digital data into a band-limited FSK signal. The band of the φW signal is limited by a Takashiro filter, and a delay equalizer is used to remove energy remaining within the FSK band. The FSK and QAM signals are then combined and fed to a smoothing filter to transmit the line output. For reception, an antialias filter limits the band of the received line signal and couples the signal to a Takagi filter and a bandpass filter. To obtain the main channel output, the Takagi filter signal is delayed equalized and coupled to a smoothing filter.The bandpass filter is coupled to a microdigital signal processor via an A/D converter for full recovery of the FSK data.

This specification describes a second channel FSK modem for use with a main channel QAM modem.

In the following description, numerous specific details are set forth, such as number of devices, bandwidth, transmission speed, etc., in order to provide a thorough understanding of the invention. However, it will be apparent to one skilled in the art that the invention may be practiced without such specific details. In other instances, well-known features have not been described in detail in order not to obscure the invention in unnecessary detail.

The preferred embodiment of the present invention provides a fully integrated second channel FSK modem. The present invention is based on F.S.
The K and φW signals are sufficiently channel separated with minimal noise and distortion introduced in the QAM signal. In the preferred embodiment, the FSK and class signals are separated by more than 30 dB. The present invention can convert FSK signals to 300~400H.
Constrain to a narrow, distributed band of z, and the remaining vocal band is Φ
Occupied by the M signal.

The second channel FSK modem of the present invention provides an F-wave means to free up a portion of the main channel bandwidth. Modulation means are provided for modulating the signal for transmission over the freed bandwidth. A combining means combines the first signal and the second signal and outputs a two-channel signal having a majority signal and a minority signal.

The receiving means includes filter means for extracting a wide bandwidth of the multiple signals and receives the two channel signals. Second filter means are provided for extracting the minority signals. Demodulation means are provided to augment the minority signal from the received two-channel signal.

The preferred embodiment of the present invention uses a microdigital signal processor (μDSP) instead of using a switched capacitor circuit to implement the FSK demodulator. At the separation frequency intended by the present invention, a high Q filter with a low corner frequency is required. The switched capacitor circuit is designed to reduce the DC voltage introduced due to the leakage current at the connection point.
Due to the offset, it is not suitable for such filter applications. The μDSP of the present invention is constructed with a pipelined bitslice architecture. This architecture can be easily edited or enhanced for various system applications.

The transmitter section of the present invention includes a Takagi filter having a delay equalizer to remove incoming energy in the conventional FSK band;
An RTS/CTS timing sequencer for interfacing with the DTE, an FSK modulation and low-pass filter for converting digital data to a band-limited FSK signal, an attenuator to set the level of the FSK signal, and a QAM signal. and an RC-active low-pass filter to attenuate any aliases associated with the clock.

In the receiver section, an antialias low-pass filter limits the band of the input signal. The resulting signal is 2
divided into two routes. In the main channel path, the Takagi filter with delay equalizer is followed by an RC-active low-pass filter.

In the second channel path, after the 10-bit A/D converter, a μDSP is provided that performs band wave functions, FSK modulation, and signal level detection functions.

〔Example〕

A preferred embodiment of the invention is shown in FIG.

The second channel FSK modem of the present invention is shown generally within the dashed line 141. 2nd channel FSK
The modem is coupled to a ΦM modem transmitter 131 and receiver 140. QAM transmitter 131 is coupled to RS232 interface 139, receives QAM data TD and handshake RTS, and sends a response CTS signal to RS232
Supply to interface. QAM receiver 140 transmits the received data and carrier detection signal to RS232 interface 7.
Supply to Ace.

The output terminal 10 of QAM transmitter 131 is coupled to a φW channel filter 133 to form the main transmission channel. Output terminal 14 of QAM channel filter 133
is coupled to adder 22. FSK transmitter 132 is FS
K data 15 and RTS signal 27 are received from the RS232 interface. FSK transmitter 132 provides a CTS signal to the RS232 interface.

Output terminal 142 of FSK transmitter 132 is provided to FSK channel filter 134. Output terminal 21 of FSK channel filter 134 is coupled to summing point 22 .

The output 137 of the summing point 22 is connected to the main QAM channel and the second F
Represents a 2-channel signal including the SK channel.

The received channel signal 138 is passed through the QAM channel filter 13
5. The output 35 of the sea bream channel filter is QA
M receiver 140. Receive channel signal 138
is also coupled to the FSK channel filter 44 so that FS
The K channel is separated from the QAM main channel signal. F
The output 45 of the SK channel filter 44 is connected to the FSK receiver 1.
36. The FSK receiver 136 provides the received data and carrier detection signal 49.50 to the RS232 interface.

The channel allocation for the preferred embodiment of the present invention is shown in FIG. QAM signals are transmitted with a bandwidth of 400-3400Hz. 2nd channel FSK signal is 300-40
Restricted to 0Hz band. Using the preferred embodiment of the present invention, the two carrier frequencies are separated by 40 Hz for a 75 BPS FSK transmission. This makes the present invention 1
Can be used with 9.2kbps QAM modem.

A block diagram illustrating a preferred embodiment of the invention is detailed in FIG. A transmission line 10 is coupled to a Takagi filter 11. Output terminal 12 of Takagi filter 11 is coupled to delay equalizer 13 . TD15 is provided as an input to FSK modulator 16. TD signal 15 is the ninth digital signal from an external signal source transmitted to the second channel.

Output terminal 17 of FSK modulator 17 is coupled to low pass filter 18 . The output terminal 19 of this low pass filter is coupled to an attenuator 20. A level control signal 30 is input to attenuator 20 . The output 21 of this attenuator 20 is combined at a summing point 22 with the output 14 of the delay equalizer 13.

The RTS-CTS sequencer provides modem handshakes to the second channel FSK. RTS is used as an input to signify that the DTE has data to transmit. - CTS is used as an output to indicate that communication has been established and data can be transmitted.

Output terminal 23 of summing point 22 is coupled to smoothing filter 24 to provide transmission line output 25.

A clock generator 31 utilizes a master time reference generated by an on-chip crystal oscillator to provide a plurality of outputs 34 for clocking a second channel FSK modem. The crystal oscillator 14 includes external crystal oscillators XTAL32 and
A TAL 33 is provided.

Receive line signal 43 is coupled to antialias filter 42 . Output terminal 41 of Unchilius 7 Ilter 42
is coupled to a high-pass filter 40 and a bandpass filter 44.

Output terminal 39 of Takagi filter 40 is coupled to delay equalizer 38 . Delay generator 38 provides an output to smoothing filter 36. This smoothing filter produces a receive line output 35.

Bandpass filter 44 provides an output to a 10-bit analog-to-digital converter 46. A 10-bit digital signal 47 is supplied to μDSP 48. This μDSP 48 generates a received FSK signal 49 and a carrier detection signal 50.

In operation, Takashiro filter 11 and delay equalizer 13 remove incoming energy in the main channel signal to make up the band available for use in the second channel.

A Takagi filter 11 is used to remove low frequencies from the wideband input signal 10. However, this filter can also change the phase of the high frequency signal. In QAM signals, since the phase of the signal carries the data information, it is desirable to correct the phase of the high frequency signal back to its original state. A delay equalizer 13 is used to return the phase of the high frequency signal to its original state.

When an external signal source is used to utilize the second channel, a request to send (RTS) signal 2T is provided to the RTS-c'rs controller 29. RTS-CTS controller 29 outputs enable signal 26 to FSK modulator 16 in response to clear to transmit (CTS) signal 28 .

The second channel data is then coupled through FSK modulator 16 , low-banded in filter 18 , and coupled to attenuator 20 . An attenuator sets the FSK signal level under the command of level controller 30. The external control signal is a signal that is externally selected by the user to provide gain to the low pass filter signal. Typically, the second channel signal is 6 dB lower than the main channel signal. Therefore, the user may wish to adjust the gain of the second channel signal according to the transmission level of the main channel QAM signal.

FSK signal 21 and QAM main channel signal are summed and coupled to smoothing filter 24. This smoothing filter uses R to attenuate aliases related to the clock.
C active, low pass filter.

Upon receiving the combined raw channel signal and second channel signal, signal 43 is coupled to an antialias 7 filter to band limit the input signal. This band-limited signal 41 is sent to the main channel and the FSK channel 2.
connected by two routes.

The main channel signal is delayed equalized in filter 40, and signal 41 is converted into a band F wave and coupled to a 10-bit A/D converter. The output of this A/D converter is coupled to a microdigital signal processor 48 to perform FSK demodulation and signal level detection functions.

A transmission state flowchart for the second channel is shown in FIG. At START 143, the START FSK modem checks at decision block 144 whether the R'rS line is high. If the RT8 signal is not high, the modem remains in standby mode.

If the RTS signal is high, the modem
5, turn off the silence and transmit data line 1.
5 is set as a mark, the reception data line 49 is set as a mark, and the carrier wave detection line 5θ is turned off. The modem remains in this state for a delay time of 71.1 milliseconds. Decision block 146 determines whether the off-to-on delay is over.

If the delay does not end, the modem checks at decision block 145 to see if the RTS signal has been turned off. Assuming the RTS signal is not turned off,
The modem returns to block 145. If the RTS signal is turned off, the modem returns to silent mode at block 154 and returns to its standby state.

Once the off-to-on delay is over, the modem enters block 14.
1, the CTS signal 28 is turned on.

The modem then begins transmitting data at block 148. During transmission, at decision block 149,
The modem checks to see if the RTS signal is turned off. If the RTS signal is not turned off, the modem begins transmitting. The transmitted data signal 115 is ignored and the RTS signal is turned off, block 15
Siren at 0/(Cattersoned.0.6
A millisecond on-to-off delay is realized and examined at decision block 151. If the delay does not end, the modem company simply waits. Once the delay has expired, the modem turns off the c'rs signal at block 152, releases the carrier detect signal, and returns to its standby state.

A microdigital signal of the present invention is shown in FIG. The μDSP is constructed with a pipelined bitslice architecture that can be easily edited or enhanced for various system applications. Referring to FIG. 2, program counter 52 controlled by reset signal 51 outputs an 8-bit program count 53 to memory storage 54. Output terminal 55 of ROM54
is coupled to controller 56. This controller has multiple outputs 5
1 to 61 are supplied to the arithmetic elements of the μDSP. In the preferred embodiment of the invention, output 5T is a 5-bit output and is coupled to RAM 78. This RAM is 10 bits}
It receives the digital output 47t- of the ADC 46 (FIG. 1).

RAM78 supplies output 67 to limiter 63.

The control block 56 sends the 1-bit control signal 58 to the limiter 6.
Supply to 3. This limiter 63 transfers the output 64 to the shifter 6
Supply to 5. The control block 56 has a 5-bit control signal 5
9 is supplied to the shifter 65. One bit among the five bits controls the direction of the shift, ie, the MSB to the LSB. The remaining 4 bits control the number of shift locations from θ to 15.

The output 65 of shifter 65 is provided as one input to an arithmetic logic unit (ALU) 67. Control block 56 provides a 4-bit control code 60 to ALU 76. ALU
The output terminal 68 of 76 is coupled to an accumulator 69. The output terminal 70 of the accumulator 70 is coupled to the other input terminal of the ALU 67 and to a saturation logic unit 72. The output terminal 73 of this saturation logic device is coupled to the input terminal of RAM 78.

The "S" output terminal (sign output terminal) 71 of the accumulator 69 is D
type slip flop γ4, is coupled to the input terminal of T5. A positive output of accumulator 69 represents a mark in the FSK scheme and a negative sign represents a space.

Control block 56 provides clock signals 76.77 to seven flip-flops 74.75, respectively.

Clip 7 romp γ4 provides the received data signal 49 and flip 7 romp 75 provides the carrier detect signal 50.

In a preferred embodiment of the present invention, 17 of ROM 32
6+ [F, 32 words of RAM, limiter, barrel shifter,
The μDSP is optimized for recursive digital processing with an 18-bit ALU, accumulator, and saturation logic.

Depending on the number of non-zero pits in the signed numerical representation of the multiplier, the multiplication is performed by several shifts and additions. μ
Domino logic is widely used to achieve the small chip area, low switching noise, and high speed required by DSPs.

Each multiplier coefficient is optimized to have no more than two non-zero bisots in the signal one-digit representation of each multiplier coefficient. With this technique, the μDSP effectively performs a 17-pole offshore wave in the FSK receiver. LDI with low sensitivity digital filter
Implemented in a ladder structure to minimize the effect of multiplier coefficient quantization on the frequency response of the filter. An error of less than plus or minus 0.0 2 dB is achieved in the passband of the fourth type oval band ladder filter.

The main analog elements included in the device are 7th type oval high-pass ladder filters, which have 12 types of delay equalizers. The Takashiro filter suppresses the FSK signal by more than 30 dB. A delay equalizer implemented in 6 picands equalizes the group delay response from 0.6 kHz to 3.4 kHz to within plus or minus 100 microseconds for the Takagi filter.

The FSK modulator 16 of FIG. 1 is shown in detail in FIG. At the frequencies and baud rates of the preferred embodiment of the present invention, asymmetric FSK Hals can be generated.

That is, the space can be expanded so that it is longer than the mark. Therefore, in order to make the rising edge and the falling edge of the pulse uniform, shrinking the space, and widening the mark, the FSK pulse 15 is processed by the precompensation circuit 79.
is combined with This results in a mark/
Space duty cycles are equal. Output terminal 80 of predistorter 79 is connected to P
Coupled to LA counter 81. PLA counter 81 provides a strobe signal 82 to decode logic 84. A reset signal 83 from this decoding logic 84 is sent to the PLA counter 81.
supplied to

Decode logic 84 provides a plus signal 85, a zero signal 86, and a minus signal 87 to modulator 8B.

Voltage VDD is applied to resistor Rl. and R2 to ground, and a junction 89 between those resistors R1 and R2 is coupled to modulator 88. Modulator 88 provides FSK tone output 17 to seven pole low pass filter 18 . Signals P1 and P2 control low pass filter 18. The output 19 of the low pass filter 18 is fed together with a control signal 30 to an attenuator 20 . The output 21 of this attenuator 20 is fed to a summing point 22 (FIG. 1).

Timing signal 3rd for various signals of FSK modulator
Shown in Figure a. Strobe signal 82 is approximately 12 times the tone frequency.

The precompensation circuit 79 is shown in detail in FIG. 6a. F
SK data 15 is input to D-type flimp 7off 11
9. Output 1 of this frimb 7 lop 119
20 is supplied to the set input terminal of the RS flip-flop 121, and the OR gate 12 is supplied as one input.
Combined into 4. The output terminal 130 of this OR gate is coupled to the reset input terminal of counter 125. This counter 125 is 5 in the preferred embodiment of the invention.
It is a bint counter. A 7.2 kHz clock signal clocks the counter 125 and the 7-rip 7-lop 119.

Output terminal 126 of counter 125 indicates end count logic 1
27. This logic 127 is the end signal 128i
It is supplied to the D-type flip 7 flop 129. This flip-flop 129 is clock-controlled by a clock signal 122. The output terminal 123 of flip-flop 129 is coupled to the other input terminal of OR gate 124 and to the reset input terminal of flip-flop 121. Flip-flop 121 provides a compensated output 80.

During operation, F8K data is transferred to D-type clip fluff 1.
19. This flip 7 lop is 7.2
Clock controlled at kHz. Synchronized data 12
0 is provided to the RS 7 rip 7 lop 1210 set input terminal. The counter 125 is also clocked at 7.2 kHz and the data 120 to be synchronized is marked (
Counter 125 always resets when either rlJ) or when the count reaches a preselected end count. In the latter case, clip flop 121 is reset to space (rOJ). According to this technique, the mark signal is stretched by a predetermined amount of time and the space is shortened by the same amount of time.

Referring now to Figure 6b, the uncompensated transmit data signal 15 has equal duty cycles for marks and spaces. In a preferred embodiment of the invention,
The length of the mark is 13.3 ms. After the precompensation circuit, the mark length at output 80 is approximately 17.3 milJ seconds and the space length is 9.3 milJ seconds. The next F-wave properties of the present invention are such that the spaces are lengthened and the marks are shortened. However, by precompensating and lengthening the marks, the net result is that the duty cycles for marks and spaces in the receive channel are equal.

Realized by micro digital signal processor 7'h
A functional block diagram illustrating the FSK demodulator is shown in FIG. This demodulator is indicated generally by dashed line 92. Received signal 4 passed through antialias filter
1 is provided to a bandpass filter 44 to limit the band of the FSK second channel. The output 45 of the filter 44 is converted into a p-digital signal by an analog-to-digital converter 46. This digital signature 47 is supplied to a demodulator 92.

μDSP implements a bandpass filter 93. This bandpass filter is a 4-pole filter in the preferred embodiment. The output 94 of this filter 93 is provided to the data detection channel and the carrier detection channel. In the data detection channel, signal 93 is provided to limiter 95. This limiter converts the signal to a glass minus 7 scale signal.

This full scale signal is applied to bandpass filter 98 to detect marks and to bandpass filter 99 to detect spaces. The output 105 of the filter circuit is coupled to an envelope detector 107 to convert the energy to a DC value. The output of this envelope detector represents the mark energy.

The output of filter 99 is coupled to envelope detector 108 to convert the space energy to a DC value. The output terminal 110 of the envelope detector 108 is the envelope detector 1.
It is coupled to the summing point 111 along with the output terminal 109 of 07. If a large amount of positive energy is present, a mark will be detected on the output line 112. If more negative energy is present, a space is detected in output line 112.

Output line 112 is coupled to a three-pole bandpass filter 113 to smooth out the noise caused by the carrier energy. The output of this filter 113 is the comparator 116
is coupled to the comparator and compared to a threshold (typically zea) with a small hysteresis to determine whether a mark or a space is detected.

Output terminal 94 of filter 93 is also coupled to a second path for determining carrier detection.

Ninth, the output 1oo of gain stage 96 is coupled to bandpass filter 117 to shorten the detection time. This band 7 ilter 11
The output 118 of 7 is coupled to envelope detector 101 for converting the carrier detection energy to a DC value. The DC value 102 is coupled through a 3-pole low-pass filter 154 to a comparator 1θ4 where the DC value is
It is compared to a threshold level 103 with a hysteresis of 2 dB. If the energy exceeds the threshold level 103, a carrier detection signal is provided to the output terminal 50.

Filter 93 of FIG. 4 is shown in detail in FIG.

This filter is a 4-pole filter, and FIG.
, X2 , X3 , X4 and the state calculation for the output state Y(n). The filter coefficients are implemented such that the maximum number of non-zero bits is three. This allows the filter f to be
t, thereby simplifying μDSP programming and providing precise F-wave performance. Coefficient M. -M10 contains a number in parentheses indicating the number of non-zero pits associated with each coefficient. The actual coefficients are as follows.

MO=2-" M1=2 -2 +2 -4 -7 -Ill M2=2 +2 +2 M3=2 +2 +2 M4=2 +2 -2 -4 -S -7 M5=2 +2 +2 M6=2 -2 - 2 M7=2 +2 -2 M8=2-"M9=2" M10=2 +2 +2 Figure 5 shows the following state, (n+1
) and the calculation of the next output value Y(n+l).

XI (n+1)=X1(n)+M1 {X2(n+1
)+MO”U(n)-MB [X1 (n)+M
2”X3 (n)) }X2(n+1)−X2
(n)+M3 (MI O”X3(n)-CX
I (n)+M2”X3 (n))}X3(n+1
)−X3(n)+M4(X2(n+1)+MO”U(
n)-M8(XI(n)+M2"X3(n)))-Fi
'l5(M9"X2(n+1)+(X4(n+l)
+M7°x3(n)))X4(n+1)-X4(n)+
M6'' The output of the addition point E2 is multiplied by the coefficient M1, and the product is supplied to the addition point E4.The output of the addition point E2 is multiplied by the coefficient M1.
4 is also multiplied and the product is supplied to addition point M9.

The output of the summing point E4 is coupled via the delay device Dl to obtain the value X.
1. This value X1 is transferred to the addition point E via a feedback loop.
4 and to summing point E5.

The output of addition point E5 is multiplied by coefficient M8, and the product is supplied to addition point E1. The output of addition point E5 is addition point E6
It is also supplied as input to. The output of this summing point E6 is multiplied by a coefficient M3, and the product is supplied as an input to the summing point E7. The output of this summing point E7 is coupled to the other input terminal of the summing point E7 via a delay device D2 and a feedback loop. This value is the X2 value mentioned above. The output of the summing point E7 is also coupled to the summing point E2 at a circuit point N2 and multiplied by a coefficient M9. Their product is provided as input to summing point E8. The output of addition point E8 is multiplied by coefficient M5, and the product is supplied to addition point E9. The output terminal of summing point E9 is coupled to summing point EIO.

The output terminal of summing point EIO is fed back to summing point EIO via delay device D3 and a feedback loop. The output of delay device D3 is the value X3. This value X3 is multiplied by the coefficient M2, and the product is supplied to the addition point E5.

The value X3 is also multiplied by the coefficient MIO, and the product is the addition point E.
6.

A value X3(n) equal to the output Y(n) is multiplied by a coefficient M6, and the product is supplied to the addition point Ell. Addition point El
The output of l is coupled to summing point E12 and fed back to circuit point Elf via delay D4. This value is the X4 value. The output Y(n) is multiplied by the coefficient M7, and the product is supplied to the addition point E12.

By implementing a filter with coefficients containing at most three non-zero bits, the digital signal processing of the present invention is simplified and the code required is The number of lines decreases.

This concludes my explanation of the second channel FSK modem.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a second channel FSK modem of the present invention, FIG. 2 is a block diagram of a microdigital signal processor of the present invention, FIG. 3 is a block diagram of an FSK modulator of the present invention, and FIG. 3a is a block diagram of a second channel FSK modem of the present invention. The waveform diagram of FIG. 4 is F of the present invention.
A block diagram of the SK demodulator, FIG. 5 is a state diagram of the filter of the present invention, FIG. 6a is a circuit diagram of the precompensation circuit of the present invention, and FIG. 6b is a diagram of the FSK data signal before and after precompensation. Timing diagram, Figure 7 shows the QAM channel and FS of the present invention.
FIG. 8 is a flowchart showing the operation of the present invention, and FIG. 9 is a block diagram of the present invention. 11.40...Takagi filter, 1 3. 38...
...Delay equalizer, 16...FSK modulator, 18...
・Low pass filter, 20・ ・Attenuator, 24.36・
... Smoothing filter, 26 ... - RTS-CTS controller, 31 ... Clock generator, 42 ... Antialias filter, 48 ... Micro digital signal processor, 46 ... A/D converter, 44...
...Band filter.

Claims (3)

[Claims] (1) coupled to the first input signal to form a first channel for transmitting the first input signal;
first filter means for providing an output signal of; and a first filter means coupled to said second input signal to form a second channel for transmitting a second input signal; a modulating means coupled to the first filter means and the modulating means for combining the first output signal and the second output signal;
A second channel modem comprising combining means for supplying two channel signals. (2) first filter means coupled to the first input signal to form a first channel for transmitting the first input signal and providing a first output signal; equalization means coupled to the output signal to provide a first channel signal; and equalization means coupled to the second input signal to form a second channel for transmitting a second input signal; modulation means for providing a signal; level control means coupled to said second output signal for controlling the amplitude of said second output signal and providing a second channel signal; said equivalent means and said level control. combining means coupled to means for combining the first channel signal and the second channel signal to provide two channel signals; and second filter means for recovering the first channel signal. and third filter means for recovering said second channel signal, receiving means for receiving two channel signals; and receiving means coupled to said third filter means for receiving said second channel signal. a demodulating means for converting the signal into a signal that is converted into a second channel modem. (3) first filter means coupled to the input QAM signal to form a first channel and provide a first output signal; and coupled to the first filter means to provide the first output signal. delay equalization means for modifying the phase of the signal and providing a first channel signal; modulation means for converting the digital input signal into an FSK signal; coupled to the FSK signal to form a second channel;
second filter means for providing a second output signal; gain control means coupled to the second output signal for controlling the amplitude level of the second output signal and providing a second channel signal; , summing means coupled to the first channel signal and the second channel signal for combining the first channel signal and the second channel signal to provide two channel output signals; receiving means having third filter means for separating one channel signal and fourth filter means for separating said second channel signal and coupled to two channel output signals; a second channel FSK modem, comprising: demodulation means coupled to a second channel signal and converting the second channel signal into a receive signal and a carrier detection signal.