JPH0746152A - Spread spectrum communication system - Google Patents

Abstract

PURPOSE:To simplify the circuit configuration and to improve S/N of matched pulses by performing the delay detection processing in the base band in the spread spectrum communication system where SAW matched pulses are used to demodulate data by delay detection. CONSTITUTION:On the transmission side, a PN code is selectively transmitted in accordance with the polarity of differentially converted source binary data. On the reception side, the matched pulse is detected in each period of the PN code by a SAW correlator 24 and is subjected to square detection by a double balanced modulator 25. The shaped matched pulse demodulates differentially converted data in a set priority flip flop circuit 32. Further, source binary data is demodulated by a delay detection circuit consisting of an exclusive OR element 34.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a spread spectrum communication system using matched pulses in direct spread modulation.

[0002]

2. Description of the Related Art Conventionally, in spread spectrum communication by direct sequence modulation, a differential detection system has been used as a system that does not require a PN code (pseudo noise sequence) synchronizer on the receiving side. In this method, the transmission side differentially converts the transmission data, and then multiplies it with the PN code to obtain a spread spectrum signal, and the reception side spreads the received spread spectrum signal and its received spread spectrum signal for one bit of data ( The product of the delayed signal (corresponding to one cycle of the PN code) is calculated,
The data signal is demodulated by using the low-frequency component of the multiplied signal.

FIG. 4 is a block diagram of a conventional differential detection system.
5 shows the signal waveform of each part. FIG. 4A shows a block diagram on the transmission side. In the figure, source binary data input from the signal line 500 is input to the exclusive OR gate 50. The other input of the exclusive OR gate 50 is input from the signal line 501, and the exclusive OR gate 50
An exclusive OR operation is performed at, and a so-called precoded signal is output to the signal line 502. Signal line 5
The signal 02 is input to the delay circuit 51 and the source binary data 1
The signal is delayed by a bit and is output to the signal line 501.

The clock generation circuit 54 outputs a clock signal for generating a modulation PN code to the signal line 504. P
The N code generator 53 generates a PN code for modulation by the clock signal from the signal line 504 and outputs it to the signal line 503. The multiplier 52 multiplies the signal from the signal line 502 and the signal from the signal line 503 and outputs the product to the signal line 505. The signal from the signal line 505 is the carrier signal generator 56.
The carrier wave signal from is multiplied by the multiplier 55, and the signal line 5
It is output to 07.

FIG. 4B shows a block diagram on the receiving side.
In the figure, the received spread spectrum signal from the signal line 508 is input to the SAW correlator 57. SAW correlator 5
7 outputs a matched pulse signal of a carrier having positive and negative phase information to the signal line 509 for each 1-bit data (1 PN code period) according to the polarity of the transmission PN code.
The matched pulse signal from the signal line 509 is multiplied by the multiplier 59.
And the data is input to the delay circuit 58 having a delay time of one bit. The multiplier 59 multiplies the matched pulse signal from the signal line 509 and the delayed matched pulse signal from 510, outputs the result to the signal line 511, and the data demodulation circuit 60 demodulates the information data.

FIG. 5 shows the signal waveform of each part. Figure 5 (a)
Shows the waveform of the source binary data of the signal line 500, and FIG. 5B shows the precoded signal waveform of the signal line 502.
5C is a matched pulse signal including the carrier wave of the signal line 509, FIG. 5D is a matched pulse signal delayed by one PN code period of the signal line 510, and FIG.
Shows the waveform of the signal line 511, and FIG. 5 (f) shows the demodulated data waveform of the signal line 512.

[0007]

In the above-mentioned conventional differential detection system, the receiving side has P in the carrier frequency band.
A delay time of one N code cycle is required. In addition to the above-mentioned method of using a SAW delay line to obtain this delay time, a method of synchronizing with a carrier frequency signal to convert it into a baseband signal and digitally using the clock signal for the baseband signal However, both types require complicated circuit configurations and are expensive.

Further, when a delay of one PN code period is obtained using the SAW delay line, there is a problem that the S / N ratio of the matched pulse signal deteriorates due to variations in delay time.

[0009]

In order to solve the above problems, the spread spectrum communication system of the present invention comprises means for differentially converting source binary data on the transmitting side in spread spectrum communication by direct spread modulation. , PN code generating means, means for controlling to selectively output the PN code from the PN code generation in accordance with the polarity of the differentially converted binary data, and the selectively output PN. At least four means for multiplying a code by a carrier frequency signal and transmitting a spread spectrum signal are provided, and the selectively output PN code is detected from the received spread spectrum signal on the receiving side. Means for generating a matched pulse for each cycle of the PN code, means for square-law detecting the matched pulse, and square-matched matched pulse The delay means for delaying the pulse by one cycle of the PN code, the square-law detected signal as a first input signal, the signal delayed by the delay means as a second input signal, and the first input signal is the above-mentioned Data that has been differentially converted by placing the second input signal in the first state and outputting it and outputting the second input signal in the second state in preference to the input of the second input signal. And at least five means for demodulating the source binary data by differentially detecting the demodulated differentially converted data.

[0010]

According to the above system, in the spread spectrum communication system for demodulating the binary source data by the differential detection system,
By performing square-law detection of the matched pulse, it is possible to perform differential detection in the baseband, and moreover
It is also possible to improve the S / N of the pulse signal.

[0011]

EXAMPLES Specific examples will be described in detail below. Figure 1
FIG. 3 is a block diagram showing an embodiment of a transmitting side that realizes the spread spectrum communication system of the present invention.

In FIG. 1A, source binary data input from the signal line 100 is precoded in the differential conversion circuit 10, output to the signal line 101, and input to the selection circuit 11. In the selection circuit 11, the signal line 102,
The signal from 103 is selected according to the polarity of the differentially converted binary data, and is output to the signal line 105. The PN code generator 12 outputs a PN code to the signal line 102 and a certain voltage to the signal line 103. The clock generation circuit 13 outputs a clock signal for generating the PN code for modulation to the signal line 104.

The spread spectrum signal from the signal line 105 is a PN code selected according to the polarity of the binary information data signal which has been differentially converted, and the multiplication circuit 14 carries the carrier frequency signal generation circuit 15 with the carrier signal. It is multiplied with the frequency signal. The product signal of the signal line 107 is a bandpass filter 1
The band is limited in 6 and the transmission spread spectrum signal is output to the signal line 108.

FIG. 1B shows a circuit example of the selection circuit 11 shown in FIG. In FIG. 1B, when the binary data signal from the signal line 101 is at H (high) level, the signal line 102
The PN code for modulation from is output to the signal line 109, and when the binary data signal is at L (low) level, the signal from the signal line 103 is output to the signal line 109. The PN code selected by the binary data signal from the signal line 109 is latched by the D flip-flop 20 by the clock signal from the signal line 104 and output to the signal line 105 as a spread spectrum signal.

FIG. 2 is a block diagram showing an embodiment of the receiving side for implementing the present invention. In FIG. 2A, the received spread spectrum signal input from the signal line 200 is input to the multiplier 20. The other input of the multiplier 20 is input from the signal line 201, the local signal from the local oscillation frequency signal generator 21 and the received spread spectrum signal from the signal line 200 are multiplied, and the signal line 202 is fed with the intermediate frequency spectrum. It is output as a spread signal.

The intermediate frequency spread spectrum signal from the signal line 202 is band-limited by the band pass filter 22,
It is output to the signal line 203. The intermediate frequency spread spectrum signal from the signal line 203 is sent to the next SAW in the amplifier circuit 23.
It is amplified to the optimum input level of the correlator 24. The SAW correlator 24 outputs a matched pulse signal to the signal line 205 for each PN code cycle in which the bit patterns match.

Since the matched pulse signal contains the carrier component of the intermediate frequency, the double balanced
Square-law detection by the modulator 25, low-pass filter 2
The low frequency component is extracted at 6 and output to the signal line 207. Due to this square detection operation and LPF band limitation,
The signal-to-noise ratio of the pulse signal can be improved. Further, the receiving circuit can be realized by using a digital correlator instead of the SAW correlator which is an analog correlator.

The matched pulse signal from the signal line 207 is a PDI (post-detection integrator).
The signal is input to the unit 48, the signal-to-noise ratio is improved by taking measures against multipath fading, and the signal is input to the matched pulse shaping circuit 30. The PDI unit 48 outputs the matched pulse signal from the signal line 207 for one data bit, that is, PN.
The delayed matched pulse delayed by one cycle of the code and the directly matched pulse signal are multiplied by the multiplier 28, and the integrator 29
Integrate with. When the influence of multi-path fading is not important, the PDI unit 48 is omitted and the signal from the signal line 207 is directly input to the matched pulse shaping circuit 30.

The matched pulse signal pulse-shaped by the matched pulse shaping circuit 30 is output to the signal line 211 and is output as a set signal of the flip-flop circuit 32. The pulse signal on the signal line 211 is output to the delay circuit 3
1 is also input to the delay circuit 31, and the delay circuit 31 receives a delay of one cycle of the PN code and is output to the signal line 212 as a reset signal of the flip-flop circuit 32.

The flip-flop circuit 32 is a set-reset flip-flop circuit with set priority.
The binary signal differentially converted by the set signal from the signal line 211 and the reset signal from the signal line 212 is demodulated and output to the signal line 213.

The signal from the signal line 213 is input to a delay detection circuit including a delay circuit 33 for one bit of data, that is, one cycle of the PN code and an exclusive OR element 34, and demodulates the source binary data.

FIG. 2B shows a circuit example of the set priority flip-flop circuit 32. Although a set signal is input from the signal line 211 and a reset signal is input from the signal line 212, the reset signal becomes valid when the set signal is at the L level, and only at that time a reset pulse is input. , Effective reset to the signal line 252 as a negative pulse.
It is output as a pulse. The set pulse signal is effective when the reset pulse signal is at H level or L level, and when the set pulse signal is input, the signal line 251 is input.
Output as a negative pulse.

The set pulse signal on the signal line 251 and the reset pulse signal on the signal line 252 are input to the D flip-flops 43 and 44 and synchronized with the clock signal 216 from the clock signal generator 35. Signal line 253
From the signal line 254 and the reset pulse signal from the signal line 254 are input to the set / reset flip-flop circuit composed of the logic gate elements 45 and 46, and the demodulated data signal is output to the signal line 255. It is output to the signal line 213 through the flip-flop 47.

FIG. 3 shows the signal waveform of each part. Figure 3 (a)
Shows source binary data of the signal line 100 in the block diagram on the transmission side of FIG. FIG. 3B shows a selection circuit 1 according to the polarity of the information data of the precoded signal line 101.
1 shows an output waveform of 1. 3C shows a matched pulse signal including the carrier wave of the signal line 205 in the block diagram on the receiving side of FIG. 2, and FIG. 3D shows a pulse-shaped matched pulse signal of the signal line 211. (E) shows the delayed matched pulse signal on the signal line 212, as shown in FIG.
Is a differential conversion data signal of the source binary data of the signal line 213, FIG. 3 (g) is the delayed differential conversion data signal of the signal line 214, and FIG. 3 (h) is the demodulation of the signal line 215. 3 shows a source binary information data signal.

In the above embodiment, the signal line 10
Although 3 is a fixed potential, the PN code generator 12 may be configured to generate a PN code different from that of the signal line 102.

[0026]

As described above, according to the spread spectrum communication system of the present invention, instead of performing the differential detection using the SAW delay line in the IF stage as in the conventional case, the matched pulse is PN coded in the base band. Since the delay detection is performed with a delay of one cycle, the circuit configuration can be simplified and the cost reduction effect is great. Further, instead of demodulating the data by using the phase information of the carrier wave as in the conventional case, square detection or P
By using a method such as DI, the S / N of the matched pulse can be improved, that is, the BER can be improved.

[Brief description of drawings]

FIG. 1 is a block diagram of a transmitting side in an embodiment of a spread spectrum communication system of the present invention.

FIG. 2 is a block diagram of a receiving side in the embodiment.

FIG. 3 is a signal waveform diagram of each part on the transmission / reception side in the embodiment.

FIG. 4 is a block diagram of a conventional spread spectrum communication system.

FIG. 5 is a signal waveform diagram of each part of the same method.

[Explanation of symbols]

10 differential conversion circuit 11 selection circuit 12, 53 PN code generator 13, 35, 54 clock signal generator 14, 20, 28, 52, 55, 59 multiplier 15, 56 wireless carrier signal generator 16, 22 bandpass Filter 17, 18, 39, 40, 42, 45, 46 AND operation gate element 19, 41 OR operation gate element 20, 43, 44, 47 D type flip-flop 21 Local oscillation frequency signal generator 23 Amplifier circuit 24, 57 SAW correlator 25 Double balanced modulator 26 Low pass filter 27, 31, 58 Matched pulse delay circuit 29 Integrator 30 Matched pulse shaping circuit 32 Set priority flip-flop circuit 33, 51 Delay circuit 34, 50 Exclusive OR gate device 60 Data demodulation circuit

Claims (2)

[Claims] 1. In spread spectrum communication by direct sequence modulation, means for differentially converting source binary data, means for generating a PN code, and polarity of the differentially converted binary data are provided on the transmitting side. In response, at least four means for controlling to selectively output the PN code from the PN code generation and means for multiplying the selectively output PN code by the carrier frequency signal and transmitting the spread spectrum signal. Means for detecting, on the receiving side, the selectively output PN code from the received spread spectrum signal, and detecting the P
Means for generating a matched pulse for each cycle of the N code, means for square-law detecting the matched pulse,
Delay means for delaying the square-law detected matched pulse by one cycle of the PN code; a square-law detected signal as a first input signal; and a signal delayed by the delay means as a second input signal, By inputting the first input signal in the first state among the polarities of the binary data and outputting the second input signal in priority to the input of the second input signal, the second input signal is output in the second state. Means for demodulating the differentially converted data,
A spread spectrum communication system comprising at least five means for delay-detecting the demodulated differentially converted data to demodulate source binary data. 2. The receiving side comprises means for multiplying a square-detected matched pulse by a square-detected matched pulse delayed by one cycle of a PN code, and integrating the multiplication result. Claim 1 characterized by the above.
Spread spectrum communication method described.