JPH02289997A - Semiconductor nonvolatile memory and information processing system using same - Google Patents

Abstract

PURPOSE:To improve the throughput of a system by starting erasure operation according to an external instruction for erasure and then performing the erasure automatically, and carrying out desired operation with an address signal, input data, and a control signal from outside after the erasing operation is completed. CONSTITUTION:An electric batch erasure type EEPROM equipped with memory arrays M-ARY-0 to M-ARY-7 where electrically erasable nonvolatile storage elements are arranged in a matrix is put in the erasing operation according to the external erasure instruction and an erasure control circuit LOGC which reads nonvolatile storage elements at least once after the erasing operation and controls whether the erasing operation is carried on or stopped according to the read information is incorporated. Namely, the EEPROM itself has an automatic erasing function for making a read so as to confirm whether stored information is erased or not, so a microprocessor performs control only by indicating the start of erasure in the erasing operation wherein the EEPROM is mounted on the system, so the throughput of the system is improved.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a semiconductor nonvolatile memory device and an information processing system using the same, such as a batch erasable EEFROM.
(Electrically erasable & programmable
This article relates to read-only memory (read-only memory) and effective technology for use in microcomputer systems using it.

[Conventional technology]

Semiconductor nonvolatile memory devices include EPROMs (erasable and programmable read only memories) whose stored information can be erased by ultraviolet rays and EEPROMs whose stored information can be electrically erased. EFROM is suitable for increasing storage capacity because the area of the memory cell where information is stored is relatively small, but in order to erase the stored information, it is necessary to irradiate the memory cell with ultraviolet light. It is therefore sealed in a relatively expensive windowed pancage. Furthermore, when a programmer writes or rewrites information, there are problems such as the need to remove the EPROM from the system in which it is installed when writing or rewriting new information.

On the other hand, the stored information in EEPROM can be electrically rewritten while it is installed in a system. However, in EEFROM, the area of the memory cells that constitute it is relatively large, for example, EEFROM.
It is about 2.5 to 5 times larger than PROM. Therefore, it is difficult to say that EEPROM is suitable for increasing storage capacity. Therefore, recently, a so-called electrically erasable EEPROM has been developed as a semiconductor nonvolatile memory device intermediate between the two types. Electrical bulk erase type EEPR
OM is a non-volatile semiconductor that has the function of electrically erasing all memory cells formed on a chip or a group of memory cells formed on a chip. It is a storage device. In an electrically erasable EEPROM, the size of the memory cell can be made as small as that of an EPROM. Regarding such bulk erase type EEFROM, the 1980 International Solid State Circuits Conference (IEEE INTH
RNATIONAL SOLID-STATE CIR
CUITS CoNPERENCE) pages 152-1
53, 1987 IEEE International Solid-State Circuits Conference (IEEE INTERNATIONAL S.
QLIn-STATE CIRCUTTS CONFE
IEEE Journal of Solid State Circuits, Vol. 23, No. 5 (1988), pp. 1157 to 1163 (IEEE+J. Solid-Sta)
te Cicuits, vol. 23 (1988)
pp. 1157-1163).

Figure 16 shows the 1987 International Electronic Devices Conference (I
international Electron Dev
This figure shows a schematic diagram of the cross-sectional structure of a memory cell of an electrically erasable EEFROM that was announced at the ICE Meeting. The memory cell in the figure is a normal EFRO
It has a structure very similar to the M memory cell. That is, the memory cell is constituted by an insulated gate field effect transistor (hereinafter referred to as a MOSFET or simply a transistor) having a two-layer gate structure.

In the figure, 8 is a P-type silicon substrate, 11 is a P-type diffusion layer formed on the silicon substrate 8, 10 is a low concentration N-type diffusion layer formed on the silicon substrate 8, and 9 is a P-type diffusion layer formed on the silicon substrate 8.
This is an N-type diffusion layer formed in each of the type diffusion layer 11 and the N-type diffusion layer 10 described above. 4 is a floating gate formed on the P-type silicon substrate 8 through a thin oxide film 7; 6 is a control gate formed on the floating gate 4 through an oxide film 7; 3 is a drain electrode; 5 is a source electrode. In other words, the memory cell in the figure is an N-channel type MOSF with a two-layer gate structure.
It is composed of an ET, and information is stored in this transistor. Here, information is held in the transistor essentially as a change in threshold voltage.

Hereinafter, unless otherwise stated, a case will be described in which a transistor for storing information (hereinafter referred to as a storage transistor) in a memory cell is of an N-channel type.

The operation of writing information into the memory cell shown in FIG. 16 is similar to that of an EFROM.

That is, the write operation is performed by injecting hot carriers generated near the drain region 9 connected to the drain electrode 3 into the floating gate 4. As a result of this write operation, the threshold voltage of the storage transistor as viewed from its control gate 6 becomes higher than that of a storage transistor that has not undergone a write operation.

On the other hand, in the erase operation, by grounding the control gate 6 and applying a high voltage to the source electrode 5, a high electric field is generated between the floating gate 4 and the source region 9 connected to the source electrode 5. Electrons accumulated in the floating gate 4 are extracted to the source electrode 5 via the source region 9 by utilizing the tunneling phenomenon through the oxide film 7 . This erases the stored information.

That is, due to the erase operation, the threshold voltage of the storage transistor as viewed from its control gate 6 becomes low.

In a read operation, a voltage is applied to the drain electrode 3 and the control gate 6 to prevent weak writing to the memory cell, that is, to prevent undesired carrier injection into the floating gate 4. voltage is limited to a relatively low value. For example, a low voltage of about 1 V is applied to the drain electrode 3, and a low voltage of about 5 V is applied to the control gate 6. By detecting the magnitude of the channel current flowing through the storage transistor using these applied voltages, it is determined whether the information stored in the memory cell is "0" or "1".

Generally, in electrical erasing, if erasing is continued for a long time,
The threshold voltage of the storage transistor can be a negative value, unlike the threshold voltage of the storage transistor in a thermal equilibrium state. On the other hand, when erasing stored information using ultraviolet rays as in EPROM, the threshold voltage of the storage transistor, which changes due to the erasing operation, settles to the threshold voltage at the time the memory device was manufactured. That is, the threshold voltage of the storage transistor after the erase operation can be controlled by the manufacturing conditions and the like when manufacturing the storage device.

However, when erasing stored information electrically, the stored information is erased by drawing the electrons accumulated in the floating gate to the source electrode, so if the erasing operation continues for a relatively long time, the write More electrons will be extracted than are injected into the floating gate during operation. Therefore, if electrical erasing is continued for a relatively long time, the threshold voltage of the storage transistor becomes different from the threshold voltage at the time of manufacture. In other words, when an erase operation is performed, in contrast to an EPROM, the threshold voltage does not settle to the threshold voltage determined by the manufacturing conditions at the time of manufacture. The present inventors measured changes in the threshold voltage of a storage transistor due to electrical erasure. FIG. 8 shows the relationship between the erasing time and the threshold voltage of the storage transistor that changes due to erasing, which was obtained through this measurement. In the figure, the horizontal axis represents the erasing time, and the vertical axis represents the threshold voltage of the storage transistor.
+V ths is the voltage with positive threshold voltage, -V
ths indicates that the threshold voltage is a negative voltage. Further, V thv indicates the variation in the threshold voltage after erasing due to variations in manufacturing conditions and the like. It will be understood from this figure that when erasing continues for a relatively long time, the threshold voltage changes to a negative voltage. It will also be understood that the threshold voltage obtained by the erase operation may vary from storage transistor to storage transistor due to variations in manufacturing conditions and the like. It can also be understood from the figure that the variation in threshold voltage increases as the erasing time increases. That is,
As the erase time becomes longer, the difference in threshold voltage between the two storage transistors becomes larger. As described above, when the threshold voltage of the storage transistor becomes negative, the read operation is adversely affected. This will be explained using FIG. 17.

Now, consider the case where stored information is read from the memory cell 12 in the written state. 17 in the figure represents a sense amplifier. In order to put the memory cell 12 into a selected state, a selection voltage during a read operation, for example, power supply voltage Vcc (5V), is applied to the word line 13 to which it is coupled, and the other memory cells 14 and the like are applied with the selection voltage. In order to bring the word line 15 into a non-selected state, the word line 15 and the like are set to a non-select voltage during a read operation, for example, the circuit ground potential OV. If the threshold value of the unselected memory cell 14 connected to the data line 16 corresponding to the memory cell 12 from which storage information is to be read is negative, the voltage of the word line 15, i.e. Even if the voltage of the control gate of the memory cell is set to Ov, an undesired current (unselected leak current) flows to the data line 16 through the unselected memory cell 14, resulting in a delay in read time. This in turn causes erroneous reading.

Further, during a write operation, if the threshold voltage of the storage transistor in the memory cell is negative, there is an adverse effect. Normally, in a write operation using hot carriers, a high voltage (Vpp) for writing applied from the outside is applied to the MO
It is applied to the drain region of the storage transistor in the memory cell via the SFET. The voltage drop across the MOSFET varies depending on the current flowing through it. Therefore, under the conditions where the threshold voltage of the storage transistor takes a negative value as described above, the voltage drop across the MOSFET becomes too large and the voltage applied to the drain of the storage transistor in the memory cell decreases. , becomes lower by the above voltage drop. As a result, the time required for writing increases.

Therefore, in the EEFROM as described above, the value of the threshold voltage after erasing must be controlled with high accuracy.

In order to realize electrical erasure of stored information, conventional EEF
In a ROM, for example, in the EEPROM described in the above-mentioned 1980 IEE International Solid-State Circuits Conference, pages 152-153, each memory cell is connected in series with a storage transistor. A selection transistor was used to block unselected leakage current.

In this EEPROM, a program line is coupled to the control gate of the storage transistor, and a selection line is coupled to the gate of the selection transistor. That is,
The storage transistor and selection transistor are coupled to separate word lines.

Figure 18 also shows the 1987 IEE, International, Solid State
A cross-sectional view of a memory cell of an electrically erasable EEPROM described on pages 76 to 77 of Circuits Conference is shown. The operation of this memory cell is different from that of the memory cell shown in FIG. 16 above! The same, but
The erasure of stored information is different from the memory cell shown in FIG. 16 above.
This is done using the tunneling phenomenon between the floating gate and drain region of the storage transistor. Although this memory cell has only one gate electrode to be connected to the word line, it can be considered that it is substantially composed of two transistors. That is, it can be considered that a memory cell is constituted by a selection transistor and a storage transistor in which a gate electrode and a control gate electrode are integrated. Since this memory cell substantially has a selection transistor as described above, it solves the problem of non-selection leakage current during reading. However, since the write operation is performed using real carriers that require a larger amount of current than when using the tunneling phenomenon, the above-described negative effects of the write operation cannot be improved.

EEPROM, for example, the above-mentioned 1980 IEE International Solid-State Circuits Conference, pages 152-153.
In the EEFROM disclosed in , one memory cell is composed of a storage transistor and a selection transistor connected to different word lines. On the other hand, the memory cells of the electric batch erasing type EF and FROM shown in FIGS. 16 and 18 are constituted by one storage transistor connected to one word line. This becomes clearer by representing the memory cells and the like shown in FIGS. 16 and 18 in circuit diagrams. Therefore, FIGS. 19(A) and 19(B) show circuit diagrams of the above-mentioned memory cell. Figure 19 (B
) shows a circuit diagram of a memory cell announced by the International Solid State Circuits Conference in 1980. In the figure, wi. w2 indicates different word lines, and D indicates a data line. Also, Qs
indicates a selection transistor, and Qm indicates a storage transistor.

FIG. 19(A) shows a circuit diagram of the memory cell shown in FIGS. 16 and 18 above. As can be understood from the figure, one memory cell has its control gate connected to one word line, its drain connected to one data line D, and its source connected to one source line S. It is composed of one connected storage transistor Qm.

In order to select one desired memory cell from a plurality of memory cells during read and write operations, one word line and one data line must be selected in FIG. 19(A). For example, it is connected to the selected word line W,
And one memory cell connected to the selected data line D can be selected. In other words, one memory cell can be defined by one word line and one data line. Note that in FIG. 19(A), the source line S is common to the source line S of all other storage transistors formed on the chip, or is a source line between a predetermined number of memory cells constituting one memory block. S is made common.

Since the memory cell shown in FIG. 19(A) can be constructed with one storage transistor, the area on the chip required to form the memory cell can be made as small as that of an EPROM. However, in order to electrically erase stored information all at once, it is essential to be able to control the threshold voltage of the storage transistor after erasing.

To do this, it is necessary to repeat the operation of dividing the erase into several times, reading each time, checking whether the erase is sufficient, and performing the erase again if it is not sufficient. The above IEE Journal of Solid State Circuits, Volume 23, No. 5
No. 1988, pages 1157 to 1163, an algorithm for controlling the threshold voltage after erasing is proposed. In the above literature,
It is described that this algorithm is executed by an external microprocessor provided separately from the electrically erasable EEPROM. Furthermore, in order to ensure the lower limit voltage Vccmin of the operable power supply voltage during normal reading, it is stated that a verify voltage is generated within the EEPROM chip during reading (during erase verification) in the above algorithm. .

[Problems to be Solved by the Invention] In the above-mentioned conventional technology, since the above-mentioned algorithm is executed by a microprocessor, it is difficult to execute the erasing operation while the electrical batch erasing type EEPROM is installed in the system. is complicated. Furthermore, since it takes a relatively long time to erase the stored information, the microprocessor does not erase the EEPR for this relatively long time.
This has a serious problem in that the system is occupied by the OM erase operation, and the system virtually stops.

An object of the present invention is to provide a semiconductor nonvolatile memory device that can be electrically erased while being installed in a system without reducing system throughput.

Another object of the present invention is to provide an information processing system that substantially realizes electrical erasure while an EEPROM is mounted in the system without reducing system throughput.

Another object of the present invention is to provide an electric batch erasing type EEFR in which erasing is automatically performed simply by giving an erasing instruction from the outside.
The goal is to provide OM.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[Means to solve the problem]

A brief overview of typical inventions disclosed in this application is as follows.

That is, after performing an erasing operation in accordance with an external erasing instruction in an electrically erasable EEPROM that includes a memory array in which electrically erasable storage transistors (nonvolatile memory elements) are arranged in a matrix,
An erase control circuit is built in to perform at least one read operation on the nonvolatile memory element that has undergone the erase operation, and to control the continuation or stop of the erase operation based on the read information. In addition, EE with built-in erase function as mentioned above
When a PROM is installed in an information processing system including a microprocessor, an erase operation is automatically performed by an internal erase control circuit in a state separated from the microprocessor in accordance with an erase instruction from the microprocessor.

[For production]

According to the above-mentioned means, since the EEFROM itself has an automatic erasing function that involves reading to confirm whether or not stored information has been erased, the microprocessor can EEFR
It takes only a short time to control the OM to instruct the start of erasing, and the burden on the microprocessor is significantly reduced.

〔Example〕

FIG. 20 shows an electric batch erase type EE to which the present invention is applied.
A block diagram of FROM (hereinafter also referred to as flash EEPROM) is shown. Although not particularly limited, each circuit block shown in the figure is formed on one semiconductor substrate using well-known semiconductor integrated circuit technology. In addition, in the same figure, the “○” mark indicates the flash EEFR.
External terminals provided on the OM are shown.

In the same figure, each of M-AR'l-0 to M-ARY7 is a memory array having a similar configuration, and although not particularly limited, each has a plurality of word lines and a memory array that intersects with these word lines. multiple data lines placed in
It has a memory cell provided at each intersection of a word line and a data line.

XADB is a row address buffer, which receives an external row address signal AX supplied via an external terminal.
An internal complementary row address signal is formed according to the row address signal AX. XDCR is a row address decoder which receives an internal complementary row address signal formed by the row address buffer XADB and decodes this internal row address signal. Although not particularly limited, in this embodiment, the row address buffer XADB and the row address decoder XDCR are connected to the memory array M-
It is common to ARY-0 to M-ARY-7. That is, the row address decoder XDCR decodes the internal complementary row address signal to
The memory arrays M-ARY-0 to M-A. A word line selection signal is generated to select one word line designated by external row address signal AX from a plurality of word lines in each of RY-7. As a result, one word line is selected from each of the memory arrays M-ARY-0 to M-ARY-7.

In the figure, YADB is a column address buffer sofa, and external force RAM address signal A.YADB is supplied via an external terminal. Y, and forms an internal complementary output RAM address signal in accordance with this external column J1 address signal AY. YDC
R is a column address decoder which decodes the internal complementary output RAM address signal formed by the column address buffer YADB and outputs the external column address signal A.
A data line selection signal according to Y is formed. Although not shown in the figure, memory arrays M-ARY-0 to M-A
Each of the RY-7s receives the data line selection signal and selects one data line designated by the external force RAM address signal AY from among the plurality of data lines in the memory array corresponding to the memory array. A column switch is provided that couples to a common data line (not shown).

In this way, memory array 4M-ARY10~M-
In each of ARY-7, one word line and one data line are selected according to the external row address signal AX and external input RAM address signal AY, and the intersection of the selected word line and data line is selected. The memory cell provided in is selected. That is, the memory cell coupled to the selected word line and data line is selected from a plurality of memory cells within the entire memory array. As a result, one memory cell is selected from each memory array.

Although not particularly limited, in this embodiment, write operations or read operations are performed almost simultaneously on memory cells selected from each memory array. That is, information is written or read in units of 8 bits.

For this purpose, the EEPROM of this embodiment is provided with eight external input/output terminals I/00 to I/07, which connect memory arrays M-ARY-0 to M-ARY-7 and corresponding external Between input/output terminals 1/00 to ■/07, data input buffer DIB, data output buffer DOB,
MOSFETQI for sense amplifier SA and switch
8, Ql 6 is provided.

Taking the memory array M-ARY-0 as an example, in the case of a write operation, the selected memory cell is a MOSFET turned on by the write control signal wr.
MOSFET Q coupled to the output node of the data input buffer DIR-0 via QI 8 and turned on by the read control signal re in case of a read operation.
It is coupled to the input node of sense amplifier SA-0 via I6.

The input node of the data bus sofa DIB-0 is coupled to the external input/output terminal ■/00, and the sense amplifier SA is connected to the external input/output terminal ■/00 via the data output bus sofa DOB10.
-0 output nodes are coupled. remaining memory array M
-ARY-1 to M-ARY-7 are also coupled to external input/output terminals I/Ol to I/07 in the same manner as the above-described memory array M-ARY-0.

In the same figure, LOGG is an internal circuit for performing an automatic erase control operation, which will be explained in detail later. Also, CN
TR is a timing control circuit, and external terminals CE and OE
, WE, EE, and Vl) in response to external signals or voltages supplied to I) and signals from the internal circuit LOGC, timing signals including the above-mentioned control signals wr, re, etc. are formed.

In the figure, Vcc is an external terminal for supplying a power supply voltage Vcc to each timing block, and Vss is an external terminal for supplying a circuit ground potential Vss to each circuit block.

In the above description, the word line is divided for each memory array, but the word line may be shared by each memory array.

FIG. 1 shows the flash EEF shown in FIG. 20 above.
A detailed block diagram of one memory array MARY in the ROM, its peripheral circuits, a row address buffer, a column address buffer, a row address decoder, a column address decoder, a timing control circuit CNTR, and an internal circuit LOGC is shown. As can be easily understood from the above explanation, each circuit element shown in FIG. 1 may be a known CMOS (complementary MO
S) Formed on a single semiconductor substrate, such as single crystal silicon, using integrated circuit manufacturing techniques. In the figure, a P-channel MOSFET is distinguished from an N-channel MOSFET by an arrow added to its channel (back gate) portion. This also applies to other drawings.

Although not particularly limited, the integrated circuit is formed on a semiconductor substrate made of single-crystal P-type silicon. N channel MOS
The FET consists of a source region, a drain region formed on the surface of a semiconductor substrate, and a polysilicon layer formed on the surface of the semiconductor substrate between the source region and the drain region with a thin gate insulating film interposed therebetween. Consists of a gate electrode. The P-channel MOSFET is formed in an N-type well region formed on the surface of the semiconductor substrate. As a result, the semiconductor substrate forms a common substrate gate for a plurality of N-channel MOSFETs formed thereon, and is supplied with the ground potential Vss of the circuit. The N-type well region has a P-channel MOSFET formed thereon.
Configure the substrate gate of T. P-channel MOSFET
The substrate gate, that is, the N-type well region, has a power supply voltage V
cc is supplied. However, although not particularly limited to the N-type well region where the P-channel MOSFET that constitutes the circuit that processes high voltage higher than the power supply voltage Vcc is formed, the voltage applied from the outside via the external terminal Vl)+1 is A high voltage pp or a high voltage generated inside the EEPROM is supplied.

Alternatively, the integrated circuit may be formed on a semiconductor substrate made of single crystal N-type silicon. In this case, the N-channel MOSFET and the nonvolatile memory element are formed in the P-type well region, and the P-channel MOSFET is formed on the N-type semiconductor substrate.

Hereinafter, the flash EEPROM of this embodiment will be explained in more detail using FIG. 1, but in order to facilitate understanding, the following explanation may overlap with the explanation of FIG. 20 mentioned above.

Although not particularly limited, the flash EEFR of this embodiment
In OM, an internal complementary address signal is formed by address buffers XADB and YADB that receive X (row) and Y (column) address signals AX and AY supplied from the outside via external terminals, and address decoders XDCR and YD.
Supplied to CR. Although not particularly limited, the address buffers XADB and YADB are activated by an internal chip selection signal i, and external address signals AX. AY is taken in, and a complementary address signal consisting of an internal address signal in phase with the external address signal supplied from the external terminal and an internal address signal in opposite phase is formed.

In addition, the address buffers XADB and YADB have
In addition to the above-mentioned chip selection signal i, a signal ES indicating an erase mode, internal address signals AXI, AY1, etc. are supplied. However, these signals BS, AXI,
YAI, etc. are signals used in erase mode, which will be described later, and in normal write or read mode,
It does not affect the operation of the address bus sofas AXDB and YADB.

The row (X) address decoder XDCR is activated by the address decoder activation signal DE and outputs 1 in accordance with the complementary address signal from the corresponding address buffer XADB.
A selection signal for selecting one word line from a plurality of word lines in the memory array M-ARY is formed.

Column (Y) address decoder YDCR is also activated by the address decoder activation signal DE, and connects one data line to multiple data in memory array M-ARY according to the complementary address signal from the corresponding address buffer YADB. Form a selection signal to select from the lines.

The memory array M-ARY includes a plurality of word lines, a plurality of data lines arranged to intersect with the word lines, and a plurality of memory cells provided at each intersection of the word line and the data line. have In the figure, this memory array M
A portion of -ARY is illustratively shown as representative. That is, in FIG. 1, the word line WIW2 among the plurality of word lines and the data lines DI and D among the plurality of data lines are shown.
2. Dn and memory cells provided at the intersections of these data lines and word lines are exemplarily shown.

As described in FIG. 19(A), each memory cell is constituted by one memory transistor (nonvolatile memory element). That is, each memory cell is constituted by one storage transistor having a stacked gate structure having a control gate and a floating gate. The memory cell exemplarily shown in the figure is a storage transistor (non-volatile storage element) Ql.
~Q6. As described above, the storage transistor has a UQ structure similar to that of an EFROM storage transistor, although it is not particularly limited thereto. However, as mentioned earlier and later, the erase operation is performed electrically using the tunneling phenomenon between the floating gate and the source region coupled to the source line CS. This is different from the method of erasing the EPROM used.

In the memory array M-ARY, the control gates (memory cell selection nodes) of the storage transistors Q1 to Q3 (Q4 to Q6) arranged in the same row are connected to the corresponding word line W1 (W2), and the same Storage transistors Ql, Q4 to Q3, Q6 arranged in columns
Drain regions (input/output nodes of memory cells) are connected to corresponding data lines D1 to Dn, respectively. A source region of the storage transistor is coupled to a source line CS.

In this embodiment, although not particularly limited, an N-channel MOSFET QI O and a P-channel MOSFET, which are switch-controlled by the erase circuit ERC, are connected to the source line CS.
ETQI 7 is connected. The above erase circuit ERC
In the write mode and the read mode, the N-channel MOSFET QIO is turned on so that the source line CS is supplied with the ground potential Vss of the circuit. On the other hand, in the erase mode, the P-channel MOSFET Ql7 is turned on so that the high voltage vpp for erasing is applied to the source line CS.

If it is desired to partially erase the memory array M-ARY, the memory transistors arranged in a matrix are vertically divided into M blocks, and each block has a source line corresponding to the source line. provided for each. As described above, each of the source lines CS provided in each block has an erase circuit E as described above.
RC and MOSFET QI O. Ql 7 are provided respectively. In this case, each erasing circuit must be designated by an address signal in order to determine which block among the plurality of blocks is to be erased. In the embodiment described above, the stored information of all memory cells constituting the memory array M-ARY is erased at once. In this case, there is one source line CS, and the erase circuit ERC and MOSFETs QIO and Q17 are provided correspondingly.

In the EEPROM of this embodiment, although not particularly limited, writing/writing in units of multiple bits such as 8 bits is possible.
Since reading is performed, the memory array M-ARY
There are a total of 8 sets (M-ARY-
A plurality of sets such as 0 to M-ARY-7) are provided. Note that when writing or reading information in units of 16 bits, for example, the memory array M-ARY
There will be 16 sets of

Each data line D1 to Dn constituting the one memory array M-ARY is connected to the RAM address decoder YDCR.
It is selectively connected to the common data line CD via column selection switch MOSFETs Q7 to Q9 (column switches) which receive selection signals formed by the MOSFETS. The common data line CD includes a write data input buffer DIB that receives write data input from an external terminal I/O.
The output terminal of is connected via switch MOSFETQI8. Similarly, the remaining seven memory arrays M-AR
As described in FIG. 20, a column selection switch MOSFET similar to that described above is also provided for Y, and a selection signal from the column address decoder YDCR is supplied thereto. Note that a different column address decoder may be provided for each memory array, and the column selection switch MOSFET may be switch-controlled by a selection signal from the corresponding column address decoder.

A common data line CD provided corresponding to the memory array M-ARY is coupled via a switch MOSFET Q16 to an input terminal of a first stage amplifier circuit forming an input stage circuit of the sense amplifier SA. For convenience, MOSFETs QI 1 to Q1 that constitute the first stage amplifier circuit are shown below.
5, and CMOS inverter circuits N1 and N2 in cascade form.
The circuit constituted by these will be called the sense amplifier SA. Sense Ambu SA has the following information when reading normally.
A relatively low power supply voltage Vcc is supplied to the power supply voltage terminal Vcc/Vcv as a power supply for the sense amplifier SA, and during erase verification to be described later, a voltage Vcv having a potential lower than the power supply voltage VccO value is supplied to the power supply voltage terminal Vcc as a power supply. /Vcv is supplied.

The common data line CD illustrated above is connected to a MOSFET Q that is turned on by the read control signal re.
Through I6, N-channel type amplification MOSFETQ
Connected to the source of I1. This amplification MOSFETQ
Between the drain of I1 and the power supply voltage terminal Vcc/Vcv of the sense amplifier SA, there is a P-channel type load MOSFE whose gate is applied with the circuit ground potential Vss.
TQI 2 is provided. Above load MOSFETQ
I2 performs an operation such as flowing a precharge current to the common data line CD for a read operation.

In order to increase the sensitivity of the above amplification MOSFET QI 1,
Common data line C via switch MOSFET QI 6
The voltage of D is the voltage of N-channel drive MOSFETQ13.
It is supplied to the gate of a drive MOSFET QI3, which is an input of an inverting amplifier circuit consisting of a P-channel type load MOSFET Q14. The output voltage of this inverting amplifier circuit is supplied to the gate of the amplification MOSFET QI1. Furthermore, during the non-operation period of the sense amplifier SA,
In order to prevent the sense amplifier SA from consuming unnecessary current, an N-channel MOSFET is connected between the gate of the amplification MOSFET QI 1 and the ground potential point Vss of the circuit.
ETQI 5 is provided. The sense amplifier operation timing signal B is commonly supplied to the gates of this MOSFETQ15 and the P-channel MOSFETQ14.

When reading a memory cell, the sense amplifier operation timing signal i is set to a low level.

This turns MOSFETQI 4 on and MOSFETQI4 turns on.
SFETQI 5 is turned off. A storage transistor constituting a memory cell has a threshold voltage higher or lower than the selected level of a word line during a read operation, according to data written in advance.

In the read operation, each address decoder X described above
If one memory cell selected from a plurality of memory cells constituting the memory array M-ARY by DCR and YDCR is in the off state even though the word line is set to the selection level, the common data Line CD is M
The current supplied from OSFETs Q12 and Qll makes it high level, which is limited to a relatively low potential. On the other hand, if the selected memory cell is in the on state due to the selection level of the word line, the common data line CD
is set to a low level limited to a relatively high potential.

In this case, the high level of the common data line CD is connected to an inverting amplifier circuit (MOSFETQI) that receives this high level potential.
3, Ql 4) is supplied to the gate of MOSFET QI 1, thereby limiting it to a relatively low potential as described above. On the other hand, the low level of the common data line CD is connected to an inverting amplifier circuit (MOSFETQ) that receives this low level potential.
By supplying the relatively high level voltage formed by I 3 , Q14) to the gate of MOSFET QI 1, it is limited to a relatively high potential as described above.

The data line discharge MOSFETs Q19 to Q21 provided between each data line D1 to Dn and the source line have a gate bias signal DS supplied to their gates set to an intermediate level as described later, so that the column address decoder YD
The charge on the data line that is not selected by CR, that is, the data line that is in the non-selected state is discharged.

Note that the amplification MOSFET QI 1 performs the amplification operation of the gate-grounded source input, and outputs the output signal to the CM
It is transmitted to the input of the OS inverter circuit N1. The CMOS inverter circuit N2 receives a signal SO obtained by waveform shaping the output signal of the CMOS inverter circuit Nl (the memory array M-ARY in FIG. 1 is the same as the memory array M-ARY-0 in FIG. 20).
) to form the corresponding data output buffer DOB
-0 input. The data output buffer DOBO is
The above signal SO is amplified and sent from the external terminal ■/00. In addition to the read data output function described above, the data output bath sofa is provided with the following functions.

As will be described later with reference to FIG. 11, the data output buffers DOB-0 to DOB-6 corresponding to I/00 to I706 among the eight external input/output terminals receive the data output buffer activation signal Do. 3 including high impedance due to Do
Performs status output operation. On the other hand, data output buffer DOB-7 corresponding to external input/output terminal I/07 is
It is controlled by data output bath sofa activation signal signals DO7 and Do7, which are different from the signals Do and Do. This data output buffer DOB-7 is used in a data polling mode in which the internal erased state of the EEPROM is read out to the outside. In addition, the write data supplied from the external input/output terminal I/O is transferred to the data input cover sofa DIB.
The data is transmitted to the common data line CD via the common data line CD. As shown in FIG. 20, between the common data line and the external input/output terminal corresponding to other memory arrays M-ARY,
A read circuit consisting of an input stage circuit, sense amplifier SA, and data output buffer DOB similar to the above, and a write circuit consisting of a data input buffer sofa DIB are provided, respectively.

timing control circuit CNTR may be particularly limited) and chip enable signal GE supplied to vpp.
, output enable signal OE. A write enable signal WE, an erase enable signal EE, a high voltage for writing/erasing Vl)p, a pre-write pulse PP supplied from an internal circuit LOGC that controls an automatic erase operation as described later, and a signal BS indicating an erase mode. , the decoder control signal DC, the erase verify signal EV, the automatic erase mode setting delay signal AED, the sense amplifier activation signal VE during verify, etc. At the same time, it is selectively supplied to an address decoder etc. to generate a read low voltage Vcc/erase verify low voltage Vc.
The voltage of v/high voltage for writing vpp is switched, and one of these voltages is selectively output. The above-mentioned signals PP, B formed by the above-mentioned internal circuit LOGC
S, D.C. EV, AED, VE, etc. are other than erasure (7)
%1 mode does not affect the operation of the timing control circuit CNTR. That is, only in the erase mode, the signals PP, ES, DC. EV, AED, VE, etc. are enabled, and various signals for erasing operation according to these signals are generated by the timing control circuit CNTR.

6 and 7, the timing control circuit CNTR
A circuit diagram of an embodiment of the main part of the circuit is shown. Table 1 below shows how the flash EEPRO is connected via the external terminals.
Each external signal supplied to M and the corresponding operation mode are shown, and Table 2 shows some internal timing signals among the internal timing signals formed based on each external signal. . In Tables 1 and 2, H indicates a high level, L indicates a low level, and VpI) indicates a voltage (eg, about 12 V) higher than the power supply voltage Vcc (eg, 5 V). In the external terminal I/O columns of Tables 1 and 2 above, Hz indicates a high impedance state, input indicates data input, and output indicates data output. In particular, output (I/07) indicates the external input This indicates that the output terminal I/07 is a data output.

Table-2 Also, in Table-1 and Table-2, * indicates high level (H)
However, it indicates that a low level (L) is also acceptable, and 0 indicates that from the internal circuit LOGC to the timing control circuit CN.
This indicates that the level changes depending on the signal supplied to the TR.

How to read Tables 1 and 2 will be explained using the read mode as an example. The same applies to other modes, so it will be easy to understand from the following example.

From external to flash EEPROM, low level (L)
A chip enable signal CE, an output enable signal OE, a high level (H) write enable signal WE, and an erase enable signal EE are supplied, and a low voltage such as the power supply voltage Vcc is supplied to the external terminal Vpfl of the flash EEFROM. is applied, it is determined that the read mode has been instructed by the timing control circuit CNTR, and the timing control circuit CNTR and internal circuit LOGC output internal signals VP, EV, wp, Wr%.
AED% DC% ES% POLM% Set each of PP to low level (L) and internal signals SC, re, D
Set each of E to high level (H).

Then, the data held in the memory cell designated by the address signal is transferred to the external input/output terminal I/O.
Output from 0-1/07.

In this specification, the same signals or the same terminals are indicated by the same symbols.

Also, a signal represented by a symbol with a ``1'' placed above an alphabetic letter has a phase difference with respect to a signal represented by the same alphabetic letter without a ``1'' placed above it. It shows an inverted signal. For example, the symbol vp is a signal whose phase is inverted with respect to the signal represented by the symbol vp. Note that this signal vp is
When high voltage vpp is applied to the external terminal vpp, it becomes high level (Vcc), and otherwise it becomes low level (Vcc).
Vss).

The operations of the circuits shown in FIGS. 6 and 7, which constitute the main parts of the timing control circuit CNTR, will not be explained in detail, but Tables 1 and 1-2 above showing the operation modes will not be explained in detail.
This will be easily understood from the explanation of the operation described below.

When the chip enable signal CE is set to a high level and no high voltage is supplied to the external terminal vpp, the flash EEPROM is in a non-selected state.

Chip enable signal CE is set to low level, output enable signal OE is set to low level, write enable signal WE is set to high level, erase enable signal EE is set to high level, and high voltage is not supplied to external terminal vpp. In this state, the read mode is set as described above, and the internal chip enable signal i is set to a low level, and the address decoder activation signal DE and the sense amplifier operation timing signal ``L read signal re'' are set to a high level. At this time, each of address decoders XDCR, YDCR, and data input circuit DIR is supplied with a low voltage Vcc (approximately 5V) as its operating voltage.
) is supplied from the timing control circuit CNTR.

As a result, the sense amplifier SA becomes operational and the read operation as described above is performed. At this time, by the circuit shown in FIG. 6, the data line discharge MOSFET
Inactivation signal SB is set to low level. Accordingly, the N-channel MOSFET receiving the deactivation signal SB
(Fig. 7) is turned off, and similarly the inactivation signal SB
The receiving P-channel MOSFET (FIG. 7) is turned on. At this time, since the sense amplifier operation timing signal i is set to high level, the N-channel MOSFET (Fig. 7) receiving this signal sc is turned on, and the P-channel MOSFET receiving the signal sc is turned on.
(FIG. 7) is turned off. Therefore, the data line discharge MOSFET gate bias signal DS is applied to two P-channel MOSFETs arranged in series (Fig. 7).
and three N-channel MOSFETs (FIG. 7), and control the data line discharge MOSFETs Q19 to Q21 provided on the data lines of the memory array M-ARY to set the non-selected state. Discharge the charge on the data line.

The chip enable signal CE is set to low level, the output enable signal OE is set to high level, the write enable signal W1 is set to low level, the erase enable signal EE is set to high level, and a high voltage (for example, about 12 mm) is applied to external terminal vpp. ) is supplied, the write mode is entered. At this time, the internal chip enable signal 5 goes to low level, and the address decoder activation signal DE. Write mode signal wp, write control signal w
r and write pulse PG are each set to high level, and gate bias signal DS, sense amplifier operation timing signal i, read control signal re, and data output bath sofa activation signals DO and DO7 are each set to low level. The address decoders XDCR and YDCR are each activated by the high level of the signal DE, and the one designated by the external address signals AX, AY is output from the plurality of word lines and the plurality of data lines constituting the memory array M-ARY. One word line and one data line are selected. At this time, address decoders XDCR, YD
The CR and data input cover sofa DIB has a high voltage Vpp as its operating voltage, which is connected to the timing control circuit CNTR.
Supplied from. As mentioned above, since the read control signal re is set to low level at this time, the MOSFET
Q16 is turned off, and the discharge MOSFETs Q19 to Q2 are turned off by the gate bias signal DSO low level.
1 is also turned off, and the sense amplifier SA is inactivated by the low level of the sense amplifier operation timing signal sc. Further, at this time, since the data output buffer activation signals DO and D07 are at a low level, each of the data output buffer sofas DOB-0 to DOB-7 is inactivated. Note that the configuration of the data output bath sofa DOB will be described later using FIG. 11.

The word line to which the selected node of the memory cell to be written is coupled, in other words, the selected word line, has its potential set to the high voltage by the address decoder XDCR to which the high voltage vpp is supplied as its operating voltage. A high voltage according to Vpp, for example about 12V, is applied. On the other hand, the selected data line is brought to a high or low potential by the data input bus sofa DIB, depending on the information to be written. The memory cell is constituted by the storage transistor shown in FIG. 16, as described above. In a memory cell whose selection node is coupled to the selected word line and whose input/output node is coupled to the selected data line, that is, in the selected memory cell, electrons are sent to the floating gate of the storage transistor constituting it. When injecting, the potential of the selected data line is set to the MOSFET QI 8 and the data input bath sofa DIB, which are turned on according to the high level of the write control signal wr.
High voltage Vl1! ) to a high voltage according to

As a result, a channel saturation current flows through the storage transistor, and in the pinch-off region near the drain region coupled to the data line, electrons accelerated by the high electric field are ionized, generating high-energy electrons, so-called hot electrons.

On the other hand, the potential of the floating gate of this storage transistor is a value determined by the voltage of the control gate connected to the word line, the voltage of the drain region, the capacitance between the semiconductor substrate and the floating gate, and the capacitance between the floating gate and the control gate. becomes. This results in
Hot electrons are attracted to the floating gate, and the potential of the floating gate becomes negative. By making the potential of the floating gate negative, the threshold voltage of the storage transistor into which electrons have been injected increases and becomes higher than before the electron injection.

On the other hand, when electrons are not injected into the floating gate of the storage transistor constituting the selected memory cell, the threshold voltage of the storage transistor does not increase and is maintained at a relatively low value. In order to prevent electron injection into the floating gate of the storage transistor constituting the selected memory cell, the drain region of the storage transistor is
Selected data line, MOSFE turned on above
A low voltage that does not generate hot electrons in the pinch-off region near the drain region may be applied through the TQ18 and the data buffer DIR. Whether to apply the above-mentioned high voltage or the above-mentioned low voltage to the drain region of the storage transistor of the selected memory cell is determined depending on the information to be written. The data input buffer DIB, which will be described later with reference to FIG. is transmitted to the selected data line.

A storage transistor whose threshold voltage is raised by injecting electrons into its floating gate is
In the read mode, even if a selection signal of a selection level (for example, 5V) is supplied to the control gate, that is, even if the word line to which the selection node is connected is selected, it will not become conductive and will remain non-conductive. state. On the other hand, a storage transistor in which no electrons were injected
Since its threshold voltage is maintained at a relatively low voltage, in the read mode, when a selection signal at a selection level is supplied, that is, when a word line is selected, it becomes conductive and current flows.

Note that in the write mode, high voltage is not applied to the control gate and/or drain region of the storage transistor constituting the memory cell that is not selected. Therefore, electrons are not injected into the floating gate, and the threshold voltage of the storage transistor does not change.

Chip enable signal CE is set to low level, output enable signal OE is set to low level, write enable signal WE is set to high level, erase enable signal EE is set to high level, and high voltage vpp is supplied to external terminal vpp. If it is, the write verify mode is set.

The state is the same as the read mode, except that the external terminal vpp is supplied with the high voltage Vpl). The operating voltage is switched from the high voltage Vpp to the low voltage Vcc and supplied to each of the address decoders XDCR, YDCR and the data input circuit DIB.

In the write/inhibit mode shown in Tables 1 and 2 above, each decoder is activated, but the high voltage VpI for writing/erasing is not supplied to each decoder. In this mode, the gate bias signal DS is set to a high level and the data line is discharged during a write/write verify/erase preparation period.

Chip enable signal CE, erase enable signal E
E is set to low level, and the output enable signal O
E, write enable signal WE is set to high level and high voltage vpp is applied to external terminal vpp,
Erase mode is started.

As will be described later using FIG. 21, the combination of these external signal voltages instructs the start of the erase mode, and it is not the case that the erase mode will end unless this state is maintained. .

Regarding the erase mode in the flash EEPROM of this embodiment, the operation flowchart in FIG. 2 showing an example of the algorithm, the specific circuit diagram of the main part of the internal circuit LOGC shown in FIGS. 3 and 4, and the This will be described in detail below with reference to the operation timing diagram shown in FIG.

The internal circuit LOGC functions as an erase control circuit.

The circuit shown in FIGS. 3 and 4 above performs sequence control for executing the algorithm shown in the flowchart of FIG. 2, so the circuit shown in FIG.
It will be easily understood from the explanation of the erase operation mode with reference to the operation timing diagram in the figure.

In the flowchart of FIG. 2, prior to the actual erasing operation, a series of pre-write operations as indicated by dotted lines in the figure are executed. This is the memory array M- before erasing.
This is done because the information stored in the memory cell in ARY, in other words, the threshold voltage of the storage transistor, varies in height depending on whether or not writing is performed (whether or not electrons are injected into the floating gate) as described above. That is, this is performed because the memory array M-ARY before erasing includes storage transistors whose threshold voltages are increased and storage transistors whose threshold voltages are maintained at a relatively low value.

The above pre-write operation, prior to the electrical erase operation,
This means writing to all storage transistors. As a result, this embodiment can automatically erase internal memory cells that are in an erased state, which are unwritten memory cells (substantially no electrons have been injected into the floating gates of the storage transistors constituting the memory cells). This operation prevents the threshold voltage of the storage transistor in the unwritten memory cell from becoming a negative threshold voltage.

In this pre-write operation, first, in step (11), address setting is performed. That is, the address counter circuit is set so that the address signal for selecting each memory cell is generated by the address counter circuit. With this address setting, the address counter circuit generates an address signal indicating the address of the memory cell to which writing is to be performed first, although this is not particularly limited.

In step (2}, a write pulse is generated;
Writing (pre-writing) is performed on a memory cell designated by an address signal generated by an address counter circuit.

After this writing, step (3) is executed.

In this step (3), address increment is performed in which the address counter circuit is operated to increment (+1).

Then, in step (4), it is determined whether the address signal generated by the address counter circuit points to the final address. If the above pre-write has not been performed up to the final address (No), the process returns to step (2) and the pre-write is performed. This is repeated until the final address. After step (3) of incrementing the address as described above, it is determined whether or not prewriting has been performed up to the final address, so the address that is actually determined is the final address +1. Of course, the step (3) of incrementing the address may be provided after the step (4) of determining the final address.

In this case, if the determination is NO, step {2} is executed from step (4) so that the address is incremented.
Step (3) is provided on the route back to .

When the pre-write as described above is performed up to the final address (YES), the following erase operation is performed next.

In step (51), initial setting of addresses for erase operation is performed. That is, initial design of address signals is performed for the address counter circuit. In this embodiment, all memory cells in the flash EEPROM are set at once. The initial setting of this address has no special meaning for the erase operation itself.This address setting is required for the verify operation (erase verify) that is performed after the erase operation. .

In step (6), an erase pulse for batch erasing is generated, and an erase operation is performed. Thereafter, a verify operation is performed in step (7) according to the address setting. In this verify operation, as will be described later, the operating voltage is, for example, 3.5V, which is lower than the low power supply voltage Vcc (for example, 5V) supplied via the external terminal Vcc.
The read operation as described above is performed under a low voltage Vcv such as Vcv.

That is, address decoders XDCR, YDCR and sense amplifier SA have power supply voltage Vc as their operating voltage.
The above-mentioned low voltage Vcν is supplied instead of c. Note that at this time, the internal circuit LOGC, the timing control circuit C
A power supply voltage Vcc is supplied to the NTR as its operating voltage. In this read operation, if the read signal is "0", that is, if the storage transistor is turned on, it is recognized that the threshold voltage of the storage transistor is in the erased state of 3.5V or less. , then step (8) is executed. This step (
In step 8), the address of the address counter circuit is incremented. Then, in step (9), as in the case of the pre-write operation described above, it is determined whether or not the address signal formed by the address counter circuit points to the final address. If it is not the final address (NO), the process returns to step (7) and the same erase verify operation as described above is performed. This is repeated until the address counter circuit points to the final address, thereby completing the erase operation. As mentioned above, in this embodiment, the information stored in the memory array M-ARY is erased all at once, so in the above erase operation, the memory cell whose threshold voltage is the highest due to the write operation among all the memory cells is The number of times of erasing is determined by the storage transistor. In other words, the storage transistor with the highest threshold voltage can be read at the above 3.5V.
That is, application of the erase pulse (erase operation) in step (6) is performed until a low threshold voltage is obtained. Then, it is detected by the erase verify operation in step (7) whether or not this storage transistor has the low threshold voltage. That is, step (
Based on the verification result in step 7), it is determined whether or not to apply an erase pulse (erase operation) in step {6).

The erase operation mode as described above will be explained in detail with reference to the operation timing diagram of FIG. 5 and the specific circuits of FIGS. 3 and 4. In addition, in the following explanation, the above-mentioned FIG. 6, FIG. 7, and Table 1. See also Table-2.

Chip enable signal CE is set to low level, output enable signal OE is set to high level, write enable signal WE is set to high level, and external terminal Vf is set to high level.
l1) is supplied with a high voltage vpp<for example, about 12V), the timing control circuit CN shown in FIG.
As is clear from the specific circuit of the TR and Tables 1 and 2, the internal chip enable signal 4 and the erase start signal 4 are at low level. Therefore, erase enable signal EE
When the signal changes from high level to low level, the frimb flop circuit FFI is set accordingly.

As a result, the signal ES indicating the erase mode changes from high level to low level and enters the erase mode. Internal signal E
S2 changes to a low level after a certain time delay determined by the delay time of the delay circuit Di. When the signal ES indicating the erase mode changes to high level, it is fed back to the no gate circuit NoR1. Therefore, the erase mode signal ES is held by this feedback operation until the erase mode signal ER is generated. Therefore, during the erase mode, the NOR gate circuit NOR 1 no longer accepts signal changes of CE, OR, WE, and EE represented by the internal signal ec. That is, the erase control circuit LOGC no longer accepts external control signals such as those described above, and executes the erase sequence. In other words,
This erase mode signal BS prevents changes in the external control signal from affecting internal operations. For example, in FIG. 6, the circuit forming the decoder activation signal DB is not affected by the signal ce based on the chip enable signal GE because the erase mode signal ES is set to a high level.

Before performing the erase operation, the pre-write operation is performed. For this pre-write operation in which all bits are written for a certain period of time, the oscillation circuit 01 is activated by the address increment start signal ATS and the oscillator control signal OSC.

The output signal of the oscillation circuit 01 is frequency-divided by a 4-bit binary counter circuit BCSI to generate a pre-write pulse PP. The generation of this pre-write pulse PP is not limited to the one formed from the frequency-divided signals OS3 and OS4 obtained by frequency division as described above and the pre-write control signal PC, but can take various modifications. Needless to say, it is.

The output signal of the counter circuit BCSI is supplied to a binary counter circuit BCS2. This counter circuit BCS2
operates as an address counter circuit and generates internal address signals A51, A61, . . . A21.

These address signals A5I, A6T, . . . A2I are input to address bus sofas XADB, YADB.

The erase mode signal ES is used to switch the inputs of address buffers XADH and YADB. Each of address buffers XADB and YADB is composed of a plurality of unit circuits having similar configurations.

FIG. 9 shows the unit circuit. As shown in the figure, when the erase mode signal BS is at a high level, the unit circuit inputs external address signals AX. AY is switched to internal address signals AXI and AYI, respectively, to form internal complementary address signals ax, ax and ay+ay to be transmitted to address decoders XDCR and YDCR. That is, due to the high level of the signal ES, the unit circuits of address buffers XADB and YADB are prevented from accepting external address signals AX and AY from external terminals, and internal address signals corresponding to internal address signals A51, A61, . . ., A21 are disabled. Accepts address signals AXI and AYE. Although not particularly limited, the counter circuit BCS2 has the same number of internal address signals A as external address signals AX, AY.
Form XI, AYI. As a result, one memory cell from each memory array M-ARY is selected by internal address signals AXI and AYI. For this selected memory cell, the data input buffer DIB-
Information is supplied from 0 to DIB7 and written (pre-write). In this case, data input buffer DIB-0~
DIB-7 forms information based on pre-write pulse PP rather than data from external terminals /oO to I/07.

When prewriting is completed for all addresses in the memory array, the final address signal END becomes high level, and the flip-flop circuit FF2 is set. As a result, the automatic erasing mode setting {i-number AE becomes high level and the erasing period begins. The internal signal PSC changes the address increment signal AIS and the oscillator control signal OSC to low level, and the oscillation circuit 01 and the counter circuit BCS
I, BCS2 is reset. The delay time set by the delay circuit D2 is a preparation period for erasing, and is used to set all word lines to a non-selected state or to discharge data lines. Thereafter, the erase start signal ST becomes high level for a certain period of time set by the delay circuit D4, and the flip-flop circuit FF3 is turned on. After the time set by the delay circuit D5, the erase pulse EP becomes low level. Due to the low level of the erase pulse EP, a high voltage vpp is applied to the source of the memory cell via the erase circuit ERC as described above. Although not particularly limited, the erase circuit ERC is a circuit shown in FIG. 10.

The signal EP is basically connected to the gate of the P-channel MOSFET QI 7 via an inverter circuit whose operating voltage is a low voltage Vcc and an inverter circuit with a level shift function whose operating voltage is a high voltage Vpp. Vc
The signal is transmitted to the gate of the N-channel MOSFET QIO through two stages of inverter circuits whose operating voltage is c. In the figure, the signal EXTE is set to a high level when the EEFROM is in the normal erase mode, that is, when the erase operation is performed only for a period set by an external signal, in addition to the internal automatic erase mode in this embodiment. This is an external erase mode signal.

The configuration and operation of the erase circuit ERC are as follows. The NAND gate circuit receiving the erase pulse 101 operates substantially as an inverter circuit when the external erase mode signal EXTE is at a low level. Therefore, the signal BP
is a cut MOSFET whose gate is constantly supplied with a power supply voltage Vcc via three inverter circuits, and a cant MOS whose gate is constantly supplied with a high voltage Vpp.
Through the FET, high voltage Vl)! ) as the operating voltage
P-channel MOSF that constitutes a MOS inverter circuit
It is supplied to the gates of F and T. The output signal of the final stage inverter circuit is supplied to the gate of the N-channel MOSFET constituting the CMOS inverter circuit. Instead of this configuration, the gate of the N-channel MOSFET may be connected to the gate of the P-channel MOSFET. A feedback P-channel MOSFET that receives a level-converted output signal is provided between the gate of the P-channel MOSFET and the high voltage vpp. In this embodiment circuit, when the erase pulse EP is set to low level, the output of the final stage inverter circuit becomes high level, so the N-channel MOSFET is turned on and the output signal is set to low level. As a result, the P-channel MOSFET for feedback is turned on, and the P-channel MOSFET forming the CMOS inverter circuit is turned on.
In order to set the gate voltage of the OSFET to a high voltage, this P-channel MOSFET is turned off. Also, since the cut MOSFET is turned off, the high voltage Vl)p
This prevents direct current from flowing from the inverter circuit to the final stage inverter circuit which operates at low voltage Vcc. This results in
Since the output signal is set to low level, MOSFETQ17
turns on and sets the potential of the source region of the memory cell to a high voltage Vl1!1. At this time, MOSFETQIO
Since the gate voltage of becomes low level, it becomes an off state. When the erase pulse EP is set to high level, the output of the final stage inverter circuit is set to low level, so the N-channel MOSFET is turned off, and the P-channel MOSFET is turned off.
OSFET turns on. As a result, the output signal becomes a high level such as a high voltage vpp, turning off the P-channel MOSFET QI7. At this time, the feedback P-channel MOSFET is turned off due to the high level of the output signal. At this time, the gate voltage of N-channel MOSFET QIO becomes high level. As a result, MOSFET QIO is turned on, and the source potential of the memory cell is set to the ground potential of the circuit.

Returning to FIG. 4 again, in the figure, the oscillation circuit 02 and the binary counter circuit BCS3 output the erase pulse end signal PE after the time determined by the erase pulse EP is set to low level. changes from low level to high level, flip-flop circuit FF3
Reset. In response, the erase pulse EP changes to high level, so the erase circuit ERc switches the source potential of the memory cell from the high voltage Vfl1) to the circuit ground potential Vss.

After the delay time set by the delay circuit D7, the erase verify signal EV changes to high level and the erase verify mode is entered. At this time, the counter circuit BCSI
and BCS2 are electrically isolated from each other by the automatic erase mode setting signal AE, unlike during pre-write, counter circuit BCS1 is used to generate a reference pulse for verify, and counter circuit BCS2 is used for pre-write. Rather, it is used to generate internal address signals for verification. That is, the counter circuit B
The output signal OS2 of CS1 is a high level signal in the first half of the cycle and a low level signal in the second half of the cycle, and the output signals SO to S7 from the sense amplifier SA during the low level period.
(In the case of 8-bit output) High level/Low level determination is performed, and when all bit signals SO to S7 output from the sense amplifier SA are at low level, in other words, the signal selected by the counter circuit BSC2 is If the threshold voltage of each of the eight storage transistors is in an erased state lowered, the flip-flop circuit FF
3 is not set, counter circuit BSC2 generates internal address signals AXI and AYI pointing to the next address in response to address increment signal EAI during verify, and determination is made again during the period when signal OS2 is at a low level. In this way, according to the address increment signal EAI during verification, the internal address signal A
XI, AYI are formed, and its internal address signal AXI
．． Memory cell determination is performed according to AYI. if,
If one or more bits of the output signal So-37 of the sense amplifier SA are at a high level, that is, if there is a memory cell that has not erased even one bit, the flip-flop circuit 3 is sent by the NOR gate circuit NOR2, and the signal is reset again. A low level erase pulse BP is generated.

The above-described erase operation is performed again by this low-level erase pulse EP, and then the above-described erase verify is performed again. In FIG. 5, the internal signal O
An example is shown in which it is determined that the data has been erased at four addresses indicated by S2, and it is determined that the data has not been erased at the fifth address, and the verify period ends. At this time, due to the action of the delay circuit D8, the last pulse of the signal OS2 is prevented from appearing in the address increment signal EAI, indicating that the last address determined not to be erased remains. In other words,
The counter circuit BSC2 holds an address signal indicating an address determined not to be erased. Therefore, although not particularly limited, after automatic erasure is performed again, erase verification is performed from the address that was determined not to have been erased previously. Here, the basic pulse of the Verify mode is used as the output signal OS2 of the frequency dividing circuit, but it goes without saying that the present invention is not limited to this.

When the memory cells corresponding to all the addresses are verified by repeating the above operation, the end address signal END becomes high level and the flip-flop circuit FF2 is reset in the same way as at the end of the pre-write. In response to the reset of flip-flop circuit FF2, automatic erase mode setting signal AE changes to low level, and erase mode end signal ER is set to high level only during the delay time set by delay circuit D9.

Due to the high level of this signal ER, the flip-flop circuit FFI is re-centered, and after the delay time set by the delay circuit D1 has elapsed, the signal ES indicating the erase mode is changed to a high level, so that it does not accept external signals. The current state will be released.

The binary counter circuit BCS4 counts the number of times the erase pulse EP is generated. If the erase mode does not end as described above even after counting a certain number of pulses EP, the abnormality detection signal FAIL is set to a high level to forcibly end the erase mode. That is, the erase mode end signal ER is generated. In addition, the logic circuit that forms this erase mode end signal ER shows a gate circuit to which the internal signal PSTOP and end address signal END are input, but this gate circuit is used when you do not want to erase by prewriting only. This is because this mode can be ended by the internal signal PSTOP generated by the signal.

In the above explanation, we will focus on the timing diagram in Figure 5.
Although the specific circuits of the erase control circuit LOGC shown in FIGS.
Address buffer, decoder, MOSF via NTR
Controls ET etc. The signal DB shown in FIGS. 6 and 7,
S.B. In signal generating circuits such as sc, re, wr, PG, Do, etc., external terminals CE, OE, WE. EE input is disabled and controlled internally. For example, when the erase pulse EP is at a low level, that is, during the period when electrical erasing is performed, the signal DC in FIGS. 3 and 4 is at a high level, the signal DE is at a low level, and each decoder XDCR, YDC
R is inactivated. Therefore, all word lines and all data lines become unselected. The states of other periods are similarly determined by the output signals of the erase control circuit LOGC shown in FIGS. 3 and 4.

The data polling mode is a mode for determining whether or not data is being erased. Therefore, it can also be regarded as a mode for knowing the internal state of EEPR0M, that is, a status polling mode. Chip enable signal C
B is set to low level, and the output enable signal o
This mode is entered in a state where E is set to low level, write enable signal WE is set to high level, erase enable signal EE is set to low level, and high voltage Vpl) is supplied to external terminal vpp. When this mode is set, the data polling control signal POLM becomes low level in the circuits shown in FIGS. 6 and 7. At this time, data output buffer activation signal D07 is set to high level, but data output buffer activation signal DO is set to low level by data volley ring control signal POLM.

A concrete circuit of the data output buffer DOB is shown in FIG. Excluding the data polling (status polling) control circuit DP, external input/output terminals I/00~■
Data output bath sofa DOB-0 to DO compatible with /06
There is no difference in the configurations of the B-6 and the data output bus sofa DOB-7, which corresponds to the external input/output terminal ■/07, in that they are both 3-state output circuits including a high impedance state.
As explained earlier in the read mode, the activation signal Do
, DO7 go high, the output signal So-37 from the sense amplifier SA is inverted and outputted. On the other hand, in the data polling mode (status polling mode), the activation signal POLM is at a low level, so the output signal S7 is invalidated, and the output signal S7 is disabled according to the level of the signal ES indicating the erase mode at that time.
The output signal of 07 is determined. That is, during the erase mode period, since the signal ES indicating the erase mode is at a low level, a low level signal is output from the external input/output terminal I/07, and if the erase operation is completed, a high level signal is output. Ru.

Figure 12 shows the sense amplifier SA and address decoder
A power supply circuit that generates an operating voltage Vcv in erase verify mode to be supplied to DCR and YDCR is shown. This circuit is constructed using a known reference voltage generation circuit VREF that utilizes a silicon bandgap and operational amplifier circuits OPI and OP2. That is, the reference voltage VR formed by the reference voltage circuit VREF is applied to the gain (
The voltage is amplified according to R1+R2)/R2, and the voltage is about 3.5V.
form a voltage like . This voltage is outputted through an operational amplifier circuit OP2 in the form of a voltage follower to obtain the voltage Vcv.

The operational amplifier circuits OP1 and OP2 are activated by the automatic erase mode setting signal AE to generate the voltage Vcv. This makes it possible to prevent the power supply circuit from consuming current in other operation modes. Note that the operational amplifier circuit OP2 has a P-channel MOSFET and an N-channel MOSFET as its output circuit.
When using an output circuit consisting of SFET, the above signal AE
When deactivating the operational amplifier circuit, the signal AE turns on the P-channel MOSFET and outputs the low power supply voltage Vcc.

By adopting this configuration, the signal A is supplied to the above power supply circuit.
E can add a function of switching between voltages Vcc and Vcv. Note that the reference voltage generation circuit VRE mentioned above
As F', for example, those disclosed in British Patent No. 2081458B can be used.

The operating voltage during the erase verify mentioned above is the flash EE
In order to make it approximately equal to the lower limit power supply voltage Vcca+in at which read operation is possible for the FROM, it is desirable to set it lower than the power supply voltage Vcc in the flash EEFROM in the read mode. Also,
Here, as shown in FIG. 12, it is assumed that the power supply is built in, but the signal AE is outputted to the outside of the flash EEPROM, and the programmable power supply provided externally is controlled by this signal AE. The voltage may be supplied to a circuit to which the voltage Vcv is applied, such as the sense amplifier SA of the present flash EEPROM and the address decoders XDCR and YDCR. here,
The above-mentioned lower limit voltage Vccmin is the lowest power supply voltage Vcc (external terminal Vcc of the EEFROM) that makes it possible to read stored information from the memory cell with the highest threshold voltage among the memory cells constituting the EEFROM.
).

FIG. 23 shows a circuit diagram of unit circuits forming address decoders XDCR and YDCR. Each address decoder is constituted by a plurality of unit circuits having similar configurations.

However, the combination of internal address signals supplied is
Different for each unit circuit. FIG. 23 shows one of these unit circuits as an example.

In the figure, UDG is a unit decoder circuit, and is constituted by, for example, a NAND circuit that receives an internal address signal ax (a3') and an address decoder activation signal DB. The output signal of this NAND circuit is supplied to a level conversion circuit having a configuration similar to that shown in FIG. Second
In the level conversion circuit shown in FIG. 3, the high voltage Vpp is supplied from the timing control circuit CNTR to the node corresponding to the node to which the high voltage Vpp was supplied in FIG.
, the power supply voltage Vcc and the low voltage Vcν are selectively supplied. On the other hand, the NAND circuit UDG is constantly supplied with the power supply voltage Vcc.

As a result, during write operation or pre-write,
Word line W designated by internal address signal ax (ay) from address bus sofa XADB (YADB)
The unit circuit outputs a selection signal having a voltage substantially equal to the high voltage vpp to (the selection line CL of the column switch MOSFE1). Furthermore, during a read operation, a selection signal having a voltage substantially equal to the power supply voltage Vcc is output to the word line W (selection line CL) designated by the internal address signal ax (a3'). Address buffer XADB (YADB) in erase verify mode
The low voltage Vc
A selection signal having a voltage substantially equal to v is output.

In addition, during the erase operation, the activation signal DE is set to low level as described above, so that a voltage substantially equal to the circuit ground potential Vss is applied from all unit circuits to the word line W.
(selection line CL). In addition, words that are not selected! A voltage according to the circuit ground potential Vss is supplied to W (selection line CL). Furthermore, as described above, at the time of pre-writing and erase verifying, the internal address signal AXI (AYI) formed by the counter circuit is taken into the address buffer XADB (YADB) instead of the external address signal AX (AY). An internal address signal ax (ay) corresponding to this is formed.

FIG. 22 shows a circuit diagram showing one embodiment of the data buffer DIB.

This data input cover sofa DIB has an external input/output terminal I/
It is commonly used when writing data from O to a memory cell and when writing predetermined data to a memory cell during pre-writing.

In the case of write mode, the above Table-1. As can be understood from Table 2, the write mode signal wp is set to high level, and the pre-write pulse PP is set to low level. Therefore, data supplied to the external input/output terminal I/O is transmitted to the input node of the inverter via two NOR circuits. The data transmitted to the input node is inverted in phase by an inverter, and then transferred to one P
Channel MOSFET, 2 N-channel MOSFs
It is supplied to a bias circuit consisting of an ET. The above data converted into a predetermined level by this bias circuit is
It is supplied to the gate of P-channel MOSFET QPI for writing. This P-channel MOSF for writing
ETQPT is a MOSFETQL whose gate is supplied with a predetermined bias voltage, and the MOSFETQI mentioned above.
8 to the common data line CD, and further connected to the drain of the memory cell (storage transistor) to be written via a selected data line. The P-channel MOS'FET QPI supplies the drain of the memory cell with a voltage according to the data to be written.

As a result, data is written into the memory cell. However, if the threshold voltage of the storage transistor of the memory cell becomes negative, the MOSFF, TQ
The current Iw flowing through L, etc. increases, and the MOSFETQ
The voltage drop at L, etc. becomes large, and as described above, sufficient writing cannot be performed. On the other hand, according to this embodiment, since the threshold voltage can be prevented from becoming negative, the current Iw can be prevented from increasing, and data can be written reliably.

Note that during the pre-write operation, the signal wp is at a low level, so data from the external input/output terminal I/O is not taken in. Instead, pre-write pulse PP
Writing is performed using this as write data.

FIG. 21 shows a timing chart focusing on the external input signal and external output signal in the automatic erase mode described above. When the erase enable signal EE changes from high level to low level at time t1, a latch provided inside the flash EEPROM is activated and the flash EEPROM enters an automatic erase mode. Thereafter, the flash EEPROM is
It does not accept external signals other than a combination of external signals indicating a data polling request. After keeping the erase enable signal EE at low level for a certain period of time determined internally, CE, OE. Any combination of external control signals for WE and EE may be used. In the automatic erase mode of this embodiment, this erase enable signal EE
Erasing is not performed during the O low level period.

Therefore, the above-mentioned fixed time is required to set the latch circuit shown in FIG. 3 to a predetermined state, and is sufficiently shorter than the time required to erase the memory cell. Further, although external address signals are not shown in this figure, any combination may be used since they are not taken internally.

The figure shows an example in which the data polling mode is entered at time t2. At time t3 determined by internal signal delay, a data polling signal appears at external input/output terminal ■/07. Between time t3 and time t4, the output is at a low level because erasing has not yet been completed.

When erasing ends at time t4, it changes to high level, and the end of erasing can be detected from outside the flash EEFROM. In addition, when in automatic erase mode, external input/output terminal r/0
0 to ■/06 are in a floating state. External input/output terminal (2)/07 is also in a floating state in automatic erase mode, except in polling mode.

FIG. 24 shows that when erasing information stored in a memory cell,
A waveform diagram of an externally supplied erase enable signal EE is shown. FIG. 24(A) shows a waveform diagram of the erase enable signal EE in the automatic erase mode described above.

Further, FIG. 24(B) shows the waveform of the erase enable signal line 100 when an erase operation and a verify operation are instructed from outside, and FIG. The waveform is shown when an instruction is given by the enable signal n. These waveforms all show the case of batch erasing. In FIG. 24(B), the period EO (for example, 1
When the memory cell (for example, 1 byte) is actually erased, and during the period vO when the signal EE is at a high level, the verify operation that involves the read operation from the memory cell (1 byte) is actually performed. It will be done. Further, in FIG. 24(C), during a period EO° (for example, 1 second) during which the signal EE is at a low level, an erasing operation is actually performed on all memory cells on the chip. On the other hand, in the automatic erase mode described above, it is sufficient that the signal EE is kept at a low level for a time long enough to set the launch circuit shown in FIG. 3 to a predetermined state. Therefore, the above erase enable signal E
The time to keep E at low level is shown in Figure 24 (B).
, may be shorter than that shown in (C), for example, about 50 ns.

This is because, in the automatic erase mode, the actual erase operation on the memory cell is not performed during the period when the erase enable signal EE is at a low level.

Although this embodiment mainly describes the internal configuration for the automatic erase mode, it is also possible to execute the erase mode shown in FIGS. 24(B) and (C) as well. good.

Further, FIGS. 24(D) and 24(E) show the external address signals AX, AY and the output signal of the external input/output terminal I/O during a read cycle. To enter the read mode, it is necessary to set each external signal as shown in Tables 1 and 2 above, but this figure shows the external address signal and output signal as described above. has been done. For example, the desired ad tz from the standby mode
By applying external address signals AX and AY that designate the address Ai to the EEPROM, the data Di held at the address Ai is output from the external input/output terminal I/O. Thereafter, the EEFROM is again put into standby mode, for example. In this read cycle, memory cell selection operations, sense amplifier activation, etc. are performed, so the cycle time is e.g.
About 200 ns is required. On the other hand, in the erase mode shown in FIG. 24(A), the pulse width of the erase enable signal EE may be as short as about 5on3 as described above. Therefore, as will be described later using FIGS. 14 and 15, it is possible to prevent a device (such as a CPU) that controls the EEPROM from being occupied for a long time with the erase operation of the EEPROM. The pulse width of this erase enable signal EE (FIG. 24(A)) is shorter than the time required to actually erase the memory cells.
That's fine.

As mentioned above, this erase enable signal E
The actual erase operation is not performed by E.
This is because an erase operation instruction is given to the EPROM.

In this embodiment, the present invention is not limited to a configuration in which erase verification is performed for all addresses. It may be changed depending on the degree of control of the threshold voltage after erasing that is required. For example, only one data line may be verified, or in extreme cases, only one representative bit (memory cell) may be verified. If the verification power supply voltage Vcv can be set sufficiently lower than the required readable lower limit voltage V ccm i n , a sufficient readable lower limit power supply voltage Vccmin can usually be secured even with this method. Note that in FIG. 5, PSTOP is a signal for testing.

FIG. 13 shows a circuit diagram of another embodiment of an EEFROM to which the present invention is applied. In this embodiment as well, only one memory array and its corresponding peripheral circuit are shown, similar to the embodiment shown in FIG. For the entire arrangement, please refer to FIG. 20 above.

In the EEPROM memory cell of this embodiment, electrical erasing is performed on the drain region side instead of on the source region side as in the previous embodiment.

That is, in this embodiment, the source line CS of the memory array M-ARY is fixedly connected to the ground potential point Vss of the circuit.

An erasure circuit ERC, and the P-channel MOSFET QI 7 and N-channel MOSFET QI7 whose switches are controlled by the erase circuit ERC.
The output node of SFETQIO is connected to the common data line CD via a P-channel type switch MOSFETQ25. The above-mentioned erase pulse EP is applied to the gate of the switch MOSFET Q25. As a result, the switch MOSFET Q25 receives the erase pulse E
P is turned on only during the period when P is set to low level, and P is turned on based on the low level of erase pulse BP.
The high voltage VpP output through the channel MOSFET QI 7 is transmitted to the common data line CD.

Further, the address decoder YDCR is connected to the memory array M-
In order to erase all memory cells in ARY at once, all column switches MOSFETQ7 to Q9 are activated in response to the erase pulse EP, for example, to transmit the high voltage vpp of the common data line CD to the data line. Turn on. Instead of this configuration, if the column decoder YDCR is configured to generate a selection signal according to an internal or external address, erasing can be performed in units of data lines. Therefore, in the EEPROM of this embodiment, the control of the address decoder YDCR during the erase operation is different from that of the embodiment shown in FIG. The other parts are the same as those in FIG. 1, so please refer to FIG.

FIG. 14 shows a flash (FLASH) according to the present invention.
) A block diagram of an embodiment of a microcomputer system using EEFROM is shown.

The microcomputer system of this embodiment is centered around a microprocessor CPU, a ROM (read only memory) in which programs are stored, and a RAM (random access memory) used as a main memory device.
memory), input/output port I/OPORT, the batch erasing type EEPROM according to the present invention, and the control circuit CONTRO.
A liquid crystal display device or CRT (cathode ray tube) as a monitor connected via the LLER is connected to the address bus ADDRE.
They are interconnected by an SS1 data path DATA and a control bus, which is exemplarily shown and conveys a control signal CONTROL.

In this embodiment, the 12V power supply RGU necessary for the operation of the display device i&LCD and CRT is also used as the high voltage Vpl of the EEPROM. Therefore, in this embodiment, the power supply RGU is activated by the control signal from the microprocessor CPU at the terminal Vl)I) during the read operation.
A function is added to switch the voltage to 5V like Vcc.

In addition, FIG. 15 shows the microprocessor CPU and EB.
The connection relationship of each signal focusing on PROM is shown.

To the chip enable terminal CB of the EEFROM, an address signal indicating an address space allocated to the EEPROM among the system addresses is supplied to the decoder circuit DEC to generate a chip enable signal CE. Furthermore, the timing control circuit TC receives and outputs an R/W (read/write) signal, a DS (data strobe) signal, and a WAIT (wait) signal from the microprocessor CPU. EEFROM external input/output terminal I/0 via path
0 to ■/07, and the address terminals of the microprocessor CPU are connected to EE through the address bus except for a part.
It is coupled to external address terminals AX and AY of FROM.

In the microcomputer system of this embodiment, EE
Since FROM has the above-mentioned automatic erase function, the microprocessor CPU addresses the EEPROM and generates the signal σ, and also uses the combination of the signals R/W, DS, and WAIT to write the 21st
Signals OE and WE specifying the erase mode as shown in the figure
and generate a signal EE. After this, the EEFROM enters an automatic erase mode internally as described above.

When the EBFROM enters the erase mode, the address terminals, data terminals, and all control terminals become free as described above, and the microprocessor CPU
are electrically isolated. Therefore, the microprocessor CPU only instructs the EEPROM to erase mode, and then performs data processing that involves exchanging information with other memory devices ROM, RAM, or input/output ports using the system bus. can be executed.

This makes it possible to erase the batch erase type EEPROM while it is installed in the system in the same way as a full-function (byte-by-byte rewritable) EBFROM without sacrificing system throughput.

After instructing the erase mode as described above, the microprocessor CPU erases the EEPROM at appropriate time intervals.
The data polling mode is specified for the data path, and it is determined whether the level of terminal I/07 of the data path is low level or high level, and it is determined whether or not the erase operation is completed, and the erase operation is completed and written to the EEPROM. If there is data to be written, it instructs writing.

The effects obtained from the above examples are as follows. That is, [1] an EEF including a memory array in which electrically erasable non-volatile memory elements are arranged in a matrix manner;
After performing an erase operation on the ROM according to an erase instruction from the outside, the corresponding memory cell is read at least once, and the erase operation is continued based on the read information. By incorporating an erase control circuit that controls the stop, the EEPROM itself has an erase confirmation function, that is, the above-mentioned automatic erase function that involves reading, so it can be used without placing a burden on the microprocessor and can be left in the system. This has the effect that erasing operation becomes possible.

(2) By adding a pre-write function to the erase control circuit that writes to all memory cells prior to the erase operation, unwritten memory cells can be pushed to the negative threshold by executing the erase operation. The effect is that it can be prevented from being caused to have a value voltage.

(3) The above memory cell is a MOS having a two-layer gate structure of a floating gate and a control gate.
The area occupied by the memory cell can be reduced by assuming that the memory cell is an FET and electrically erased by extracting the information charge accumulated in the floating gate to the source, drain, or well using a tunneling phenomenon. The effect is that it becomes smaller and a larger storage capacity becomes possible.

(4) The memory cells constituting the above memory array have a common source and drain for the entire memory array or a group of memory cells in a part thereof, and an electrical erase operation is performed for each common memory cell at once. As a result, it is possible to achieve the effect of reducing the size of the memory cell as described above.

(5) By providing an address generation circuit for sequentially selecting memory cells as the erase control circuit, it is possible to carry out the pre-write and erase verification for all memory cells. It will be done.

(6) At the time of verifying the memory cell to control the continuation and stop of the above-mentioned erasure, the selection potential of the word line transmitted to the control gate is set to approximately 3.5 cm, which corresponds to the readable lower limit voltage Vccmtn, which is lower than the low voltage Vcc. By setting the voltage to a low voltage Vcv such as Vcv, it is possible to ensure necessary and sufficient erasing.

(7) Set the selection potential of the word line to a relatively low voltage Vcv.
a first operational amplifier circuit that receives a reference voltage generated by a reference voltage generation circuit and converts it into a desired output voltage based on a gain setting resistor element; By receiving the output signal from the output terminal of the second operational amplifier circuit in the form of a voltage follower that forms the output voltage, any desired voltage can be set with high precision without being affected by variations in the device process. You can obtain the effect that can be obtained with .

(8) By providing the above EEPROM with a data polling function that outputs the internal status such as continuation or stop of the erase operation to the outside according to instructions from the outside, the effect of simplifying memory management by the microprocessor sensor can be obtained. It will be done.

(9) The EEFROM is mounted on a microcomputer, and an internal erase control circuit automatically performs the erase operation in accordance with erase instructions from the microprocessor while being electrically disconnected from the microprocessor. This provides the advantage that EEPROM erasure can be performed on-board without sacrificing the throughput of the microcomputer system.

Q[Il has a memory array in which electrically erasable nonvolatile memory elements are arranged in a matrix and are selected by one gate signal line (word line) and one drain signal line (data line). , the erase operation is started in accordance with an external erase instruction, and after that, the erase is performed automatically regardless of the external address signal, input data, or control signal, and after the erase is completed, the external address signal is A semiconductor nonvolatile memory device that can perform desired operations based on input data and control signals can be obtained.

αυIt has a memory array consisting of a matrix arrangement of electrically erasable non-volatile memory elements selected by one gate signal line (word line) and one drain signal line (data line). The erasing operation starts according to the erasing instruction. After that, erasing is performed automatically regardless of external address signals, input data, and control signals. After the erasing is completed, external address signals and input It includes a semiconductor nonvolatile memory device that can perform desired operations based on data and control signals, a microprocessor that has a predetermined information processing function, and a system bus that connects the semiconductor nonvolatile memory device and the microprocessor. An information processing system is obtained in which the nonvolatile storage device automatically performs erasing operation by an internal erasure control circuit in a state where it is electrically disconnected from the microprocessor in accordance with an erasure instruction from the microprocessor.

An electrically writable and erasable non-volatile memory arranged in a matrix of sub-rows and columns, in which erasure is initiated by inputting a single pulse of less than the read cycle period. After that, erasing is performed automatically regardless of the input of address, data, and control signals from the outside, and after the erasing is completed, a semiconductor nonvolatile memory device that accepts addresses, data, and control signals from the outside is obtained.

(self) In an information processing system including an electrically writable and erasable non-volatile memory arranged in a matrix of rows and columns, and connected to a microprocessor by a system bus, in the erasing process, a readout process is performed. Erasing is started by inputting a single pulse of less than the cycle period, and after that, erasing is performed automatically regardless of the address, data, and control signals from the system bus. An information processing system including a semiconductor nonvolatile memory device that accepts data is obtained.

Among the memory cells, the memory cell with the lowest threshold voltage is prevented from having a negative threshold voltage due to the erase operation, and the memory cell with the highest threshold voltage is The erase operation lowers the lower limit voltage Vccm.
An effect is obtained in that the erase operation of the EEPROM is automatically controlled by the internal erase control circuit so that the EEPROM has a threshold voltage that can be read in the in.

Although the invention made by the present inventor has been specifically explained above based on Examples, it goes without saying that this invention is not limited to the above Examples and can be modified in various ways without departing from the gist thereof. Nor. For example, the signals FAIL and ER shown in FIG. 4 may have a function of being output to the outside. In this case, in order to prevent an increase in the number of external terminals, it is desirable to output using the data polling function. For example, data input/output terminal ■/05 and I/06,
As a circuit similar to the data output circuit corresponding to the data input/output terminal I/07 in FIG. 11, the signals FAIL and ER may be made to correspond to the gates to which the signal ES is supplied. In this way, signals indicating other internal operation sequences may also be output to the outside as necessary. Furthermore, erasing of the memory array MARY may be performed by dividing the source line and word line, respectively, and specifying the memory block to be erased by the combination thereof. In addition to stacked gate structure MOS transistors used in EPROMs, storage transistors constituting memory cells include
The write operation may also use a FLOTOX type storage transistor that uses a tunneling phenomenon. In the above embodiment, one memory transistor shown in FIG. 16 was used as one memory cell, but one memory transistor shown in FIG. (the transistor is regarded as one memory transistor) may be used as one memory cell. That is,
The present invention is particularly suitable for an EEPROM in which one memory transistor shown in FIG. 19 (A) is used as one memory cell. It can also be applied to an EEFROM which has a 2 transistors and is defined by 2 word lines and 1 data line.The high voltage vpp for writing/erasing is a high voltage supplied from the outside. In other words, if the current flowing during writing/erasing is small, a voltage boosted from the power supply voltage Vcc inside the EEFROM by a known charge bomb circuit or the like may be used.Also, This internal boosted power supply and external high voltage vpp may be used together.

In BBFROM, the configuration of the circuit part (CNTR) that controls normal writing/reading, etc. and the circuit part (LOGC) that controls the erase algorithm can be any type of circuit as long as it performs the operation sequence described above. It doesn't matter if it is. That is, in addition to those using random logic circuits as shown in FIGS. 3 and 4, FIGS. 6 and 7,
Although a programmable logic array (PLA), a microcomputer and software are incorporated, or an asynchronous circuit is used in the above embodiment, a synchronous circuit may be used. In this way, the circuit that realizes the above operation sequence can take various embodiments.

The specific circuit configuration of the memory array and its peripheral circuits constituting the EEFROM can take various embodiments. Furthermore, the EEPROM or the like may be built into a digital semiconductor integrated circuit device such as a microcomputer.

The present invention can be widely used in semiconductor nonvolatile memory devices that use stacked gate structure memory transistors such as those used in EFROMs and FLOTOX type memory transistors, and information processing systems that use the same.

In the above explanation, in order to simplify the explanation, the pair of regions of the storage transistor were defined as the source region and the drain region, but in the storage transistor, the source and drain are determined by the value of the applied voltage. The present invention can be applied by reading the above-mentioned source region and drain region as one region (node) and the other region (node).

〔Effect of the invention〕

A brief explanation of the effects obtained by typical inventions disclosed in this application is as follows. That is, in an EEPROM equipped with a memory array in which electrically erasable non-volatile memory elements are arranged in a matrix, the corresponding memory cells are erased at least once after an erase operation is performed according to an erase instruction from the outside. A built-in erase control circuit performs a read operation and controls whether to continue or stop the erase operation based on the read information. In addition, EE with built-in erase function as mentioned above
When a PROM is installed in an information processing system including a microprocessor, erasing operation is automatically performed by an internal erasing control circuit in a state separated from the microprocessor according to instructions from the microprocessor.

In this configuration, since the EEPROM itself has an automatic erase function that involves reading the erase confirmation, in the erase operation while the EEPROM is still installed in the system, the control from the microprocessor only requires a slight instruction to start erasing. time, significantly reducing the burden on the microprocessor without sacrificing system throughput.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram of a memory array section and a block diagram of peripheral circuits showing one embodiment of an EEPROM to which the present invention is applied. FIG. 2 is a flow chart diagram showing an example of an erasing algorithm according to the present invention. 4 and 4 are circuit diagrams of a specific embodiment of the erase control circuit LOGC, FIG. 5 is a timing diagram for explaining the erase operation, and FIGS. 6 and 7 are diagrams of the timing control circuit CNTR. A circuit diagram of a specific embodiment; FIG. 8 is a characteristic diagram showing the relationship between erase time and threshold voltage of a storage transistor; FIG. 9 is a circuit diagram of an address buffer XADB. A circuit diagram showing an example of a YADB unit circuit, FIG. 10, is an erase circuit E.
FIG. 11 is a circuit diagram showing an embodiment of the RC; FIG. 11 is a circuit diagram showing an embodiment of the data output bath sofa DOB; FIG. 12 is a circuit diagram showing an embodiment of the power supply circuit that generates the erase verify voltage Vcv. Figure 13 shows the above E
FIG. 14 is a block diagram showing an example of a microcomputer system in which the above EEPROM is used; FIG. 15 is a circuit diagram showing the above EEPROM and a microprocessor C
FIG. 16 is a structural cross-sectional diagram for explaining an example of a conventional memory cell; FIG. 17 is a schematic circuit diagram for explaining its read operation; FIG. 18 is a structural cross-sectional view for explaining another example of a conventional memory cell, FIG. 19(A) is a circuit diagram of a memory cell in an EEPROM to which the present invention is applied, and FIG. ) is a circuit diagram of a conventional memory cell, No. 20
21 is a diagram showing an example of an external signal of EEPRQM to which the present invention is applied. FIG. 22 is an example of an embodiment of a data buffer. 23 is a circuit diagram showing an embodiment of the address decoder, and FIG. 24 (A), (B). (C) A waveform diagram showing the waveform of the erase enable signal. FIGS. 24(D) and (E) are waveform diagrams showing the read cycle. XADB, YADB...address bar sofa, XDCR,
YDCR...Address decoder, UDG...Unit decoder circuit, M-ARY...Memory array, SA...Sense amplifier, DIR, DIB-0 to DIB-7...Data input cover sofa, DOB, DOB-0 to DOB- 7...Data output bath sofa, CNTR...timing control circuit, E
RC: Erase circuit, LOGC: Erase control circuit (internal circuit), Nl. N2...CMOS inverter circuit, CS...
・Source line, Wl, W2...Word line, D1~Dn...
Data line, CD...Common data line, 01,02...Oscillation circuit, BCSI~BCS4...Binary counter circuit, DP
・・Data polling control circuit, CPU・・Microprocessor, ROM・・Read only memory, RA
M... Random access memory, I/OPORT...
・I/O port, EEPROM (FLASH) ・
・Bulk erase type semiconductor non-volatile storage device, RGU...12
V-system power supply, LCD...liquid crystal display, CRT...cathode ray tube, ADDRF, SS...address bus, DATA
...Data path, DEC...Decoder circuit, TC...Timing control circuit, 3...Drain, 4...Floating gate, 5...
Source, 6. Control gate, 7. Thin oxide film, 8. P-type silicon substrate, 9. N-type diffusion layer, 10.
・Low concentration N-type diffusion layer, 11...P-type diffusion layer, 12...
Selected memory cell, 14...Unselected memory cell, 13...
Selected word line, 15..Unselected word line, 16..data line, 1.Sense amplifier.

Claims (1)

[Scope of Claims] 1. One memory cell is constituted by each intersection of one word line and one data line, and the memory cell is an electrically erasable nonvolatile memory device, The erase operation is started according to the erase instruction from the external address signal, input data, and control signals from the outside. A semiconductor non-volatile memory device characterized by being capable of performing desired operations based on input data and control signals. 2. During the erasing, a determination signal as to whether erasing is in progress or has been completed is sent to the outside by an external control signal without interrupting or terminating the erasing mode. semiconductor non-volatile memory device. 3. An electrically writable and erasable non-volatile memory arranged in a matrix of rows and columns;
In the erasing process, erasing is started by inputting a single pulse that is shorter than the read cycle time, and thereafter, the erasing is performed automatically regardless of the input of external address, data, and control signals, and after the erasing is completed, address from outside,
A semiconductor nonvolatile memory device characterized by receiving data and control signals. 4. In an information processing system including an electrically writable and erasable non-volatile memory arranged in a matrix of rows and columns and connected to a microprocessor by a system bus, the erasing process requires less than a read cycle. Initiate the erase by inputting a single pulse, after which the address, data,
An information processing system including a semiconductor nonvolatile memory device, characterized in that it automatically performs erasing regardless of a control signal and receives a signal from a system bus after the erasing is completed. 5. A memory array in which electrically erasable non-volatile memory elements are arranged in a matrix, and after performing an erase operation according to an external erase operation instruction, perform at least one read operation on the corresponding memory cells. 1. A semiconductor nonvolatile memory device, comprising: an erase control circuit that performs continuous erase operation and controls continuation or stop of erase operation based on the read information. 6. The semiconductor non-volatile device according to claim 5, wherein the erase control circuit has a pre-write function of writing to all memory cells prior to the erase operation. Storage device. 7. The above memory cell is a MOSFET with a two-layer gate structure consisting of a floating gate and a control gate, and the information charge accumulated in the floating gate is extracted to the source, drain, or well using a tunneling phenomenon, thereby generating electrical power. 7. The semiconductor nonvolatile memory device according to claim 5, wherein the semiconductor nonvolatile memory device is erased. 8. The memory cells constituting the above-mentioned memory array have a common source and drain for the entire memory array or a group of memory cells in a part thereof, and an electrical erase operation is performed for each common memory cell at once. A semiconductor nonvolatile memory device according to claim 5, 6, or 7, characterized in that the semiconductor nonvolatile memory device is a semiconductor nonvolatile memory device. 9. The semiconductor nonvolatile memory device according to claim 5, 6, 7, or 8, wherein the erase control circuit includes an address generation circuit for selecting a memory cell. 10. A patent characterized in that the read operation of the memory cell for controlling the continuation and stop of erasing is performed by setting the selection potential of the word line transmitted to the control gate to a relatively low potential. Claims 5th and 6th
, the semiconductor nonvolatile memory device according to claim 7, 8, or 9. 11. The operating voltage for setting the selection potential of the word line to a relatively low potential receives a reference voltage generated by a reference voltage generation circuit, and converts it into a desired output voltage based on a gain setting resistor element. The voltage is obtained from the output terminals of a first operational amplifier circuit and a second operational amplifier circuit in the form of a voltage follower that receives the output signal of the first operational amplifier circuit and forms an output voltage. A semiconductor nonvolatile memory device according to claim 10. 12. A memory array in which electrically erasable non-volatile memory elements are arranged in a matrix, and after performing an erase operation according to an external erase operation instruction, perform at least one read operation on the corresponding memory cells. an erase control circuit that controls the continuation or stop of the erase operation based on the read information; and an output circuit that has the function of outputting the internal state of the erase operation, such as continuation or stop of the erase operation, to the outside according to instructions from the outside. A semiconductor nonvolatile memory device comprising: 13. A memory array in which electrically erasable non-volatile memory elements are arranged in a matrix, and after performing an erase operation according to an external erase operation instruction, perform at least one read operation on the corresponding memory cells. A semiconductor non-volatile device comprising an erase control circuit that controls the continuation or stop of the erase operation based on the read information, and an output circuit that has the function of outputting the internal state of the erase operation such as continuation or stop of the erase operation to the outside. The semiconductor nonvolatile storage device includes a digital storage device, a microprocessor having a predetermined information processing function, and a system bus that connects the semiconductor nonvolatile storage device and the microprocessor. An information processing system characterized in that an erase operation is automatically performed by an internal erase control circuit in a state separated from a microprocessor. 14. Claims characterized in that the microprocessor instructs the semiconductor nonvolatile storage device to output an internal state using the output circuit to determine whether or not the erase operation is completed. The information processing system according to item 13. 15. It has a memory array in which electrically erasable nonvolatile memory elements are arranged in a matrix and are selected by one gate signal line (word line) and one drain signal line (data line), The erase operation is started according to the erase instruction from the outside, and after that, the erase is performed automatically without depending on the address signal, input data, or control signal from the outside. After the erase is completed, the address signal from the outside, A semiconductor non-volatile memory device characterized by being capable of performing desired operations based on input data and control signals. 16. During the erasing, a determination signal as to whether erasing is in progress or has been completed is sent to the outside by an external control signal without interrupting or terminating the erasing mode. semiconductor non-volatile memory device. 17. It has a memory array in which electrically erasable non-volatile memory elements selected by one gate signal line (word line) and one drain signal line (data line) are arranged in a matrix, The erase operation starts according to the erase instruction from the outside, and after that, the erase is performed automatically regardless of the address signal, input data, or control signal from the outside. After the erase is completed, the address signal from the outside is , a semiconductor non-volatile memory device that can perform desired operations based on input data and control signals, a microprocessor having a predetermined information processing function, and a system bus that connects the semiconductor non-volatile memory device and the microprocessor,
An information processing system characterized in that the semiconductor nonvolatile memory device automatically performs an erasure operation by an internal erasure control circuit in a state separated from the microprocessor in accordance with an erasure instruction from the microprocessor. 18. The semiconductor non-volatile memory device is characterized in that during the erasing, a determination signal as to whether or not erasing is being performed is sent to the outside by an external control signal without terminating the erasing mode. An information processing system according to claim 17. 19. The microprocessor externally sends to the semiconductor non-volatile storage device, during the erasing, a determination signal as to whether or not erasing is in progress using an external control signal without terminating the erasing mode. 18. The information processing system according to claim 17, wherein the information processing system uses a function to instruct output of an internal state to determine whether or not the erasing operation is completed.