JPH02288922A - Memory access control circuit - Google Patents

Abstract

PURPOSE:To resolve the access contention at the time of outputting a request signal at an arbitrary timing by a request source, which requests the access to a memory, by providing plural service control circuits, a data holding circuit, and a cycle control circuit. CONSTITUTION:When the CPU service from a request input terminal 1 having a high priority level is executed, an AND 21 of a service control circuit 11 is operated with AND between a continue input signal and the input signal from an input terminal 11A. This AND is sent to a priority control circuit 7 through a output terminal 11B, and execution of the CPU service from the request input terminal 1 is registered in a data holding circuit 14. This register data is sent to a service control circuit 12, and a holding signal is outputted from a wait output terminal 5 by AND of an AND 20. Service control circuits 11 to 13 are arranged correspondingly to respective request sources and continuation of the service of an arbitrary request source is reported by the data holding circuit 14, thereby continuing the service of the CPU which preferentially uses the memory.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to memory access control circuits, and more particularly to multiple memory access control circuits, and more particularly to improved priorities for prioritizing multiple memory access requests. The present invention relates to a memory access control circuit having a control circuit.

[Conventional technology]

The priority control circuit provided in the conventional memory access control circuit is as shown in the block diagram of FIG.
For example, input the access request signal when there is a memory access request from three CPUs, or Quest input terminal 1.
．． 2.3, a priority control circuit 7 that prioritizes the three access request signals such as first come, first served, and a go output terminal 4 that sends an access start signal to one of the three CPUs according to the priority order. ' and two other CPUs
and a wait output terminal 5.6 for sending an access hold signal to each of the terminals. Therefore, since there is only one go output terminal 4, the first priority CPU starts reading, for example, and after the read is finished, the access hold signal of the second priority CPU is released, and the second priority CPU is read from the go output terminal again. The method was to send an access start signal to U.

[Problem to be solved by the invention]

The priority control circuit provided in the conventional memory access control circuit described above only has one go output terminal and way 1~ output terminals, so while a request is being serviced, other requests are processed with information other than pending information. The disadvantage is that there is no priority information, and therefore it is not possible to generate refresh 1~ at an arbitrary timing. In addition, if the request continues to Rifnis 1, which has a higher priority, for example, after the task of the request currently being serviced has finished, even if you want to continue servicing with the 1st priority and j-, if the service is terminated. Rifnis 1~ has the disadvantage that it cannot receive service in the next cycle.

[Means to solve the problem]

In the memory access control circuit of the present invention, which prioritizes the access request signals output from a plurality of memory access request sources, the input of each memory access request source and the access request signal, and the input of the memory access continuation signal are provided. a plurality of service control circuits having terminals and logic circuits for outputting input and memory access suspension signals; and a priority control circuit for assigning priorities to signals to access refniss 1 of each of the plurality of service control circuits. , a data holding circuit that holds priority information determined by the priority control circuit, and a cycle control that detects the start and end of an access service during a memory access service and outputs an information holding timing signal to the data holding circuit. circuit, and during a period when any one of the service control circuits continues to access the memory, the priority information determined by the priority control circuit is temporarily suspended and the information is accessed from the memory from each of the other service control circuits. Outputs access pending signal.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram of an embodiment of the present invention, and FIG. 2 is a logic circuit diagram of service control circuits 11 to 13. The example of the embodiment shown in Figure 1 outputs to the question 1 using three CPUs.
Interface with service control circuits 11 to 13
, the same Brioli day control circuit 7 as in the conventional example, a priority data holding circuit 14 that holds the priority determined by the priority control circuit 7 as temporary information, and detects the start/end of a memory (not shown) access cycle. The data holding circuit 14 has a cycle control circuit 15 that generates the holding timing of the data holding circuit 14. As shown in FIG. 2, each →Navi control circuit 11-13 inputs a refresh 1- signal from a request source C2I) IJ (not shown) or a query 1-input terminal 1-. ~3. CPt that determines the priority order explained in the operation described below.
From the beginning of Zahis to the end of Zahis to J, that rifnis 1
-Continue input terminal 8-1.0 which inputs the continuation signal of the request source Zahis, and wait output terminal 4-6 which sends the hold signal due to priority order, are provided respectively. .

Next, the operation of this embodiment will be explained. The cases where the signal is input to the input terminal 1 to input terminal 2 are summarized. From this, if there is no request with a high priority and no other request is being serviced, the output from the output terminal 12B to the priority control circuit 7 is disabled by the logical sum of 0R22 of the service control circuit 12. The priority control circuit 7 sends a permission signal to the input terminals 1.2 and 2A via the data holding circuit 14, since there are no other priority riffs 1 to 1. This permission i]' signal sends a start signal to the corresponding CPU. On the other hand, if the CPU from the request input terminal 1 with a high priority is in service, the AND21 of the service control circuit 11 operates by logical product of the continue input signal and the input signal from the input terminal 11A. Therefore, this AND is sent to the priority control circuit 7 via the output terminal 11B, and furthermore, it is registered in the data holding circuit 14 that the CPU at the request input terminal is in service.

Here, if the continue signal is input prior to the request input signal, the request for the next cycle can be forwarded and notified to the priority control circuit 7, and the priority control circuit 7 can be notified of the request for the next cycle as well. If the price is high, the service can be continued. Such a registered take is sent to the service control circuit 12, and a hold signal is output from the wait output terminal 5 based on the logical product of AND20. The cycle control circuit 15 sends a signal not to cancel the service of the requester 1 until the service of the requester 1 is completed to the data holding circuit #r14, thereby continuing to hold other requests. In this way, in the conventional example, services are switched according to a predetermined priority order of multiple requests, but the service control circuits 11 to 13 are arranged corresponding to each request source, and the data holding circuit 14 is used to switch services according to the priority order of multiple requests. By reporting that the request source's service is continuing, the CPU that is being used preferentially can continue the service.

〔Effect of the invention〕

As explained above, by providing a plurality of service control circuits, data holding circuits, and cycle control circuits, the present invention provides access even when a request source that requests access to memory outputs a request signal at any timing. You can resolve conflicts and also
It is possible to provide a memory access control circuit that accepts requests in succession and prioritizes processing of requests that have gained access rights, thereby improving overall throughput. There is.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing one embodiment of the present invention, FIG. 2 is a circuit diagram of the main part of this embodiment, and FIG. 3 is a block diagram of a conventional memory access control circuit. 1-3...Request input terminal, 4-6...Wait output terminal, 7...Priority control circuit, 8-1
0...Continue input terminal, 11-13...Service control circuit, 14...Data holding circuit, 15...Cycle control circuit, 20.21...AND, 22...
0R1IIA, 12A, 13A...Input terminal, 11B
. 12B, 13B...output terminal, 4'...go output terminal.

Claims (1)

[Claims] In a memory access control circuit that prioritizes access request signals output from a plurality of memory access request sources, each memory access request source receives an input of the access request signal, an input of a memory access continuation signal, and a memory access control circuit. a plurality of service control circuits each having a terminal and a logic circuit for outputting an access suspension signal; a priority control circuit that assigns a priority to each access request signal of the plurality of service control circuits; a data holding circuit that holds determined priority information;
a cycle control circuit that detects the start and end of an access service during a memory access service and outputs an information retention timing signal to the data retention circuit, and one of the service control circuits continues the memory access. The memory access control circuit is characterized in that during a period in which the priority information determined by the priority control circuit is temporarily suspended, each of the other service control circuits outputs a memory access suspension signal.