JPH02287809A - Optical signal multiplier - Google Patents

Abstract

PURPOSE:To use the entire surface of an optical signal multiplier as a photoelectric conversion part by forming a photoelectric conversion part into the highest layer and then forming the 1st and 2nd memory transistors into a layer under the highest layer. CONSTITUTION:The picture memory transistors TR Q1 and Q2 containing MNOS memory gates MG (MG1 and MG2) are formed at a lower layer part LD, and a photoelectric conversion part is formed at an upper layer part LU composed of an amorphous Si:H film 31. Thus the photoelectric conversion operation is carried out via the film 31 formed on the entire surface of the part LU. At the same time, the value of multiplication between the charge amount stored previously after the photoelectric conversion operation and the charge amount which is under the photoelectric conversion operation can be obtained as an integrated value difference signal by reading the value of multiplication between the TR Q1 for reference and the TR Q2 for multiplication. Thus it is possible to obtain an optical signal multiplier having a 100% aperture rate.

Description

[Detailed Description of the Invention] [Industrial Field of Application] The present invention provides an amount of electric charge that has been photoelectrically converted and stored in advance;
This invention relates to an optical signal multiplier that can perform multiplication processing with the amount of charge currently being photoelectrically converted.

[Conventional technology]

Storage of optical signal image information and arithmetic processing are generally performed by computer program operations, but this method has the disadvantage that high-speed processing cannot be easily achieved. Therefore, if we could create an image sensor with a new structure called a smart sensor that performs uniform calculations on the entire screen during the photoelectric conversion process of optical signals, it would be possible to process image information in parallel.
It is thought that it can be applied to simple terminal equipment that performs high-speed processing such as image correlation and classification.

Such an imaging device basically requires three functions: imaging and storage/arithmetic processing. Among these, an image memory element that stores optical signals in analog form in each pixel of an image sensor is described in IEEE Electron Device Magazine ED-32 (19
There is an image memory device disclosed in the paper ``Solid-state image sensor incorporating rMNOs memory gate'' by H. Yamasaki et al. in 1985).

FIGS. 2(a) and 2(b) are a circuit configuration diagram showing the basic configuration of this image memory element and a sectional view showing the sectional structure of one pixel.

In FIG. 2(a), 41 is a horizontal scanning circuit, 42 is a vertical scanning circuit, 43 is a read/write switching circuit, 44 is a horizontal switch MO8+- transistor, 45 is an integrating circuit for detecting a read signal, and VS is a video signal Output line, ■ is video output, POl) is OHALF UT load drain terminal, PoG is overflow gate terminal 1. l! 2 is an A9 horizontal selection line, p3 is an A, Q vertical signal line, and p4 is an overflow drain line.

Further, 46 indicates an image memory component for one pixel, which includes a photodiode PD, an overflow gate, an MNO
It is composed of transistors T1 to T3 each having an S memory gate I. and a transfer gate I.

As shown in FIG. 2(b), each pixel 46 has four n+ diffusion layers 51 to 54 formed in the upper layer of a p-type Si substrate 50. As shown in FIG. An overflow gate OG made of polysilicon is formed on an r) type Si substrate 50 between the n+ diffusion layers 5], 52 via a 5IO2 film 55. Furthermore, an MNOS memory gate MG made of polysilicon is placed on the p-type Si substrate 50 between the n+ diffusion layers 52 and 53.
A transfer gate TG made of polysilicon is formed between the p-type Si substrate 50 and the n+ diffusion layer 5354 via the SiO2 film 55. Then, the transistor T1 is connected to the n+ diffusion layer 5 by the n+ diffusion layer 5152 and the overflow gate OG.
2.53 and the MNOS memory gate MG form the memory transistor T2, and the n+ diffusion layer 53.54 and the transfer gate T.
G connects the transistor T3 to the n+ diffusion layer 52 and the p-type S
A photodiode PD is formed by a pn junction with the i-substrate 50. The above transistor T2. T3 constitutes a dual gate transistor.

Also,? S102 film 55°513N4 on the diffusion layer 54
A and Q vertical signal lines ρ3 are formed through the film 56, and n
+SiO2 film 55°Si3N4 film 56 on the diffusion layer 51
An overflow drain line p4 is formed passing through.

The MNOS memory gate MG in the memory transistor T2 is a composite film composed of an S102 film 55 and a Si3N4 film 56, and stores a signal when a signal is desired to be written. In other words, some of the photoexcited charges are
Inside the 513N4 film 56 and the SiO film 55 and Si3N4 film 5
The image information is captured in a trap at the interface with 6 and is stored in analog form by changing the flat band voltage V1)13.

Further, the transistor T3 having the transfer gate TG functions to prevent the charges accumulated in the memory transistor T2 from flowing out to the Aρ vertical signal line ρ3 by being turned off. Transistor T] overflow day 1-O
G, n+ diffusion layer 5] are an overflow gate terminal P and an overflow drain terminal P, respectively. , performs a preset operation of the four diode PD during writing as will be described later. Furthermore, when taking images, strong light is
When the diode PD is irradiated, the photodiode PD
It also serves as an overflow drain that sweeps away overflowing charges and suppresses blooming. Furthermore, the overflow gate terminal POG and the overflow drain terminal PoD serve as sources of a certain amount of charge during reading, as will be described later.

The read/write switching circuit 43 allows a positive write voltage,
Alternatively, apply a negative erase pulse voltage to the memory transistor T2.
Writing and erasing into the memory transistor T2 can be performed by applying the signal to the MNOS memory gate 1-MG. on the other hand,
Reading of the memory contents of the pixel 46 (including during imaging) is performed by the horizontal scanning circuit 41 and the vertical scanning circuit 42, respectively.
This can be done by applying a scanning pulse through the vertical signal line β3 and the A and Q horizontal selection lines 92 to scan each pixel 46 and read out the information.

FIG. 3 is a potential distribution diagram for explaining the write operation to the image memory shown in FIG. 1 shows the potential distribution on one surface (hereinafter referred to as “substrate surface”). In the figure, the downward direction is the positive potential direction. The writing principle will be explained below with reference to the same figure.

First, a reset pulse is applied from the overflow gate terminal PoG to the overflow gate OG of the transistor T1, and as shown in FIG. Set the charge amount EO in the preset state to
Determine.

In this state, when light is incident on the photodiode PD for a certain integration period T1, the photo-excited optical signal charges are accumulated in the n+ diffusion layer 52, and the potential is reduced to V as shown in FIG.
Descend to 8□. Note that E2 indicates the amount of optical signal charge. This operation is I old εEJ, 5olid-8tale C1r
cuits, Vol 5C-2, no, 12 p, Et
G, P, Weck in 5-735apL 1967
Ke's paper "0perajion orpn jun"
ction photodeLectors jn a
photon flux integration
P FI (Photon-Flux In
tcgration) mode.

After this, when a positive write pulse voltage is applied to the MNOS memory gate MG of the memory transistor T2, the MNOS
The substrate surface potential φMG under the memory gate MG increases, and n
The charges accumulated in the + diffusion layer 52 are transferred under the MNOS memory gate 1-MG in the BBD mode, as shown in FIG. Then, an equilibrium state is reached at an equilibrium potential v8F in which the charges accumulated under the n+ diffusion layer 52 and the MNOS memory gate MG are balanced, and the transfer of charges is completed as shown in FIG. 4(d). In addition, El is the preset charge amount EO
is the amount of bias charge transferred.

After that, as shown in the same figure (e), the MNOS memory game h
A part of the charge on the substrate surface under the MG is tunnel-injected into the thin 5i02 film 55, and the S102 film 55°Si3N4 film 56
captured by the interface trap.

As a result, the flat band voltage VPB of the MNOS memory gate 1-MG in the memory transistor T2 increases. This flat band voltage VFB has a negative correlation with the substrate surface potential φMG under the MNOS memory gate MG.If the voltage applied to the MNOS memory gate MG is the same, the higher the flat band voltage V, the substrate surface potential φ
. . becomes lower. In this way, the optical information photoelectrically converted by the photodiode PD is stored as analog information in the MNOS memory gate 1-MG of the memory transistor T2 as a displacement of the flat band voltage vFB.

Therefore, there is no need to separately provide an A/D conversion section.

At this time, the lower the preset voltage Vso is, the greater the preset charge amount EO is for the same optical signal charge amount E2. Substrate surface potential φ
The difference with MG becomes larger. As a result, the bias charge jt
As E1 increases, the equilibrium potential VSP increases, and M
NOS memory game) The amount of charge accumulated under MG increases. Therefore, the potential difference between the MNOS memory gate MG and the SIO2 film 55, which is a tunnel insulating film, becomes large, and even with a small amount of incident light, charges are tunnel-injected into the 5102 film 55, allowing writing to be performed in a short time. However, if the preset voltage Vso is lowered too much, the bias charge amount E1 will increase too much, and the flat hand voltage VI'I3 will change greatly regardless of the increase or decrease in the optical signal charge amount E2. This must be taken into account since the range of

FIG. 4 is a potential distribution diagram for explaining the read operation from the image memory shown in FIG. 2, and in particular, the n+ diffusion layer 52. The potential distributions of the substrate surface under the memory gate MG, the substrate surface under the transfer gate TG, and the n+ diffusion layer 53 are shown. The readout principle will be explained below with reference to the same figure. Note that during reading, the substrate surface potential φTG under the transfer gate 1-TG is MNOS of the transistor T2.
A voltage is applied to the transfer gate TG of the transistor T3 so as to be higher than the maximum level of the substrate surface potential φ when the scanning pulse is applied to the memory gate IMG.

First, M of the memory transistor T2 in each pixel 46
The horizontal scanning circuit 41 connects the NOS memory gate MG to
Horizontal scanning pulses are sequentially applied via the A and Q horizontal scanning lines p2. Then, when the voltage applied to the n+ diffusion layer 54, which is the drain of the transistor T3, is sufficiently large, the potential Vs of the n+ diffusion layer 52, which is the source of the transistor T1, becomes the voltage below the MNOS memory gate MG, as shown in FIG. It is fixed at the substrate surface potential φ. Note that φ is the erase state, MC1, MCI is M in the 0 write state as analog information.
The substrate surface potential under the NOS memory gate MG, φ, indicates the substrate surface potential under the MNOG2S memory gate MG in the writing state of optical signal charges. □
The read operation CI at the substrate surface potential φ will be explained below. At this time, it is assumed that the voltage applied to the MNOS memory gate MG is sufficiently small so that writing does not occur.

When the scanning pulse to the memory gate 1-MG ends, the n+ diffusion layer 52, which is the source of the transistor T1, is reverse biased, and a potential well is formed as shown in FIG. 1(b). The depth of this potential well is determined by the substrate surface potential φ under the MNOS memory gate 1-MG when the scanning pulse is applied.

Then, by applying a predetermined voltage from the overflow gate I terminal POG at a time corresponding to each retrace period of horizontal scanning, the overflow gate 1-OG of the transistor T is turned on, and the overflow drain terminal P is turned on. By supplying a predetermined voltage to the n+ diffusion layer 51, which is the drain of the transistor T1, as shown in FIG.
Charges are injected into all of the n+ diffusion layers 52 that also form.

After that, the MNO of the memory transistor T2 of each pixel 46
Sequential scanning pulses are applied to the S memory gate 1-MG, and as shown in FIG. It is transferred to the n+ diffusion layer 54. In other words, the substrate surface potential φ□. The lower the value of 1, the less charge will be transferred to the n-diffusion layer 54. The charges transferred to the n+ diffusion layer 54 are transferred to the Ap vertical signal line p3. The signal is outputted as a video output V through a transistor 44 degree integration circuit 45. That is, the stored contents of the MNUT OS memory gate MG can be read out as analog information from this video output V. In this operation, MNOS memory game 1-M
When G is turned on, the n+ diffusion layer 52 to the n diffusion layer 5
The amount of charge flowing through the MNOS memory gate 4 becomes smaller as the substrate surface potential φMG under the MNOS memory gate 1-MG becomes smaller. Also, as mentioned above, the substrate surface potential φ□.

Since there is a negative correlation with the flat band voltage ■F13, the flat I band voltage ■11, and the larger I3, [1
+The amount of charge flowing into the diffusion layer 54 is reduced. Therefore, the larger the amount of charge accumulated in the MNOS memory gate MG during writing, that is, the larger the optical signal charge amount E2, the smaller the video output (2) during reading becomes.

UT On the other hand, in order to erase the information stored in the memory transistor T2, a large negative erase pulse voltage is simultaneously applied for a certain period of time to the memory gate MG of the memory transistor T2 of all the pixels 46, and charges are tunnel-released from the Si○2 film 55. This is done by lowering the flat band voltage PB. This erasing operation causes the reflat hand voltage vr:B to return to its initial state.

Next, the imaging operation will be explained. First, a constant voltage is applied to the transfer gate TG of the transistor T3 of all pixels 46, and the MNOS memory gate 1-MG of the memory transistor T2 is periodically turned on with a small voltage that does not cause writing. The accumulated optical signal charges are output from the n+ diffusion layer 54 as a video output V. At this time n
+ If the potential of the diffusion layer 5UT 4 is ■, φ ku■, φMo<φ, 0D
It is necessary to set it to MG D. This is to prevent the difference in the substrate surface potential φMG due to the displacement of the flat band voltage VFI3 stored in the MNOS memory game 1-MG from affecting the video output V.

UT In this way, the image memory device shown in FIGS. 2 to 4 is realized by injecting and capturing photo-excited charges into the MNOS memory gate MG, and the stored contents are stored in the MNOS memory gate MG.
This can be observed by changes in the flat band voltage ■PB of the memory gate MG. That is, this image memory element has M
NOS memory game) It has a structure in which a pn photodiode PD is charge-coupled to the MG, and a bias charge is superimposed on the optical signal charge generated by the photodiode PD, and a weak optical signal can be efficiently written in a short period of time while being stored. The contents can be easily read out non-destructively.

An optical signal multiplier that performs multiplication between incident image information and stored image information on an imaging surface using the above-mentioned image memory element is an I.
EEE Electron Device Letter Magazine EDL-6 (
1985) by H. Yamasaki et al.
"Optical multiplication operation in solid-state image sensor with built-in s memory"
has been disclosed. FIGS. 5(a) to 5(d) are explanatory diagrams showing the principle. FIG. 5(a) shows the basic configuration of the pixel of the optical signal multiplier, and FIG. 5(b) shows its potential distribution. 5(C) shows the waveform of the multiplication value readout pulse, and FIG. 5(d) shows the temporal change in the source potential s with respect to the multiplication value readout pulse shown in FIG. 5(C). . As shown in FIG. 5(a), this optical signal multiplier uses a dual-gate reference transistor Ql (gate hMG1.TGI) for one pixel, which shares an n+ common source layer 71, and a multiplication transistor Ql (gate hMG1.TGI) for multiplication. It is composed of a transistor Q2 (gate 1-MG2.TG2). These transistors Q1 and Q2 are the MNO transistors shown in FIG. 2(b).
S memory gate 1-MG This is a transistor equivalent to a dual gate transistor having a transfer gate TG.

The principle of optical signal multiplication will be explained below. First, assume a situation in which photoelectric conversion analog data is stored in advance in the MNOS memory gate MG2 of the multiplication transistor Q2 in the same manner as in the image memory device shown in FIGS. 1 to 4.

Under this situation, transistor Q1. Transfer gate TGI in strong inversion state for each Q2
The area under TG2 is regarded as a virtual drain region, and its potential is set to V,
In this case, transistors Ql and Q2 can be considered as single-gate (MGl, MG2) FETs. In this case, each transistor Q1 . Q2
The drain current 1dl, Id2 is as follows (la),
It is given by equation (1, b).

Idl-β (V-V8) [V-V-(V,,+V8)/2]MG
Tl...(1a) Id2=β (■1)-Vs) [V -V -(V +V,) /2]MG
T2 1) (It)) However, β is the gain factor, Vs is the source potential, ■
is the memory gate voltage, V and V are respectively MG
TI T2 transistor Q],
, is the threshold voltage of Q2.

Also, the potential difference ΔvFB between the flat band voltages is ΔvFB=■T2-VT1(2) It is expressed as

Q is the result of integrating the current difference between the drain currents Idl and Id2 over the multiplication value reading pulse period t. , 1, the integral value Q is expressed by the following equation (3). ut can do it.

On the other hand, the multiplication value readout pulse interval is 11 (Fig. 5(c)).
The amount of signal charge Q stored in the source in (see) is given by the following equation: If the source potential at the time of presetting is Vl (-1g ■D), the source potential immediately after the accumulation time has elapsed is V2, and the storage capacitance of the source is C, It is expressed by the following equation (4).

Here, ■ is the photocurrent amount, η is the photoelectric conversion sensitivity, and L is the incident light intensity. Ignoring the voltage dependence of the source storage capacitance C, equation (4) can be approximated by the following equation (5).

Q and c (v2-v,)=-ηLt,...(5
)1g Figure 6 shows the temporal change in the source potential v8 during application of the multiplication value read pulse. From the start of the readout multiplication value readout pulse (application) until time t has elapsed, the source potential (2) rises from v2 to v1 (=VD). Here, if the change in source potential V8 is approximated by a straight line, equation (3) becomes the following (
6) It can be expressed by the formula.

yi' (V - V2)/2 = - (6)w
1 In equation (6), time t' is a value equivalent to the time constant of the potential change of the source potential VS, and in the range where the potential difference ΔvFB is small compared to the multiplication value read voltage MG, the potential difference Δ
Regardless of V1 and B, it can be regarded as constant.

Then, from the above equations (3), (5), and (B),
The following equation (7) can be derived.

Since the change in flat band voltage V is proportional to the amount of optical signal written during the writing period B, finding the integral value Q means multiplying the amount of stored optical signal by the amount of optical signal during imaging. I will ask for it.

The above is the principle of optical signal multiplication.

FIG. 7 is a circuit configuration diagram showing the basic configuration of this optical signal multiplier. Note that in this figure, explanations of the same components as in FIG. 2(a) will be omitted. In the figure, 76 indicates an image memory component for one pixel, which includes a photodiode PD, a reference transistor Q1, a multiplication transistor Q2, and an I transistor TIO having an overflow gate.
It is composed of And reference transistor Q1
The MNOS memory gates 1-MG1 are connected to the reference gate selection lines R3LI to 3 in units of horizontal direction, respectively.
The MNOS memory gate MG2 of the multiplication transistor Q2 is connected to the multiplication gate selection lines MSL1 to MSL3 in vertical units, respectively.

Also, the transfer gate T of the reference transistor Q1
The drain of GI is connected to the reference vertical signal line RVL in the vertical direction.
1 to 3, respectively, and the drains of the transfer gates TG2 of the multiplication L/Rangis Q2 are connected to the multiplication vertical signal lines MVLI to MVLI, respectively, in the vertical direction.

Reference vertical signal line RVL 1 to 3 are selection transistors S
The vertical signal lines MVL1-3 for multiplication are connected to the integrator 81 via TI-ST3, and the selection transistors ST
It is connected to the integrator 82 via 4-6. The selection transistors ST4 to ST6 are controlled to turn on and off by the horizontal synchronization circuit 41, and the selection transistors ST] to ST3
The on/off state is controlled by a horizontal synchronization circuit having the same configuration as the horizontal synchronization circuit 4 (not shown).

In such a configuration, first, the multiplication selection signal line MSL
By applying a write pulse to the memory gates 1 to 3 (at this time, no write pulse is applied to the reference selection signal lines R8LI to R3L3), the memory gates 1 to 3 of the multiplication transistor Q2 are
The flat hand voltage vPB of MG2 is changed to perform analog storage of optical information.

Next, the memory gates of the multiplication and reference transistors Ql and Q2 are connected via the multiplication selection signal lines MSL1 to 3 and the reference selection signal lines R8LI to 3. .

At the same time as applying a voltage value 1 to MG2 to read out the multiplication value of MG, the transfer gate 1 TGI of all pixels 76 is applied.
Transfer gate voltage ■□ to TG2. give. This transfer gate voltage (G) is a sufficiently large voltage with respect to the drain voltage (G). And horizontal scanning circuit 41,
The reference vertical signal line R is controlled by the vertical scanning circuit 42, etc.
The drain current Id of the reference transistor Q1 in each pixel 76 is sequentially supplied to the integrator 8 through VL1 to VL3, and at the same time, the integrator 82 is supplied to each pixel through multiplication vertical signal lines MVL1 to MVL3. The train current Id2 of the multiplication transistor Q1 at 76 is sequentially applied. The integrator 8182 outputs integration results Sl and S2 of the drain currents Idl and Id2 of the same pixel 76 during the read pulse period t 1 , respectively. Then, by calculating (Sl-52) by a difference circuit (not shown), the integral value Q of equation (3) is obtained, and the optical signal information stored in analog form in the multiplication transistor Q2 and the optical signal during the multiplication value reading period are obtained. Information multiplication results can be obtained.

[Problem to be solved by the invention]

Conventional optical signal multipliers are configured as described above, and because the photoelectric conversion section, storage section (multiplication section reference section), and scanning circuit are provided on the same plane, the aperture ratio is limited and the photoelectric conversion sensitivity deteriorates. There was a problem with that.

This invention has been made to solve the problems mentioned in item 1 above, and its purpose is to obtain an optical signal multiplier that can make the aperture ratio required for photoelectric conversion 100%.

[Means to solve the problem]

a photoelectric conversion unit; a first memory transistor that is electrically connected to the photoelectric conversion unit and stores the amount of charge in analog form by changing transistor characteristics according to the amount of charge converted by the photoelectric conversion unit; a second memory transistor having the same configuration as the first memory transistor, which is electrically connected to the photoelectric conversion unit and shares one electrode with one electrode of the first memory transistor;
and integral value difference means for performing differential processing of integral values of the first and second currents respectively obtained from the other electrode of the second memory transistor over a predetermined period and outputting an integral value difference signal; A write signal is applied to the control electrode of the first memory transistor, the amount of charge converted by the photoelectric conversion unit is stored in analog form in the first memory transistor, and when reading the multiplication value, the first and second
By applying a multiplication value readout signal to the control electrode of the memory transistor of the first memory transistor and causing the integral value difference means to output the difference integral signal, the amount of charge converted by the photoelectric conversion section during the multiplication value readout period and the first and a control means for outputting a multiplied value by the amount of charge stored in the memory transistor, and the photoelectric conversion section is the uppermost layer.
The first and second memory transistors are formed in a second layer below the first layer.

[Effect]

Since the first layer in this invention does not need to have any function other than the photoelectric conversion function, the entire surface can be used as a photoelectric conversion section.

〔Example〕

FIG. 1 is a sectional view showing one pixel of an optical signal multiplier according to an embodiment of the present invention. Note that the basic configuration of this optical signal multiplier is almost the same as that shown in FIG.

However, the photodiode PD is not used as the photoelectric conversion means, but the amorphous Si+H film 31 is used.

As shown in the same figure, the MNO shown in FIG.
Two image memory transistors Q1Q2 each containing an S memory gate 1-MG (MCI, MG2) are formed, and a photoelectric conversion section made of an amorphous SIH film 31 is formed in the upper layer LU.

In this photoelectric conversion section, the glass plates 32
One color filter 33. Adhesive 34. Transparent electrode 35 An amorphous Si:H film 31 is formed.

As a solid-state image sensor using such a photoelectric conversion unit, for example, the Technical Report of the Television Society (MG15, No. 2)
9 ED606 (1981), Umaji et al.
There is a solid-state image sensor disclosed in ``Design, Prototype, and Characteristic Evaluation of Single-Plate Color Solid-State Image Sensor Using Amorphous Si''.

Then, between the A, Q layer 27 and the n+ diffusion layer 52,
A layer 60 is formed penetrating through the SiO film 55 and the 513N4 film 56 to electrically connect the amorphous Si:H film 31 and the n+ common source layer 7]. Also upper layer L
The other region between U and the lower layer LD is insulated by an interlayer insulating film 61 made of polyimide or the like. This interlayer insulating film 6] also has the role of planarizing the lower layer LD.

On the other hand, in the lower LD, on the p St substrate 50, a reference transistor Q having the same configuration as the dual gate transistor consisting of the transistors T2T3 shown in FIG.
l (memory game-1-MGl, transfer gate TG
1) and multiplication transistor Q2 (memory gate MG2
．． h transfer gate TG2) is formed. Note that the other configurations are the same as the configurations of the conventional example shown in FIGS. 2 and 7, so the explanation will be omitted.

With this configuration, the upper layer L formed on the entire surface
While performing photoelectric conversion using the amorphous Si:H film 31 of U, the multiplication value of the amount of charge previously photoelectrically converted and stored and the amount of charge currently being photoelectrically converted is transferred to the reference transistor Q1 and the multiplication transistor Q2. Figure 5~
The integral value difference signal (S]-82) can be obtained by the multiplication value reading operation described in the conventional example of FIG. As a result, an optical signal multiplier with an aperture ratio of 1.00% can be obtained. The multiplication value reading operation is the same as described in the conventional example except that the photoelectric conversion means is changed from a photodiode to an amorphous Si:H film.

In this example, an MNO8 structure made of a 513N4 film was shown as a nonvolatile I transistor, but a floating gate MOS FET structure,
M ON OS (Metal Oxide N1t
Other non-volatile 1-transistors may also be used, such as oxide semiconductors. In other words, by changing transistor characteristics such as the flat band voltage VFB according to the amount of optical signal charge, the amount of optical signal charge can be stored in analog form, and the optical signal multiplication principle shown in FIGS. 5 and 6 can be applied. Any suitable transistor can be used instead.

Furthermore, in this example, an amorphous Si:H film was used as the photoelectric conversion means, but a new bicon film (Zn
Other photoelectric conversion films such as CdTe)
X may be used.

〔Effect of the invention〕

As explained above, according to the present invention, since the first layer does not need to have any function other than the photoelectric conversion function, the aperture ratio can be set to 100% when the entire surface is used as the photoelectric conversion section.

Further, the control means utilizes the difference in transistor characteristics between the first and second memory transistors formed in the second layer to control the amount of charge stored in the first memory transistor and the multiplication value during the reading period. A value multiplied by the amount of charge converted by the photoelectric conversion section can be output as an integral value difference signal.

[Brief explanation of drawings]

FIG. 1 is a sectional view showing an optical signal multiplier that is an embodiment of the present invention, and FIGS. 2(a) and 2(b) are circuit configuration diagrams showing the basic configuration of a conventional image memory device, respectively. A cross-sectional view showing the cross-sectional structure of one pixel, FIG. 3 is a schematic diagram of the potential distribution showing the write operation of the image memory element shown in FIG. 2, and FIG. 4 is a readout diagram of the image memory element shown in FIG. A schematic diagram of a potential distribution showing the operation, Figures 5 and 6 are explanatory diagrams showing the principle of a conventional optical signal multiplier, and Figure 7 is an optical signal multiplication based on the principle shown in Figures 5 and 6. FIG. 2 is a circuit diagram showing the basic configuration of the device. In the figure, 31 is an amorphous S i :H film, 2
7.60 is A, Q layer, 53.54 is n+ diffusion layer, 71 is n+ common source layer, Ql is reference I transistor, Q2
is a multiplication transistor. Note that the same reference numerals in each figure indicate the same or corresponding parts.

Claims (1)

[Claims] (1) A photoelectric conversion unit; and a first memory that is electrically connected to the photoelectric conversion unit and stores the amount of charge in analog form by changing transistor characteristics according to the amount of charge converted by the photoelectric conversion unit. a second memory transistor having the same configuration as the first memory transistor, which is electrically connected to the photoelectric conversion section and shares one electrode with one electrode of the first memory transistor; and integral value difference means for performing differential processing on the integral values of the first and second currents respectively obtained from the other electrode of the second memory transistor over a predetermined period and outputting an integral value difference signal; A write signal is applied to the control electrode of the first memory transistor, the amount of charge converted by the photoelectric conversion unit is stored in analog form in the first memory transistor, and when the multiplication value is read, the amount of charge of the first and second memory transistors is By applying a multiplication value readout signal to the control electrode and causing the integral value difference means to output the differential integration signal, the amount of charge converted by the photoelectric conversion section and the first memory transistor during the multiplication value readout period are An optical signal multiplier comprising a control means for outputting a multiplied value by a stored amount of charge, wherein the photoelectric conversion section is formed in a first layer that is an uppermost layer;
An optical signal multiplier, wherein the first and second memory transistors are formed in a second layer below the first layer.