JPH02287678A - Cad system for logical diagram - Google Patents

Abstract

PURPOSE:To decrease an instruction miss, a design miss and a manufacturing miss, etc. by executing an instruction for bringing a wiring hole of parts which are not mounted actually on a substrate to wiring to a ground and a power source, etc., on a net list. CONSTITUTION:When a user generates a parts file 11 by a file generating part 12, an operation for inputting logical drawing generating information such as arrangement information on a substrate of various parts in each part of a circuit required for generating a logical diagram of a desired logic circuit board, connecting information of each pin between each parts shown by this arrangement information, etc., is executed by using an input device. In this case, it is supposed that a position in which a dummy symbol defined by DUM MY #20 is not placed actually but there is possibility that it is placed in the future, and logical diagram generating information for showing the connection to a ground of the pin of pin number 20 of the same symbol are also inputted. In a logical diagram file generating part 14, a logical diagram file 13 consisting of information of many logical diagram realized on the substrate is generated, based on the logical diagram generating information inputted from the input device and the file 11.

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial Application Field) The present invention relates to a CAD system for logic drawings applied to board wiring.

(Prior Art) Generally, in a CAD system for logical drawings, drawings are created by interconnecting ten symbols registered for each part (or each functional block). Also, C for logical drawings.
The AD system generates a parts list, which is a list of information about parts placed on a board (printed board, multi-wired board), and a netlist, which is a list of connection information between parts, based on the created drawing. Circuit (logic) simulation is performed.

Now, in the case of prototype or research product boards, it often happens that additional parts are required. Therefore, in consideration of the possibility of adding components to this type of board, it is necessary to form holes (wiring holes) for wiring additional components even in locations where components are not mounted. Since such holes are not included in the netlist, they are simply formed and no wiring is performed at all. Therefore, if you wish to connect the holes in which the above-mentioned components are not mounted to the ground or power supply in advance, when requesting board installation,
It is necessary to provide wiring instructions for this type of hole separately from the netlist.

However, wiring instructions performed separately from the netlist have a problem in that they are prone to instruction errors, design errors, and production errors.

On the other hand, instead of instructing wiring separately from the netlist, there is a method of arranging the above-mentioned components that are not actually mounted in the logical drawing. According to this method, since wiring instructions can be given on the netlist, there is no possibility of the above-mentioned instruction errors and production errors, but there are problems (1) to (4) below.

■ When performing circuit simulation, the parts that are not actually mounted as mentioned above do not work at all, so the simulator will issue a notification saying, ``There are parts that do not work at all, so please add a test vector to make them work.'' the simulation may be considered invalid.

- When creating a parts list, the unmounted parts are also counted, so when arranging parts based on the parts list, there is a risk of purchasing extra parts.

■ Similarly, when determining the manufacturing cost of a board based on a parts list, there is a risk that the cost of parts that are not actually used may be counted.

(Problems to be Solved by the Invention) As mentioned above, in the conventional Jiff drawing CAD system, wiring holes for unmounted components are formed on the board in consideration of the possibility of adding components in the future. If you are trying to connect a hole that is connected to the ground or power supply, using a method that specifies wiring separately from the netlist will lead to instruction errors, design errors, manufacturing errors, etc. Unable to perform circuit simulation, n
There was a problem that effective parts management could not be performed.

Therefore, the problem to be solved by this invention is to be able to instruct wiring holes for components that are not actually mounted on a board to ground, power supply, etc. without causing instruction errors, design errors, manufacturing errors, etc. Moreover, it is to be possible to perform correct circuit simulation and effective component management.

[Structure of the Invention (Means for Solving the Problems) This invention provides a component (dummy component) that is not actually mounted on a board but requires wiring through a wiring hole in a Noss board-L.
A specific component symbol, which is defined as being distinguishable from other components actually mounted on the board and logically completely non-functional, is assigned to the various components including dummy components to which this specific component symbol is assigned. By generating a logic drawing file that stores ethical drawing information regarding a logic circuit realized by interconnecting components, and by generating a netlist based on this logic drawing file, wiring holes in dummy components can be easily This system is characterized in that wiring instructions are given on a netlist. Further, in the present invention, a dummy component to which a specific symbol on the above-mentioned netlist is assigned is also apparently operated, and circuit simulation is performed on the assumption that the dummy component is logically non-functional. Based on the file, a list of components to be actually mounted on the board is generated depending on whether a specific symbol is 9 or 0.

(Function) According to the above configuration, wiring instructions for wiring holes of components (dummy components) that are not actually mounted on the board are made on the netlist, so there is no possibility of instruction errors, design errors, and manufacturing errors. can be reduced.

In addition, in circuit simulation, dummy components are also moved upward, and dummy components, that is, dummy components defined with specific symbols, are treated as logically non-functional, so the wiring of dummy components Correct circuit simulation is possible even when instructions are given on the netlist. Furthermore, the parts list generated based on the logical drawing file can be prevented from including dummy parts depending on the presence/absence of a specific symbol, making it easier to manage parts purchasing and reduce board manufacturing costs. Calculations, etc. can be performed correctly.

(Embodiment) FIG. 1 is a logical diagram 11 according to an embodiment of the present invention.
It is a functional block block diagram of D system.

In the figure, numeral 11 stores information regarding components to be mounted on a board such as a printed circuit board or a multi-wired circuit board, as well as components that may be added in the future even if they are not mounted (hereinafter referred to as dummy components). (hereinafter referred to as a component file). Parts file 11
is the shape of each part (part symbol on the physical drawing)
, contains information such as internal logic operations of parts, packages, and attributes of each bin. Here, the symbol of the dummy part is called a dummy symbol, and is defined by, for example, a character string D U M M Y. This dummy symbol is logically completely non-functional.

Reference numeral 12 denotes a component file creation unit that creates a component file 11 based on component information manually entered by the user, and J3 stores information regarding one unified logical function realized by interconnecting components in the component file ll. File (
The following is a logical drawing file). Logical drawing file 1
3 also includes information regarding the arrangement (mounting) position of each component on the board for realizing the above logical function.

14 inputs logical drawing creation information for instructing component placement, wiring, etc. necessary to realize the above-mentioned logical machine 1j, and based on this logical drawing creation information and the parts file 11, 254. -The theory of creating a logical file ■3 (11!
This is the drawing file creation department.

15 is the type and number of parts actually used on the board;
A file that stores list information such as mounting locations (hereinafter referred to as
), 1G is W I11! This is a parts list creation unit that creates a parts list file 15 based on the drawing file 13. The parts list creation unit 16 has a dummy parts identification function, and is configured not to overwrite dummy parts in the parts list file 1:). 17 is a file (hereinafter referred to as a netlist file) of an information list (netlist) regarding the connections of each bin of each component indicated by the information in the logical drawing file 13; 18 is a netlist file based on the logical drawing file 13; A netlist file creation section 17 creates a netlist file, and a circuit simulation section 19 performs a circuit simulation based on the netlist file 17 and the component file 11.

Next, the operation of the configuration shown in FIG. 1 will be explained.

First, when a user attempts to create a logic drawing of a desired logic circuit board using the system shown in FIG. parts), and even parts that may be added in the future even if they are not actually implemented (dummy parts)
For each part, the part file creation part generates part information including the part symbol in a logical drawing, the logical operation inside the part, the package, and the attributes of each bin (such as whether it is an input bin or an output bin). E'- for input to 12
make a work The component file creation unit 12 creates a component file 11 based on component information for each component input manually from an input device.This component file 11 includes, for example, D
20-bin D I P defined in UMMY#20 (
It is assumed that information on a dummy symbol (dummy part) of the Dual In-1ine Package) type is included. The parts file creation unit 12
When registering information on a dummy symbol having the character string Y in the component file 11, set the capacity (impedance) of the bin to an appropriate value (for example,
Automatically set to O).

The user creates the component file 1 by the component file creation unit 12.
1 is created, using manual equipment, information on the placement of various parts on the board in each part of the circuit necessary for creating the logic diagram of the desired logic circuit board, and the location of each bin between the parts indicated by this placement information are recorded. Perform operations to input logical drawing creation information such as connection information. Here, the position of the dummy symbol defined by DUMMY #20 that is not actually placed (implemented) but may be placed in the future, and the position of the 20th bin (bin number 20) of the same symbol to the ground are shown. It is assumed that the logical drawing creation information showing the connections was also created manually.

The logical drawing file creation unit 1.t creates, for example, a logical drawing of the entire circuit consisting of several 11-logical blocks, and a logical drawing for each logical block, based on the logical drawing creation information and the component file 11 manually inputted from the human-powered device. A logic drawing file 13, such as a logic drawing, is created which is made up of information on a large number of logic diagrams 1fii that hierarchically represent one logic circuit implemented on a board. DUMM included in this 1-graphics file 13
FIG. 2 shows the state of the logical drawing near the dummy symbol defined by Y#20. In Fig. 2, 21 is a DIP type dummy symbol with 20 bins, 22 is a 20-bin wiring hole of the dummy symbol (21), and 23 is a hole to which this 20-bin wiring hole (22) is connected. Indicates the ground.

Logical drawing file 1 created by logical drawing file creation unit 14
3 is completed, the parts list creation unit IG can create the parts list file 15, and the netlist file creation unit 18 can create the netlist file 17. First, the parts list creation unit 16 extracts information including the type, number, mounting position, etc. of parts used on the board from the logical drawing file 13, and creates a parts list file 15 in a list format. At this time, the parts list creation unit 1G creates a symbol (
Dummy symbols) are not considered to be parts that make up the parts list, and therefore are not included in the list. That is, the parts list file 15 is created which consists only of the parts actually mounted on the board. Using the parts list file 15 created in this way,
By arranging parts and calculating the manufacturing cost of the board (completed board until mounting), you can avoid problems such as purchasing unused parts (dummy parts) by mistake or counting the price of unused parts. It can be eliminated.

On the other hand, based on the contents of the logical drawing file 13, the netlist file creation unit 18 generates a netlist file, which is a list (netlist) file indicating which bin of which part each signal line is connected to. A file (connection information file) 17 is created. Information regarding dummy symbols is reflected in this netlist file 17, as shown in FIG. FIG. 3 shows a list of dummy symbols defined by DUMMY#20 included in the netlist file 17. According to the list i in FIG.
It is instructed to wire to D).

Therefore, by using the netlist file 17 that includes the list part shown in Figure 3, the preliminary designer can (to the same designer) either request a reference design or request a reference design for the wiring of components that will not actually be mounted. Even if the wiring instructions for the hole are not specified separately from the netlist, for example, the fourth (DUMM
2 of dummy symbols (dummy parts) defined by Y#20
Wiring (to the ground) of (the wiring hole corresponding to) the 0 bin can be performed. In addition, in FIG. 4, 41 is a virtual placement position (planned placement position) of the above-mentioned dummy symbol.
42 is a group of wiring holes for dummy symbols, 43 is wiring hole 1
! 142, ('th in netlist file 17)
This is a wiring hole (bin number 20) that is designated as a wiring (to ground) by the list part shown in Figure 3.

When the creation of the netlist file 17 by the netlist file creation unit ill is completed, the circuit simulation by the circuit simulation unit 19 becomes possible. When performing this circuit simulation, the circuit simulation unit 19 uses the connection information in the netlist file 17 and the component information in the component file 11 (the capacity forming part of the attributes of the bins of each component therein). , the propagation delay time is calculated in consideration of the impedance of each signal line. In this embodiment, the capacitance of the pin of a dummy component (dummy symbol) that is not actually mounted is set to an appropriate value by the component file creation unit 12, so the netlist file 1
Even if the wiring of dummy parts (dummy symbols) is specified in 7, it is possible to obtain an accurate value of the propagation delay time.

After calculating the propagation delay time of each signal line, the circuit simulation unit 18 refers to the component file 11 and the netlist file I7 and performs circuit simulation according to the test vector. This test vector is DUM
It includes content that causes a dummy symbol defined by a character string containing MY to apparently work better. However, since the dummy symbol (in this example, the dummy symbol defined by DUMMY#20) has no logical function and is meaningless, it will not have the same negative effect on the simulation results of other circuit parts. . In addition, the test vector described in -1- is set so that any input or output of the dummy symbol is assumed to be correct so that the operation of the dummy symbol is not treated as an error. . Therefore, even if the netlist file 17 is used to indicate the wiring fit of components that are not actually mounted, a correct circuit simulation can be performed.

[Effects of the Invention] As detailed above, according to the present invention, the following effects can be achieved.

■ Instructions for wiring holes for components that are not actually mounted on the board to the ground, power supply, etc. can be made on the netlist, so it is possible to reduce instruction errors, design errors, manufacturing errors, etc.

■ Among the components registered in the netlist, specific symbols (dummy symbols) are assigned to components that are not actually mounted on the board (dummy components) so that they can be identified. Even if the dummy parts are apparently operated well, the circuit/simulation can be performed assuming that the dummy parts are logically non-functional, so that an iE L circuit simulation can be performed.

■ We identify whether or not a dummy component is a dummy component by checking whether the dummy symbol is empty, and only components that are not dummy components (i.e., components that are actually mounted on the board) are set in the component list, so we manage component purchasing. It is possible to correctly calculate the manufacturing cost of a board, etc.

[Brief explanation of the drawing]

FIG. 1 is a functional block configuration diagram of a CAD system for logical drawings according to an embodiment of the present invention, and FIG. 2 is a diagram showing an example of a logical drawing near a dummy symbol included in the logical drawing file 13 of FIG. 1. FIG. 3 is a diagram showing the list portion of the dummy symbols included in the netlist file 17 of FIG. 1, and FIG. 4 is a diagram showing the wiring state of the wiring hole of the dummy symbol on the board. . 11...Parts file, 12...Parts file creation J
13... Logical drawing file, 14... Logical drawing file creation section, 15... Parts list file, 1
6... Parts list creation section, 17... Netlist file, 18... Netlist file creation section, 19
...(Route 111 Simulation Department. Applicant's representative Patent attorney Takehiko Suzue)

Claims (1)

[Claims] In a logic drawing CAD system applied to board wiring, the board A specific component symbol that is distinguishable from other components actually mounted on the board and is logically completely non-functional is assigned to the board, including the dummy component to which this specific component symbol is assigned, and A component file generation means for generating a component file in which component information regarding various components constituting a logic circuit realized by the above is registered, and a position indicating the placement position of the component file and each component generated by the component file generation means. a logical drawing in which logical drawing information regarding the above-mentioned logic circuit realized by interconnecting the components in the above-mentioned component file is stored based on logic drawing creation information including information and instruction information for signal connections between each component; A logical drawing file generating means that generates a file; Based on the logical drawing file generated by the logical drawing file generating means, a list of parts actually mounted on the board is generated according to the presence or absence of the specific symbol. a parts list generating means to generate, and a list showing, in a list format, the connection states of signal lines between various components that constitute the logic circuit realized on the board, including the dummy parts, based on the logic drawing file. a netlist generation means for generating a netlist; a dummy component to which the specific symbol is assigned is apparently operated based on the netlist and the component file generated by the netlist generation means;
A CAD system for logical drawings, comprising: circuit simulation means for performing a circuit simulation assuming that the dummy component is logically non-functional.