JPS59125469A - Automatic designing device of printed board - Google Patents

Abstract

PURPOSE:To decrease the quantity of input information and to reduce both labor and time by attaining the reuse of a general-purpose circuit, a circuit having a high emerging frequency, etc. after registering them. CONSTITUTION:An automatic designing device for printed base board contains a central processing unit CPU10. The CPU10 includes a part file 11 and a cell file 12 as external memories and is connected to a console 13 functioning as an input/output device, an X-Y plotter 17 for final designed result and a printer which delivers said result in the form of a data. The general-purpose parts and circuits are registered to the files 11 and 12 together with parts and circuits having high emerging frequencies. These parts and circuits are reused when necessary.

Description

DETAILED DESCRIPTION OF THE INVENTION Background of the Invention The present invention provides an automatic printed circuit board design device, and more specifically, an automatic printed circuit board design device that automatically selects components, circuits, etc. to be assembled on a printed circuit board based on input information provided. Relates to devices for arranging and wiring.

The assembly of electric circuits with predetermined functions onto printed circuit boards is achieved not by the combination of individual circuit elements such as transistors and resistors, but by the combination of ICs in which multiple circuit elements or logic circuits are integrated on one chip. It is often done. Generally, one chip tC includes a plurality of unit circuits, for example, a certain IC includes four AND gates.

Therefore, designed electric circuits such as AND games and O
The logic circuit consisting of the combinatorial power of R gates is actually an IC
In many cases, the circuits assembled using this method and their layout have changed significantly. However, when designing a predetermined circuit to be assembled on a printed circuit board using a conventional automatic design device, not only the circuit configuration but also the number of all parts (IC etc.) to be used, The product name and wiring information had to be provided as input information. This work requires a lot of effort, and since there is a large amount of input information, input errors are likely to occur, which poses the problem that a complete designed wiring pattern is not output. Furthermore, since the device connects all the given parts in the given manner, if there are many parts, the number of connections also increases, which increases the processing time and costs.

Summary of the Invention The present invention aims to reduce the amount of input information for automatic design as much as possible to reduce labor and time, eliminate input errors, and reduce the processing time of the device. The purpose is to provide an automatic circuit board design device.

The automatic printed circuit board design device according to the present invention has a means for registering in advance a designed wiring pattern of a reusable circuit composed of a plurality of parts, a means for registering in advance a designed wiring pattern of a reusable circuit composed of a plurality of parts, a method for registering in advance the types of reusable circuits and unit circuits constituting an electric circuit to be designed, Means for inputting wiring data; means for selecting components for realizing a unit circuit based on input data about their types; means for connecting the selected components with each other and between the components and the reusable circuit based on the input wiring data. , and a means for outputting a wiring pattern of the connected components and the reused circuit.

According to this invention, designed wiring patterns for general-purpose circuits and circuits that appear frequently are registered in advance as reusable circuits, so when automatically designing printed circuit boards, it is only necessary to input the registration number. , the number of input data can be significantly reduced, the labor and time required for this can be reduced, and the possibility of input errors is also greatly reduced. In addition, regarding the internal operation of the automatic design equipment, since the design of reusable circuits has been completed, it is only necessary to connect the input/output lines between the reusable circuits and other circuits, which significantly reduces processing time. It is shortened to . Furthermore, once a wiring pattern is registered, the same circuit can be used any number of times, so for circuits whose performance changes due to stray capacitance of the wiring pattern, etc., it is possible to use stable circuits with constant performance. can.

DESCRIPTION OF THE EMBODIMENTS FIG. 1 shows the entire system of an automatic printed circuit board design apparatus. The automatic design device is a central processing unit (CPU)
(10), and this CPU (10) stores a component file (11) and a hill file (12) as external memory.
It is equipped with Also connected to the CPU (10) are a console (13) as an input/output device, an X-Y plotter (11) for plotting the designed final result, and a printer (not shown) for outputting data. ing. The console (13) has a keyboard (14)
, a CRT display (15), and a digitizer (16) for inputting position coordinates.

An example of the arrangement of keys J3 on the keyboard (14) is shown in FIG. The keyboard (14) is provided with numeric keys and various function keys.

The operating modes of the automatic KQ il device include cell registration processing and automatic printed circuit board design processing. Cell registration processing is a basic circuit that can be used frequently (reused circuit).
(This is called a cell) is configured in advance using a plurality of parts (IC chips), that is, arranged and connected, and the name of the parts, number of parts, and connection information are stored in a cell file (12). Automatic printed circuit board design processing is the process of assembling a printed circuit board on a printed circuit board based on the given printed circuit board design input information using various parts in the parts file (11) and necessary cells in the cell file (12). This refers to the process of configuring, ie arranging, and connecting circuits. Since the cell configuration has already been created in the cell registration process, it is only necessary to combine cells with each other or cells with other parts in this automatic design process.

Cell registration process First, the cell registration process will be explained in detail.

FIG. 3 shows the two-to-one area within the cPU (10) during cell registration processing.

The working area is provided with various areas and buffers. Each of these areas and buffers will become clear in the operational description.

Figure 4 shows an overview of the cell registration process, which includes circuit diagram input (step (111)), automatic component placement (step (112)), and automatic placement M (step (111)).
) and cell file creation (step (11)
It consists of 4 steps: /l)). Details of each of these steps are shown in FIG.

An example of a hill to be created is shown in FIG. This circuit consists of one NANO group (G1), AND
Consists of a gate (G2) and an OR gate (G3), five input terminals IN1 to IN5 and one output terminal 0U
T1. Since the gate (G1) is a NAND gate with two inputs, it is called a 2NAND gate. Other gates are called in a similar manner. In step (1i1) of FIG. 4, information on this circuit diagram is entered using the keyboard (14) and digitizer (16).

Referring to FIG. 5a, first, in order to input the gate (G1), use the numeric key of the keyboard (14) to input 2NAND.
When 2 of 2 is input manually (Stetsu 7 (121)), ko (1) input data 2 is input to the working area of CPU (10).
It is stored in the numeral part of the input buffer of the arear (FIG. 3) (step (122)). Next, when the NAND key of the seven action keys on the keyboard (14) is pressed (step (123)), this data is similarly stored in the function section of the input buffer (step <131>>. (G1)
The coordinates of the reference point (A) (see Figure 6) on the arrangement of are specified on the digitizer (16) and the digitizer switch (
SW) (path shown) is turned on (step (132)
). Then, the designated coordinate data (12, 11) is stored at the location designated by the input buffer data r2NANDJ in the gate position area in the working area (see FIG. 3). When the END key is pressed (step (134)), the incoming cover sofa is cleared (step (135)).

Data 2 that similarly specifies gates (G2) (G3)
AND, , 3OR and the coordinates of their reference points (B) and (C) are input and stored in the gate position area in the working area (display tab (121) (122
) (124) (125) (131) ~ (135
) ).

When input of gate information is completed, input of wiring information is next performed. The wiring is a line that connects gates as shown by LINEloo in FIG. First, when a wiring number (for example, 100) is input, this is stored in the input buffer's numeral field (step (121) (1
22) ), when the LINE key is pressed, this data is stored in the function section (step (126) (
731) ). The coordinates of one @ (point A) of this LINE are specified by the digitizer (16) and its SW is turned on, so that the specified coordinates (12, 11>) are input into the wiring information area in the working area. )] Stored in the location specified by the buffer data rLrNE100J (steps (132) (133)). Similarly, the coordinates of the other end (point D) of LINE 10'O are input and stored in the wiring information area. Finally, the END key is pressed and the input buffer is cleared (step (13)
4) (135) ). All other wiring information is entered in the same manner and stored in the wiring information area.

With this, the circuit diagram input operation in step (111) in FIG. 4 is completed.

The automatic component placement and automatic wiring processing in steps (112) and (113) in FIG. 4 are started by pressing the 5TART key. Referring to FIG. 5b, when the 5TART key is pressed (step (142)) , the number of gates to be used is determined for each gate type by referring to the data stored in the gate position area, and the result is stored in the gate position area of the working area (step (143)). .In this example, 2NAND, 2AN
There is one each of the three types of game 1-, D and 30R.

Next, the number of ICs to be used is calculated, and the result is
It is stored in the number area (step (144)).

IC means a component that is actually used. Normally, a single IC includes a plurality of gate circuits. For example, a 2NAND IC chip has four 2
NAND gates are integrated. Therefore, it is calculated how many ICs are required to implement each given type of gate. This calculation can be obtained for each type of gate by (number of rcs required) - (number of gates required)/(number of games built in one depth) (rounding up to the nearest whole number). The number of ICs determined in this way is stored in the number of ICs area of the working area. In this embodiment, each of the three types of gates is one piece, so the IC for each gate is also one piece.
Each piece is required. If there are four gates built into the IC, three of them will not be used.

The information stored in the gate position area A7 and the wiring information area in the working area A7 merely represents the position of each gate and each wiring. Therefore, from this information, it is unclear which wiring information directly indicates which wiring connects the input and output of which gate. Step (145) is a process for creating such connection information. In this process, the parts file (first part) is referred to.

In the component file (11), as shown in Figure 7, there are a logic gate file and an (IC>chip file.The logic gate file (11) contains the output terminals for each gate. The coordinates of the output terminal and input terminal are expressed based on the position (coordinates (0, 0>)).The chip file contains the name of the gate built in, the number of IC model name,
It stores the number of pins, type of bin, etc. 0 here
represents an output terminal, and I represents an input terminal.

First, based on the position coordinates (coordinates of the reference point, which represent the position of the output terminal as described above) stored in the gate position area V of each gate, the logic gate file is referred to, The coordinates of the input terminal of that gate are found.For example, the reference point (
Since the coordinates of B) are (22, 10), the logic gate
Referring to the file, the coordinates of the input terminals ((D), (E) points) of this 2AND gate (G2) are (18, 11)
(18,9). Next, it is checked whether the wiring information (coordinates of both ends of each LINE) in the wiring information area matches the coordinates of which input/output terminal of each gate calculated as described above. For example, LINEloo's (12,
The data 11>(ia, il) is 2NAND
(G1) output terminals (12, 11) and 2AND (G
Since it matches the input terminal (18, 11') of 2>, LI
It can be seen that NEloo connects the output of 2NAND and one input of 2AND. Such calculations are performed on all wiring information, and finally, wiring information as shown in FIG. 8 is obtained, and this is stored in the wiring information area in the working area. In Figure 8,
O represents an output terminal (output bin), and ■ represents an input terminal (input bin), respectively.

Next, based on the data in the IC number area, the necessary number of ICs to be used is arranged (step (
146) ). There are various possible placement methods, but -
An example is shown in FIG. In this example, each IC is assumed to have a certain size, and each IC is arranged with a certain interval between each IC. The coordinates of the reference bin of each IC (indicated by a black dot in FIG. 9, which is one bin of the IC) are determined in consideration of the number of bins of rC, the wiring pattern, etc. For example, in the case of a 14-bin IC, they are arranged at equal intervals such as 11 pitches in the X-axis direction and 7 pitches in the Y direction. Here, 1 pitch is the interval between IC bins. When the placement is completed, the chip file (
The coordinates of the input and output bins are divided by referring to the bin type data in FIG. The data is stored in the buffer.This completes the automatic placement process of step (112) in FIG.

Next, based on the connection information already created in the connection information area A7, the bin coordinates of the ICs arranged as described above are connected (step (147)).

The connected state is shown in FIG. Connections are shown as dashed lines. The symbol (OL) indicates the outer shape of the cell.

All connections are made in a straight line C and are turned at right angles if necessary (for example at the turning point (CL)). Additionally, coordinates that have already been used will not be used. The coordinates of the starting point, turning point, and destination point of each LINE are sequentially stored in the wiring pattern buffer (step (148)). The finally obtained wiring pattern is shown in FIG. Here, 5IZE indicates the size of the cell in coordinates.

(This is Step (+13)' in Figure 4).

Finally, the cell number (for example 001) is entered (5a
Figure step (121) (122) ), CELL
The 5th key is pressed in sequence.
Steps (141) (150) in Figure b, all the data in the working area (excluding the data in the input horn buffer) are transferred to the cell file (12),
stored (step (151)). Also PRIN
When the 'r key is pressed (step (149)), the created cell wiring pattern is output to the plotter (17) (step (152)) (step (11) in Figure 4).
4) ).

Printed Board Automatic Design Process Next, the process of assembling a predetermined circuit on a printed board using the information regarding the hills registered as described above will be described in detail.

Figure 12 shows the J3 output during automatic printed circuit board design processing.
A working area within the CPU (10) is shown.

The areas and types of buffers provided within this working area are the same as those shown in FIG.

However, in FIG. 12, there is an area A7 or buffer (-cell section) for already registered cells, and an area A7 or buffer (random gate section) for other gates (including flip-flops, etc.). and is provided.

FIG. 13 shows an outline of the automatic printed circuit board design process, which is also almost the same as the outline of the cell registration process shown in FIG. Some details of this automatic design process are shown in FIG.

Reference is also made to FIG. 5a if necessary.

FIG. 15 shows a circuit to be automatically designed. This electrical circuit consists of two flip 70 tubes (FF1) (FF2>
, one gate (G4) and already registered cell 20
Consists of 0. The reference point of each unit circuit is (F),
They are shown as (G), (H), and (J), respectively.

Type of gate (G4) and its position (reference point (H))
is entered in the same way as in the cell registration process. The flip-flop is input by pressing the FF key (step (127) in Figure 5a) and then specifying the coordinates of the reference points (F) and (G) using the digitizer (16). Figure 5a step (131)~
(135) ). These input data are
The data is stored in gate position area V (random gate section) within the area.

Information in cell 200 is entered as follows. Cell number 200 is input using the numeric keys (step <121>(122)> CrRCU I in Figure 5a).
The E key is pressed (step (222) in FIG. 14).

Then, the gate position, wiring information, number of gates, number of ICs, wiring information, and wiring pattern data regarding the already registered cell 200 are read out from the cell file (12), and the corresponding cell part in the working area is read out. are transferred all at once to (step (223)). Next, when the coordinates of the reference point (J) of this cell are specified by the gagetizer (16), these are read (step (224)
(225) ). Then, the coordinates of the opening gate position, wiring information, and connection information on the hill 200 transferred to the working area are
The coordinates are converted to coordinates based on the reference point (J) (step (226)). As a result, the relative positional relationship between each coordinate of the random gate section and the coordinates inside the cell 200 is unified, and these coordinates are expressed in one coordinate system.

Wiring information is entered in exactly the same manner as during hill registration.

Since the wiring information inside the cell 200 has already been registered, there is no need to input it, and here, wiring information between gates other than registered cells and wiring information between hills and gates are input. With this, the blueprint input process (step (211) in FIG. 13) is completed.

When the 5TART key is pressed (step (221)),
The number of gates in the random gate section is counted in the same way as when registering the cell (step (227)), and the total number with the already calculated number of gates in the cell section is calculated (step (227)).
228) ). Regarding the number of ICs to be used, the number of ICs in the random gate section and the number of ICs including the cell section are calculated in the same way (step (229) (2)
30)).

Next, connection information regarding the random gate section is calculated (step (231)). This is done by referring to the component file (11) in the same way as when registering the cell.

Connection information between registered cells and gates other than cells is also calculated. However, regarding the inside of the cell,
This process is unnecessary because the data read from the file (12>) and coordinate-transformed in step (226) can be used.An example of the created connection information is the 17th
As shown in the figure.

Cells and ICs are then placed (step (232)
) ). An example of this arrangement is shown in FIG. I
The C chips are arranged at regular intervals as in the case described above. It is not necessary to arrange the ICs inside the cell because they have already been created, and it is sufficient to arrange the ICs in units of cells so that there is an appropriate distance between the cell and other ICs. This completes the automatic placement process (step (212) in FIG. 13).

After this, the coordinates of the wiring pattern inside the cell (for example, the first
(Figure 1) is converted into coordinates with the reference position of the cell placed in step (232) added (the coordinates of the reference point of the cell wiring pattern at the time of cell registration are (0, 0>
) (step (233)'). This results in
The coordinates of the IC inside the cell are matched with the coordinates of the entire circuit of the printed circuit board to be created, that is, they are expressed in the same coordinate system.

Finally, all the cells and IC bins are connected to each other based on the connection information shown in FIG. 17, and the wiring pattern for the entire printed circuit board is created (step (2).
34) (213) ).

In this case, for each cell, only connections between the cell's person, output terminal, and other ICs are required, and connections inside the cell can be made using already created and registered connections. Therefore, processing time can be reduced.

After the arrangement and wiring are completed, a product number is assigned according to a certain rule (for example, right-aligned, left-aligned, etc.), and the final wiring pattern as shown in FIG. 18 is completed.

This wiring pattern is outputted by the X-Y plotter (17) - (step (214)').

Since the circuit registered as a cell can be used as a black box,
Placement and wiring time can be significantly reduced. In order to be less susceptible to the restrictions of the external shape of the printed circuit board, instead of registering only one type of cell, several types of cells such as vertically long, horizontally long, etc. can be registered. Furthermore, in order to shorten the wiring length, registering left-right symmetrical shapes of input/output signal lines is also a way to make the cell easier to use.

[Brief explanation of the drawing]

Figure 1 is a block diagram showing the entire automatic printed circuit board design device, Figure 2 is a diagram showing the keyboard, Figures 3 to 11 are diagrams showing hill registration processing, and Figure 3 is a working area. Figure 4 shows the flow chart showing the outline of the process.
Figure 5 is a flow chart showing the details of the process, Figure 6 is a diagram showing the circuit to be registered, Figure 7 is a diagram showing the contents of the component file, and Figure 8 is the details of the connection information area. Figure 9 shows the arrangement of tC, Figure 10 shows the wiring, Figure 11 shows the contents of the wiring pattern and buffer, and Figures 12 to 18 show the printed circuit. FIG. 12 is a diagram showing the working process V, FIG. 13 is a flow chart showing an overview of the process, and FIG. 14 is a flow chart showing details of the process. Figure 15 is a diagram showing the circuit to be designed, Figure 16 is a diagram showing the arrangement of ICs and cells, Figure 17 is a diagram showing the wiring information area, and Figure 18 is a diagram showing the wiring pattern buffer. be. (10)...CPU, (11)...Parts file,
(12)...Cell file, (13)...Console, (14)...Keyboard, (15)...CR
T, (16)...digitizer, (17)...X-
Y plotter. Patent applicant Tateishi Electric Co., Ltd. Figure 1'-13 Figure 2 Figure 5b Figure 7 Figure 8 Figure 11 Figure 13 Figure 14

Claims (1)

[Claims] Means for registering in advance a designed wiring pattern of a reusable circuit composed of a plurality of parts, types of reusable circuits a3 and unit circuits constituting an electrical circuit to be designed, and Means for inputting wiring data; Means for selecting components for realizing a unit circuit based on input data regarding their types; Means for connecting the selected components with each other and between the components and the reusable circuit based on the input wiring data. , and means for outputting wiring patterns of connected components and reusable circuits.