JP7244451B2 - Arithmetic device and method - Google Patents

Description

An embodiment of the present invention relates to simulation data, a computing method, and a computing device.

Power fluctuations in semiconductor devices such as LSIs (Large Scale Integrated circuits) are generally verified by performing simulations using specific operation patterns assuming worst cases. However, the characteristics obtained in the worst case with a low probability of occurrence have a large deviation from the characteristics during actual operation of the semiconductor device, and there is a possibility that the design will be of excessive quality.

JP 2017-10248 A

Accordingly, an embodiment of the present invention provides simulation data, a calculation method, and a calculation device that enable operation verification corresponding to the actual operation of a semiconductor device and appropriate circuit design.

In order to solve the above-described problems, according to an embodiment of the present invention, simulation data to be input to an arithmetic unit for executing simulation of a semiconductor device is part shape describing the shape and terminal information of the semiconductor device. information, element information describing connection information and terminal information of elements in the semiconductor device, and power supply model information modeling a power supply path of the semiconductor device, wherein the arithmetic unit receives the part shape information and , the element information and the power supply model information are associated with each other to provide simulation data used for executing the simulation of the semiconductor device.

FIG. 4 is a diagram showing simulation data according to one embodiment; 1 is a plan view showing an example of a semiconductor device; FIG. 1A and 1B are diagrams illustrating an example of an element in a semiconductor device; FIG. The figure which shows an example of a power supply model. The figure which shows typically the circuit produced|generated by the integrated file. The figure which shows the specific example of the data for simulation which are the contents of an integrated file. FIG. 4B is a diagram following FIG. 4A. FIG. 2 is a block diagram showing an example of the internal configuration of an arithmetic device; 4 is a flow chart showing an example of processing operation of an arithmetic device; FIG. 4 is a diagram showing an example of separating I/O elements in a semiconductor device from other elements; The figure which shows typically the circuit produced|generated by the integrated file. FIG. 9 is a diagram showing a specific example of simulation data that is the content of the integrated file corresponding to FIG. 8; The figure following FIG. 9A. FIG. 4 is a diagram schematically showing noise generated from a semiconductor device;

Embodiments of simulation data, a calculation method, and a calculation device will be described below with reference to the drawings. In the following, the main components of the simulation data, the calculation method, and the calculation device will be mainly described, but the simulation data, the calculation method, and the calculation device may include components and functions that are not illustrated or described. . The following description does not exclude components or features not shown or described.

FIG. 1 is a diagram showing simulation data 1 according to one embodiment. The simulation data 1 in FIG. 1 includes component shape information I1, element information I2, and power supply model information I3.

The component shape information I1 is information describing the shape and terminal information of the semiconductor device. Semiconductor devices include those that perform digital operations and those that perform analog operations, but the present embodiment is applicable to semiconductor devices that perform any operation. Here, the shape information is information representing the external shape of the semiconductor device, such as the size of the semiconductor device and the position information of the corners. The terminal information is information about the terminal names and terminal positions of the input terminals and output terminals of the semiconductor device.

FIG. 2A is a plan view showing an example of a semiconductor device 2 which is a component. Although FIG. 2A shows an example of a DIP (Dual In-line Package) type semiconductor device 2, the package shape of the semiconductor device 2 does not matter. For example, it is applicable to semiconductor devices 2 of arbitrary package shapes such as SIP (Single In-line Package), PGA (Pin Grid Array), SOP (Small Outline Package), and BGA (Ball Grid Array).

The element information I2 in FIG. 1 is information describing connection information and terminal information of elements in the semiconductor device 2 . The element can be any element in the semiconductor device 2 . Here, the connection information is information indicating the connection relationship between a certain element and another element in the semiconductor device 2 . As a more specific example, information indicating which terminal of a certain element is connected to which terminal of another element, or which input terminal or output terminal of the semiconductor device 2 each terminal of a certain element is connected to. information indicating whether the The terminal information is as described above.

FIG. 2B is a diagram showing an example of the element 3 in the semiconductor device 2. As shown in FIG. The elements 3 include those that are not connected to the output terminals of the semiconductor device 2 (elements 3A and 3B in FIG. 2B) and those that are connected to the output terminals (element 3C in FIG. 2B). As will be described later, it is possible to distinguish these elements 3, but first, an example of handling the elements 3 in the semiconductor device 2 without distinguishing them will be described.

The power supply model information I3 in FIG. 1 is information in which the power supply path of the semiconductor device 2 is modeled. More specifically, the power supply model information I3 is a power supply model equivalently representing the voltage applied between the power supply terminal and the ground terminal of the semiconductor device 2 and the current flowing between the power supply terminal and the ground terminal. information.

FIG. 2C is a diagram showing an example of a power supply model. As shown in FIG. 2C, the equivalent circuit 4 of the power supply model includes a current source 5, a series circuit 6 of resistors and capacitors, and a circuit 7 having resistors, inductors and capacitors. Note that the equivalent circuit 4 of the power supply model is not limited to that shown in FIG. 2C.

The simulation data 1 in FIG. 1 can be saved in one file (hereinafter also referred to as an integrated file). This file is generated in a form that can be interpreted and executed by a computer. This file may also be made available for download, for example, from a particular website. The downloaded file can be interpreted and executed by the computer at the download destination. By executing the simulation data in the integrated file, the computer can generate a circuit and perform operation verification (simulation) of the generated circuit. Instead of using a computer, the simulation may be performed by inputting the integrated file to a dedicated simulator. In this specification, computers and the like that interpret and execute integrated files are collectively referred to as arithmetic units.

FIG. 3 is a schematic diagram of a circuit generated by an integrated file. In the example of FIG. 3, the semiconductor device 2 has input terminals IN1 to IN4, a power supply terminal VDD, a ground terminal GND1, a ground terminal GND2, and an output terminal OUT. Among them, the input terminals IN1 and IN2 are connected to the element 3A, the input terminals IN3 and IN4 are connected to the element 3B, the output terminal OUT is connected to the element 3C, and the power supply terminal VDD and the ground terminal GND1 are equivalent circuits of the power supply model. 4 is connected. The power supply terminal of the element 3C is connected to the equivalent circuit 4 of the power supply model, and the ground terminal of the element 3C is connected to the ground terminal GND2. Furthermore, the output terminals of the elements 3A and 3B are connected to the input terminal of the element 3C. Thus, the circuit of FIG. 3 can be generated by executing the integrated file on the arithmetic device.

4A and 4B are diagrams showing specific examples of the simulation data 1, which are the contents of the integrated file corresponding to FIG. Simulation data 1 in FIGS. 4A and 4B shows a description example of a circuit inside the semiconductor device 2 shown in FIG. The simulation data 1 in FIGS. 4A and 4B is text information in ASCII code, and includes component shape information I1, element information I2, and power source model information I3. In the examples of FIGS. 4A and 4B, the component shape information I1, the element information I2, and the power supply model information I3 are described in this order, but the order in which each information is described is arbitrary.

The component shape information I1 in FIGS. 4A and 4B has a row Ln1 describing the coordinates of the external shape of the component and a row group Ln2 describing the identification information and coordinates of the terminals T1 to T8 of the component. As shown in FIGS. 4A and 4B, each terminal T1-T8 of the component has a predetermined length and width, and row Ln2 describes the center coordinates of the area of each terminal T1-T8.

The element information I2 in FIGS. 4A and 4B is described in order for the elements 3A, 3B, and 3C. The first line of the element information I2 (line group Ln3) of the element 3A refers to the external file "LOGICA.vhd" describing the operation and connection information of the element 3A. From the second line onward, the correspondence information between the terminal information included in the part shape information I1 of the element 3A and the terminal information in the external file, and the name "LOGICAB_OUT" of the output terminal of the element 3A are described. For elements 3B and 3C (row groups Ln4 and Ln5), the external file name, terminal information, and output terminal information are described in the same order as for element 3A.

In the power supply model information I3 (line group Ln6) in FIGS. 4A and 4B, the first line refers to the external file "POWER.cpm" describing the connection information of the power supply model as shown in FIG. 2C. From the second line onward, terminal information included in the component shape information I1 of the power supply model, correspondence information with terminal information in the external file, and connection information to the power supply terminal of the element 3C are described.

The integrated file containing the simulation data 1 shown in FIGS. 4A and 4B may be stored in a storage unit (not shown) as necessary. The simulation data 1 shown in FIGS. 4A and 4B are read by an arithmetic device such as a simulator, the contents of the integrated file are interpreted, and the simulation is executed.

FIG. 5 is a block diagram showing an example of the internal configuration of the arithmetic device 10. As shown in FIG. 5 includes an input unit 11, a component information storage unit 12, an element model storage unit 13, a power supply model storage unit 14, an execution unit 15, an output unit 16, and a verification unit 17. ing. The arithmetic device 10 in FIG. 5 executes simulation of the semiconductor device 2 . Arithmetic unit 10 uses simulation data 1 to associate component shape information I1, element information I2, and power supply model information I3 and execute simulation of semiconductor device 2 .

The input unit 11 inputs the integrated file shown in FIG. The operator may input the integrated file of FIG. 3 using a keyboard or the like. Alternatively, the integrated file may be electronically captured via the input unit 11 from an electrical device having a communication function.

The parts information storage unit 12 stores various parts information. The component information is information such as the external shape, size, number of terminals, and terminal position of the component, as shown in FIG. 2A.

The element model storage unit 13 stores an external file described in the element information I2 in the simulation data 1. FIG. Note that the element model storage unit 13 may not be provided when the connection information and operation of the element 3 are described directly in the element information I2 without referring to the external file.

The power supply model storage unit 14 stores external files described in the power supply model information I3 in the simulation data 1 . It should be noted that the power supply model storage unit 14 may not be provided if the connection information and operation of the power supply model are described directly in the power supply model information I3 without referring to an external file.

The execution unit 15 reads and interprets the component shape information I1, the element information I2, and the power supply model information I3 described in the input integrated file, and based on the component shape information I1, the element information I2, and the power supply model information I3, Generate a circuit and run a simulation based on the generated circuit.

As will be described later, the simulations performed by the execution unit 15 include a plurality of simulations such as circuit simulations, electromagnetic field simulations, and temperature simulations. Although an example in which the same execution unit 15 performs a plurality of simulations is shown in this specification, a plurality of arithmetic units 10 (simulators) may perform separate simulations.

The output unit 16 outputs the result of the simulation executed by the execution unit 15. FIG. The output format of the simulation results is arbitrary.

The verification unit 17 verifies whether or not the circuit or layout arrangement generated based on the integrated file is valid based on the simulation result output from the output unit 16, and if not valid, changes the circuit or layout arrangement. to direct.

FIG. 6 is a flow chart showing an example of the processing operation of the arithmetic unit 10. As shown in FIG. First, an integrated file is input through the input unit 11 (step S1). Next, the execution unit 15 reads and interprets the integrated file, and generates a simulation target circuit based on the component shape information I1, the element information I2, and the power supply model information I3 (step S2). The generated simulation target circuit is output from the output unit 16 .

Next, the execution unit 15 and the verification unit 17 use a circuit simulator to verify the operation of the simulation target circuit (step S3). Next, the verification unit 17 determines whether or not there is a problem in the operation of the circuit to be simulated based on the simulation result of the circuit simulator (step S4). If there is a problem with the operation, the processing after step S2 is repeated. In some cases, when it is determined that there is a problem in step S4, a new integrated file may be input again. In this case, the processing after step S1 is repeated.

If it is determined in step S4 that there is no problem in operation, layout placement is performed based on the simulation target circuit whose operation has been verified (step S5). The arithmetic device 10 according to the present embodiment can also perform layout arrangement, but the processing after step S5 may be performed by another arithmetic device 10 or the like. Alternatively, the arithmetic device 10 according to the present embodiment may request another device that performs layout arrangement to perform the layout arrangement process, receive the layout arrangement result, and perform the processes after step S5.

Next, the arithmetic device 10 performs an electromagnetic field simulation based on the layout arrangement result (step S6). Next, it is determined whether or not there is a problem in the result of the electromagnetic field simulation (step S7). For example, when it is determined by electromagnetic field simulation that EMI (Electro Magnetic Interference) noise generated from a part of the layout area of the semiconductor device exceeds a predetermined threshold, it is determined that there is a problem.

If it is determined in step S7 that there is a problem, it is determined whether or not to change the layout (step S8). If it is determined that the layout is to be changed, the processes after step S5 are repeated. On the other hand, if it is determined that the problem in step S7 cannot be solved by changing the layout, for example, the processes after step S2 are repeated.

If it is determined in step S7 that there is no problem, the layout arrangement result in step S5 is output via the output section 16 (step S9).

In FIGS. 3, 4A, and 4B, the element information I2 is described without distinguishing the elements 3 in the semiconductor device 2. However, in the semiconductor device 2, the elements 3 connected to the terminals of the semiconductor device 2 and an element 3 that is not connected to a terminal of the semiconductor device 2 but is connected to an internal node of the semiconductor device 2 . In particular, the element 3 connected to the output terminal of the semiconductor device 2 has a large influence of noise and the like to the outside of the semiconductor device 2 . Therefore, as shown in FIG. 7, the element 3 connected to the output terminal of the semiconductor device 2 may be treated as an I/O element 3D, distinguishing it from the other elements 3. FIG.

In this case, the element information I2 consists of I/O model information (hereinafter referred to as first model information) I4 relating to the I/O element 3D (first element) and elements 3 other than the I/O element 3D (second element ) (hereinafter referred to as second model information) I5. The first model information is information describing the operation of the I/O element 3D (first element) connected to the terminal of the semiconductor device 2 . The second model information I5 is information describing the operation of the elements 3 (second elements) other than the I/O element 3D in the semiconductor device 2. FIG.

FIG. 8 is a diagram schematically showing a circuit generated by an integrated file when the element information I2 is divided into first model information and second model information. The difference from FIG. 3 is that the I/O element 3D connected to the output terminal of the semiconductor device 2 is distinguished from the other elements 3, and the circuit configuration inside the semiconductor device 2 is the same.

9A and 9B are diagrams showing specific examples of the simulation data 1, which are the contents of the integrated file corresponding to FIG. The simulation data 1 in FIGS. 9A and 9B has component shape information I1, second model information, power supply model information I3, and first model information. The description order of each information is arbitrary.

Since the component shape information I1 and the power supply model information I3 are the same as those in FIGS. 4A and 4B, their description is omitted. The second model information is information (row group Ln3) on elements 3 (second elements) other than the I/O element 3D in the semiconductor device 2, and the first line describes the operation and connection information of the second elements. Referencing the external file "LOGIC.vhd". From the second line onwards, correspondence information between the terminal information included in the component shape information I1 of the second element and the terminal information in the external file is described.

The first model information (I/O model information) I4 is information (row group Ln5) on the I/O element 3D (first element) in the semiconductor device 2, and the first row indicates the operation of the I/O element 3D. And refer to the external file "IO.sp" that describes the connection information. From the second line onwards, correspondence information between the terminal information included in the component shape information I1 of the I/O element 3D and the terminal information in the external file is described.

In this embodiment, the semiconductor device 2 is simulated based on the component shape information I1, the element information I2, and the power supply model information I3. Power supply noise generated from can be verified.

FIG. 10 is a diagram schematically showing noise generated from the semiconductor device 2. As shown in FIG. The signal level of the I/O element 3D connected to the output terminal of the semiconductor device 2 changes depending on the logic of the output signal of the element 3 in the preceding stage, and the current flowing through the power supply path of the I/O element 3D also changes. . Therefore, by verifying the output voltage of the I/O element 3D connected to the output terminal of the semiconductor device 2 and the current flowing through the power supply path of the I/O element 3D, power supply noise generated from the semiconductor device 2 can be accurately detected. can guess.

Conventionally, it was only possible to verify the power supply noise in a specific operation of the semiconductor device 2, but according to this embodiment, the I/ Since the voltage of the output terminal of the O element 3D and the current flowing through the power supply path of the I/O element 3D can be verified, the power supply noise generated from the semiconductor device 2 can be estimated with high accuracy, and based on the estimation result, It is also possible to review the circuit configuration and element arrangement in the semiconductor device 2 .

Further, according to this embodiment, the signal delay amount can be predicted when the voltage output from the I/O element 3D is different from the original voltage level. By reflecting the prediction result of the signal delay amount in the circuit simulation, the circuit simulation can be performed in consideration of the signal delay amount, the simulation result close to the actual operation can be obtained, and the simulation accuracy can be improved. In addition, by reviewing the circuit configuration and layout arrangement based on the simulation results that take into consideration the amount of signal delay, the semiconductor device 2 suitable for actual use can be designed.

Furthermore, according to this embodiment, the power consumption of the semiconductor device 2 can be estimated from the voltage level and voltage fluctuations output from the I/O element 3D. That is, when the voltage fluctuation of the signal output from the I/O element 3D is large, the power consumption increases, so it is possible to verify whether or not the power consumption is within the previously assumed range. A semiconductor device 2 with low power consumption can be designed by reviewing the circuit configuration and layout arrangement based on the estimated power consumption.

The simulation data 1 in FIG. 1 described above may be data in the form of a program executable by the arithmetic device 10 . That is, the simulation data 1 of FIG. 1 may be described in the form of a program in which the component shape information I1, the element information I2, and the power supply model information I3 are set as separate parameters. More specifically, this program describes one or more functions that can be executed by the arithmetic unit 10, and the component shape information I1, the element information I2, and the power supply model information I3 are given as arguments of this function. may be

At least part of the arithmetic device 10 described in the above embodiments may be configured by hardware or may be configured by software. When configured with software, a program that implements at least part of the functions of the arithmetic device 10 may be stored in a recording medium such as a flexible disk or CD-ROM, and read and executed by a computer. The recording medium is not limited to a detachable one such as a magnetic disk or an optical disk, and may be a fixed recording medium such as a hard disk device or memory.

Also, a program that implements at least part of the functions of the computing device 10 may be distributed via a communication line (including wireless communication) such as the Internet. Furthermore, the program may be encrypted, modulated, or compressed and distributed via a wired line or wireless line such as the Internet, or stored in a recording medium and distributed.

Aspects of the present disclosure are not limited to the individual embodiments described above, but include various modifications that can be conceived by those skilled in the art, and the effects of the present disclosure are not limited to the above-described contents. That is, various additions, changes, and partial deletions are possible without departing from the conceptual idea and spirit of the present disclosure derived from the content defined in the claims and equivalents thereof.

1 simulation data, 2 semiconductor device, 3, 3A, 3B, 3C, 3D element, 11 input unit, 12 component information storage unit, 13 element model storage unit, 14 power supply model storage unit, 15 execution unit, 16 output unit, 17 verification unit, I1 part shape information, I2 element information, I3 power supply model information

Claims (14)

Component shape information describing the shape and terminal information of a semiconductor device, element information describing connection information and terminal information of elements in the semiconductor device, and power supply model information modeling the power supply path of the semiconductor device. an input unit for inputting simulation data including
an execution unit that associates the component shape information, the element information, and the power supply model information and executes a simulation of the semiconductor device;
a verification unit that verifies power supply noise generated from a power supply device and a ground terminal of the semiconductor device during execution of the simulation of the semiconductor device by the execution unit;
the element information includes first model information describing the operation of a first element connected to an output terminal of the semiconductor device;
The arithmetic device, wherein the verification unit verifies at least one of the output voltage of the first element obtained by the simulation by the execution unit and the current flowing through the power supply path of the first element. The power supply model information is power supply model information equivalently representing a voltage applied between a power supply terminal and a ground terminal of the semiconductor device and a current flowing between the power supply terminal and the ground terminal. 2. The computing device of claim 1, wherein: 3. The arithmetic device according to claim 2, wherein said element information includes connection information between a power supply terminal of said element and said power supply model. 4. The arithmetic device according to claim 1, wherein said element information includes connection information between terminals of said element and terminals of said semiconductor device. 4. The arithmetic device according to claim 1, wherein said element information includes connection information between a plurality of elements in said semiconductor device. 6. The arithmetic device according to claim 1, wherein said element information further includes second model information describing operation of a second element other than said first element in said semiconductor device. the first model information includes connection information of the first element and operation information of the first element;
7. The arithmetic device according to claim 6, wherein said second model information includes connection information of said second element and operation information of said second element. 8. The arithmetic device according to claim 1, wherein said first model information includes connection information of a power supply path of said first element. 9. The arithmetic device according to claim 1 , wherein said first model information includes connection information between a power supply model included in said power supply model information and a power supply terminal of said first element. 10. The arithmetic device according to claim 1, wherein said component shape information includes information defining an outer shape of said semiconductor device. 11. The arithmetic device according to claim 10, wherein said part shape information includes position information of corners of said semiconductor device. 12. The arithmetic device according to claim 1, wherein said component shape information includes position information of terminals of said semiconductor device. 13. The component shape information, the element information, and the power supply model information according to claim 1, wherein the information is described in a format interpreted and executed by an arithmetic unit that executes simulation of the semiconductor device. computing device . Input simulation data including component shape information describing the shape and terminal information of a semiconductor device, element information describing connection information and terminal information of elements in the semiconductor device, and power supply model information of the semiconductor device death,
executing a simulation of the semiconductor device by associating the component shape information, the element information, and the power supply model information;
verifying power supply noise generated from a power supply and a ground terminal of the semiconductor device during execution of the simulation of the semiconductor device;
the element information includes first model information describing the operation of a first element connected to an output terminal of the semiconductor device;
A calculation method for verifying at least one of an output voltage of the first element and a current flowing through a power supply path of the first element obtained by simulation of the semiconductor device.

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