JP2010134775A - Method, program and apparatus for simulating circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a circuit simulation method for accurately and easily conducting circuit simulations for the variation of element characteristics according to the locations of elements. <P>SOLUTION: A circuit simulation apparatus 1 includes a symbol library 11 for storing symbols of elements used in the circuit design of an integrated circuit, and a SPICE (Simulation Program with Circuit Emphasis) model storage unit 13 for storing a SPICE model. Position information about the locations of the elements is set for the symbols of the elements. Circuit simulation of the integrated circuit is conducted using a model parameter of the SPICE model for which a variable corresponding to each element's position information is set, and the position information set for each symbol. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a circuit simulation method, a circuit simulation program, and a circuit simulation apparatus.

  In recent years, a highly accurate integrated circuit has been designed using a circuit simulator (circuit simulation apparatus) having various analysis functions. As one of circuit analysis methods, there is variation analysis for examining the influence of element process variations. For this variation analysis, two types of analysis methods are mainly used: corner analysis and Monte Carlo analysis.

  Corner analysis is a method in which model parameters (a plurality of variation conditions) reflecting the degree of process variation are prepared, and one variation condition is selected from the prepared variation conditions to execute circuit simulation. The designer performs circuit simulation under various conditions by switching selection switches called model parameter sections.

  The Monte Carlo analysis is a method of statistically analyzing the result of executing circuit simulation using a condition obtained by adding random fluctuation to some of circuit parameters many times. In this Monte Carlo analysis, random fluctuations are added to predetermined ones of model parameters in order to analyze variations in elements. Thereby, the designer can estimate the influence of the process variation with reference to the statistically processed result.

  In these variations analysis, it was impossible to analyze the layout dependence of the characteristic variation of the element. For example, in order to make the characteristics of the elements the same, the effects of the countermeasures on the layout cannot be analyzed when the arrangement directions of the elements are aligned or arranged close to each other.

  Therefore, in the variation analysis method described in Patent Document 1, a circuit simulation is executed after calculating position-dependent variation amounts of characteristics and shapes from element position information and correcting circuit information.

  However, the above-described conventional technique has a problem that it takes time and effort to execute the simulation because the position-dependent variation amount of the characteristics and shape must be calculated before the simulation is executed.

JP 2007-213134 A

  It is an object of the present invention to obtain a circuit simulation method, a circuit simulation program, and a circuit simulation apparatus that perform circuit simulation accurately and easily for variations in element characteristics according to element arrangement positions.

According to one aspect of the present invention, a position information setting step for setting position information related to the arrangement position of the element is set in a symbol of the element used when designing an integrated circuit, and a variable corresponding to the position information of the element is set. There is provided a circuit simulation method including a simulation step of performing a circuit simulation of the integrated circuit using the model parameter of the element and the position information set in the symbol.
Further, according to one aspect of the present invention, a position information setting unit that sets position information related to an arrangement position of the element in a symbol of the element used when designing a circuit of the integrated circuit, and a variable corresponding to the position information of the element There is provided a circuit simulation apparatus comprising: a simulation unit that performs a circuit simulation of the integrated circuit using a model parameter of the element for which the parameter is set and position information set for the symbol. .

  According to the present invention, it is possible to accurately and easily perform circuit simulation of variations in element characteristics according to the arrangement position of elements.

  Hereinafter, embodiments of a circuit simulation method, a circuit simulation program, and a circuit simulation apparatus according to the present invention will be described in detail with reference to the drawings. Note that the present invention is not limited to the embodiments.

(Embodiment)
FIG. 1 is a functional block diagram showing a configuration of a circuit simulation apparatus according to an embodiment of the present invention. The circuit simulation device 1 is a device that performs circuit simulation of an integrated circuit, and includes variable information of model parameters (condition files for simulating circuit characteristics) that are used when circuit simulation is performed on arrangement information of elements constituting the integrated circuit. And circuit simulation. The circuit simulation apparatus 1 is incorporated in, for example, a CAD (Computer Aided Design) apparatus that designs an integrated circuit.

  The circuit simulation apparatus 1 includes a symbol library 11, a schematic data generation unit 12, a SPICE model storage unit 13, an analysis method setting unit 14, an instruction input unit 15, a layout data storage unit 16, an element recognition data generation unit 17, and a net list generation unit. 18, a circuit simulation processing unit 19, an analysis result output unit 20, and a control unit 21.

  The symbol library 11 is a memory that stores symbols of elements to be analyzed. The symbol of the element stored in the symbol library 11 is information used at the time of circuit design of the integrated circuit. The symbol arranged on the circuit diagram, various information about the element (property (attribute), model name, size, Process information).

  The schematic data generation unit 12 generates schematic data (schematic data) using the symbols stored in the symbol library 11. When predetermined instruction information is input from the instruction input unit 15, the schematic data generation unit 12 generates schematic data based on the instruction information. When the instruction information designating the element is input to the instruction input unit 15, the schematic data generation unit 12 extracts the symbol of the designated element from the symbol library 11. Further, when the instruction information specifying the element coordinate value is input to the instruction input unit 15, the schematic data generation unit 12 associates the specified coordinate value (position information) with the symbol of the element. Thus, in the present embodiment, information (coordinates) of the position where the element is arranged is associated with the symbol property. The schematic data generation unit 12 inputs the generated schematic data and a symbol in which element coordinate values are registered as properties to the net list creation unit 18.

  The SPICE model storage unit 13 is a memory that stores a SPICE (Simulation Program with Integrated Circuit Emphasis) model. The SPICE model is a model used in the SPICE simulation program, and includes SPICE parameters (model parameters) and the like. The model parameter of the present embodiment is configured to include a parameter having a coordinate value as a variable (a variable corresponding to position information), and the circuit simulation apparatus 1 uses the parameter having the coordinate value as a variable, the coordinate value, and the like. Then, the circuit simulation of the integrated circuit is performed.

  Based on the instruction information from the instruction input unit 15, the analysis method setting unit 14 sets either a circuit simulation using element coordinate values or a conventional circuit simulation as a circuit simulation method.

  The instruction input unit 15 inputs instruction information for specifying an element used for generating schematic data, instruction information for specifying a coordinate value of the element, instruction information for specifying the type of circuit simulation method, and the like. The layout data storage unit 16 is a memory that stores layout data of an integrated circuit used for circuit simulation.

  The element recognition data generation unit (design support apparatus) 17 performs element recognition using the layout data stored in the layout data storage unit 16. As element recognition, the element recognition data generation unit 17 extracts information about elements and wiring from layout data and generates Extracted data (element extraction drawing). The element recognition data generation unit 17 includes the coordinate value of each element in the element extraction drawing. The element recognition data generation unit 17 inputs the generated element extraction drawing to the net list generation unit 18.

  The net list creation unit 18 creates a net list using the schematic data generated by the schematic data generation unit 12 and the SPICE model in the SPICE model storage unit 13. A netlist is information about elements in an integrated circuit. In the netlist, information such as element name, element type, and element connection destination is associated with each element. When the element recognition data generation unit 17 inputs the element extraction drawing to the net list creation unit 18, the net list creation unit 18 creates a net list using the element extraction drawing.

  The circuit simulation processing unit 19 performs circuit simulation of the integrated circuit using the net list created by the net list creation unit 18. The net list includes element coordinate values and the like, and the circuit simulation processing unit 19 performs circuit simulation using the element coordinate values. When the analysis method setting unit 14 sets a predetermined circuit simulation method, the circuit simulation processing unit 19 performs circuit simulation of the integrated circuit by the set circuit simulation method.

  The analysis result output unit 20 displays or externally outputs the circuit simulation result by the circuit simulation processing unit 19. The control unit 21 includes a symbol library 11, a schematic data generation unit 12, a SPICE model storage unit 13, an analysis method setting unit 14, an instruction input unit 15, a layout data storage unit 16, an element recognition data generation unit 17, and a net list generation unit 18. The circuit simulation processing unit 19 and the analysis result output unit 20 are controlled.

  Note that the schematic data generation unit 12 and the element recognition data generation unit 17 of the circuit simulation apparatus 1 correspond to the position information setting unit described in the claims, and the net list creation unit 18 and the circuit simulation processing unit 19 claim. Corresponds to the simulation part described in the range.

  FIG. 2 is a diagram illustrating a hardware configuration of the circuit simulation apparatus according to the embodiment. The circuit simulation apparatus 1 includes a CPU (Central Processing Unit) 91, a ROM (Read Only Memory) 92, a RAM (Random Access Memory) 93, a display unit 94, and an input unit 95. In the circuit simulation device 1, the CPU 91, the ROM 92, the RAM 93, the display unit 94, and the input unit 95 are connected via a bus line.

  The CPU 91 performs circuit simulation of the integrated circuit using a circuit simulation program 97 which is a computer program for performing circuit simulation. The display unit 94 is a display device such as a liquid crystal monitor, and based on instructions from the CPU 91, various information (symbol, schematic data, SPICE model, layout data, element extraction drawing, netlist, Analysis method setting screen, circuit simulation result, etc.) are displayed. The input unit 95 includes a mouse and a keyboard, and inputs instruction information input from the user from the outside. The instruction information input to the input unit 95 is sent to the CPU 91.

  The circuit simulation program 97 is stored in the ROM 92 and loaded into the RAM 93 via the bus line. The CPU 91 executes a circuit simulation program 97 loaded in the RAM 93. Specifically, in the circuit simulation apparatus 1, the CPU 91 reads the circuit simulation program 97 from the ROM 92 and expands it in the program storage area in the RAM 93 in accordance with an instruction input from the input unit 95 by the user, and executes various processes. . The CPU 91 temporarily stores various data generated during the various processes in a data storage area formed in the RAM 93.

  The circuit simulation program 97 executed by the circuit simulation apparatus 1 according to the present embodiment includes the above-described units (symbol library 11, schematic data generation unit 12, SPICE model storage unit 13, analysis method setting unit 14, instruction input unit 15, The module configuration includes a layout data storage unit 16, an element recognition data generation unit 17, a net list creation unit 18, a circuit simulation processing unit 19, an analysis result output unit 20, and a control unit 21). The above-described units are generated on the main storage device.

  Note that the circuit simulation program 97 executed by the circuit simulation apparatus 1 of the present embodiment may be provided by being stored on a computer connected to a network such as the Internet and downloaded via the network. . Further, the circuit simulation program 97 executed by the circuit simulation apparatus 1 of the present embodiment may be configured to be provided or distributed via a network such as the Internet. Further, the circuit simulation program 97 of the present embodiment may be configured to be incorporated in advance in a ROM or the like and provided to the circuit simulation apparatus 1.

  Next, an operation procedure of the circuit simulation apparatus 1 according to the embodiment will be described. FIG. 3 is a flowchart showing an operation procedure of the circuit simulation apparatus. Element symbols are registered in advance in the symbol library 11, SPICE models are registered in the SPICE model storage unit 13, and layout data is registered in the layout data storage unit 16 (step S10). Based on the instruction information from the instruction input unit 15, the analysis method setting unit 14 sets a circuit simulation using element coordinate values or a conventional circuit simulation as a circuit simulation method. Here, a case where a circuit simulation (circuit simulation according to the embodiment) method using the coordinate values of the element is set in the analysis method setting unit 14 will be described.

  The circuit simulation apparatus 1 performs circuit simulation of the circuit 2 shown in FIG. 4, for example. FIG. 4 is a diagram illustrating an example of a circuit having a current mirror. The circuit simulation apparatus 1 analyzes the pair characteristics of the transistors constituting the current mirror using the circuit 2 in FIG.

  The circuit 2 includes a current mirror 25 and power supplies 31 to 33 connected to the output side of the current mirror 25. The circuit simulation apparatus 1 performs circuit simulation on the current values output from the terminals (Iout1, Iout2, Iout3) to the power supplies 31 to 33 using the coordinate values of the elements in the current mirror 25. FIG. 5 is a diagram illustrating an example of the configuration of the current mirror. As shown in the figure, the current mirror 25 includes a plurality of elements M0 to M5. And Iout1, Iout2, and Iout3 of the current mirror 25 are connected to the power supplies 31 to 33, respectively.

  The schematic data generation unit 12 refers to symbols in the symbol library 11 and generates schematic data (step S20). At this time, when instruction information for designating an element is input to the instruction input unit 15, the schematic data generation unit 12 extracts a symbol of the designated element from the symbol library 11. When the instruction information for specifying the coordinate value of the element is input from the instruction input unit 15 (Yes in step S30), the schematic data generation unit 12 associates the specified coordinate value with the symbol of the element (step S40). .

  Note that the schematic data generation unit 12 sets a default value (for example, x = 0, y = 0) as an element coordinate value in advance for each element, and associates the default value with the symbol of the element. Good. Further, the coordinate origin is set as a default value as the coordinate value of each element, and when the coordinate value of the element is input, the schematic data generation unit 12 may associate the designated coordinate value with the symbol of the element. Good. The schematic data generation unit 12 inputs the generated schematic data and symbols associated with element coordinate values to the net list creation unit 18.

  On the other hand, when the instruction information for designating the element and the instruction information for designating the coordinate value of the element are not input to the instruction input unit 15 (No in step S30), the layout data storage unit 16 stores the element recognition data generation unit 17. Element recognition is performed using the layout data. Specifically, the element recognition data generation unit 17 extracts element and wiring information (circuit elements and parasitic elements) from the layout data, generates an element extraction drawing, and corresponds the coordinate value of each element to the element extraction drawing. It is attached (step S50). As a result, it is possible to perform a circuit simulation more accurately than in the past in consideration of the influence of parasitics that depend on the layout pattern such as the influence of wiring.

  FIG. 6 is a diagram for explaining a method for generating an element recognition drawing using layout data. FIG. 6 shows a case where the current mirror 25 includes PMOSs 41 and 42 and NMOSs 51 to 54. Here, the PMOS 41 corresponds to the element M0, and the PMOS 42 corresponds to the element M1. Further, the NMOSs 51 to 54 here correspond to the elements M2 to M5, respectively.

  In the current mirror 25, for example, the NMOS 54 may be arranged separately from the NMOSs 51 to 53. A difference may occur in the output values (Iout1 to Iout3) from the current mirror 25 depending on the arrangement of each element. Therefore, the element recognition data generation unit 17 of the present embodiment extracts element and wiring information from the layout data of the current mirror 25 to generate an element extraction drawing, and each element (PMOS 41, 42, NMOS 51) is included in the element extraction drawing. To 54) are associated with each other. Thereby, when performing circuit simulation, it becomes possible to perform circuit simulation according to arrangement | positioning of each element.

  The net list creation unit 18 creates a net list by referring to the schematic data generated by the schematic data generation unit 12 and the SPICE model in the SPICE model storage unit 13. At this time, the net list creation unit 18 creates a net list by using the symbol or the element extraction drawing with which the coordinate value of the element is associated (step S60).

  The circuit simulation processing unit 19 performs circuit simulation of the integrated circuit using the net list created by the net list creation unit 18 (step S70). The analysis result output unit 20 displays a circuit simulation result by the circuit simulation processing unit 19 and the like.

  Here, a specific example of a symbol when the symbol of the element has the coordinate value of the element as a property will be described. FIG. 7 is a diagram illustrating an example of a net list generated from symbols having coordinate values. FIG. 7 shows a symbol example (symbol information 61) when the element is a MOS transistor. The element information represented by each row of the elements M0 to M5 in the symbol information 61 includes information on the connection destination, element model name, gate width (W), gate length (L), as well as element coordinate values (x and y). For example, the element M5 has a gate width (W) of 5 μm and a gate length (L) of 0.13 μm. Further, the element M5 has coordinate values of x = 111 μm and y = 68 μm.

  Although the case where the element is a MOS transistor is shown here as an example, the element may be another element such as a resistor or a capacitor. Also in this case, the element can be indicated by the same symbol as in the case where the element is a MOS transistor.

  Next, a specific example of the model parameter in the case where the parameter having the coordinate value of the element as a variable is given to the model parameter will be described. FIG. 8 is a diagram illustrating an example of a model parameter file when a model parameter is provided with a parameter whose element coordinate value is a variable. FIG. 8 shows a part of the model parameter file (model parameter file 62) when the parameter values belonging to the process parameters in the BSIM model of the MOS transistor have coordinate dependency.

  In the model parameter file 62, element coordinate information (x, y) and relative position variation variables (d_tox_xy, d_vth_xy, d_lint_xy) are defined in the part following parameters. The part following model indicates normal model parameters. Here, by adding a position variation variable to a parameter value belonging to a process parameter such as tox, the coordinate dependency can be analyzed by circuit simulation.

  For example, the parameter (variation value) indicating the oxide film thickness (d_tox_xy) of the MOS transistor when x = 0 and y = 0 is used as a reference value is 0.3E-9 * ((x * X) + (y * y)). Further, a parameter indicating the threshold voltage (d_vth0_xy) of the MOS transistor can be expressed by 0.1 * ((x * x) + (y * y)) or the like using the coordinate value of the element. Further, a parameter (d_lint_xy) for determining an effective channel length can be represented by 1.0E-08 * ((x * x) + (y * y)) using the element coordinate values.

  Therefore, the oxide film thickness (tox) of the MOS transistor can be expressed by 3E-9 + d_tox_xy or the like using (d_tox_xy). The threshold voltage (vth0) of the MOS transistor can be expressed by 0.1 + d_vth0_xy using (d_vth0_xy). The effective channel length (lint) can be represented by 1e-8 + _d_lint_xy using (d_lint_xy).

  As a result, for example, even when using a macro model with a parasitic capacitance in the resistor element model in order to increase the accuracy of circuit simulation, the coefficient for calculating the parasitic capacitance should be coordinate-dependent. Can do.

  Next, an analysis method setting screen in the case where a section for analyzing the coordinate dependency of an element (a part for designating the type of circuit simulation method) is provided in the model parameter will be described. The circuit simulation apparatus 1 according to the present embodiment is a display for selecting one of the circuit simulation methods from a plurality of types of circuit simulation methods such as corner analysis, Monte Carlo analysis, and analysis using element coordinates (position). The screen is displayed on the display unit 94. When an instruction to select an analysis method using the element coordinates is input from the instruction input unit 15, the circuit simulation device 1 executes the analysis method according to the present embodiment using the element coordinates. Specifically, the circuit simulation apparatus 1 performs circuit simulation by setting a variable (variable using the element coordinates) corresponding to the analysis method using the element coordinates as a model parameter.

  FIG. 9 is a diagram illustrating an example of a model parameter file when a model parameter is provided with a section for analyzing element coordinate dependency. FIG. 9 shows a part of a model parameter file (model parameter file 63) used for circuit simulation. The model parameter file 63 of the present embodiment has a plurality of sections with different parameter values in order to execute any one of corner analysis, Monte Carlo analysis, and analysis using element coordinates. For example, the analysis using element coordinates is associated with the section “xy”. When “xy” is input (selected) as a section, the circuit simulation apparatus 1 performs circuit simulation using the same parameter values as the parameters illustrated in FIG.

  The circuit simulation device 1 displays an element coordinate setting screen on the display unit 94 as necessary when performing a circuit simulation using the element coordinates. In other words, when a section name (analysis condition) indicating variation analysis according to the element coordinates is designated by the user, the display unit 94 displays the element coordinate setting screen. The element coordinate setting screen may be a screen for inputting element coordinates (x, y) or a screen for designating the arrangement of elements shown in FIG.

  Further, the circuit simulation apparatus 1 according to the present embodiment gives element coordinate values to element properties when extracting elements from layout data. FIG. 10 is a diagram illustrating an example of a screen (element coordinate display screen 71) when element coordinate values are extracted from layout data. When the element recognition data generation unit 17 performs element extraction from the layout data, the element recognition data generation unit 17 extracts the coordinate value of the element and associates the coordinate value with the element property. Conventionally, when performing element extraction, elements and property values of the elements are extracted from layout data. The circuit simulation device 1 according to the present embodiment extracts the coordinate values (x, y) at which the elements are arranged, together with the elements and the property values of the elements. Then, the circuit simulation device 1 registers the extracted coordinate value in the element property and displays it in the coordinate display areas 72 and 73 in the element coordinate display screen 71. Here, the case where the x coordinate of the element is displayed in the coordinate display area 72 and the y coordinate of the element is displayed in the coordinate display area 73 is shown. Note that, in the variation analysis of the present embodiment, one of the purposes is to evaluate the difference in circuit characteristics between a plurality of elements, so the coordinate values of the elements need to be absolute position information on the integrated circuit. Relative positional information between elements may be sufficient.

  As described above, in the present embodiment, a symbol of an element has the coordinate value of the element as a property. In addition, the model parameter has a parameter with the coordinate value of the element as a variable. The model parameter is provided with a section (parameter corresponding to the analysis condition) for analyzing the coordinate dependency of the element. Also, the element coordinates are extracted from the layout data, and the element coordinate values are assigned to the element properties.

  FIG. 11 is a diagram illustrating a result of circuit simulation using the coordinate values of the element. FIG. 11 shows the result of the circuit simulation when the coordinate value of the element of the circuit 2 shown in FIG. 4 is input from the instruction input unit 15. Here, the current value flowing to the power source 31 is i = 16.2 μA, the current value flowing to the power source 32 is i = 15.9 μA, and the current value flowing to the power source 33 is i = 114.4 μA. ing. As described above, even if an error occurs in the output value from the current mirror 25 due to the difference in the element arrangement position, the circuit simulation device 1 can perform the circuit simulation according to the element arrangement position. As a result, it is possible to analyze the influence of mismatch of element characteristics according to the arrangement position of the element.

  FIG. 12 is a diagram illustrating a result of circuit simulation using the element coordinates extracted from the layout data. FIG. 12 shows a circuit simulation result when the coordinate values of the elements of the circuit 2 shown in FIG. 4 are extracted from the layout data. Here, the current value flowing to the power source 31 is i = 113.8 μA, the current value flowing to the power source 32 is i = 12.7 μA, and the current value flowing to the power source 33 is i = 110.9 μA. ing.

  By the way, when the wiring parasitic of the element is extracted from the layout data and the circuit simulation is performed considering only the influence of the extracted wiring parasitic, the value of the current flowing to the power source 31 is i = 13.9 μA. The value of current flowing to the power supply 32 was i = 111.2 μA, and the value of current flowing to the power supply 33 was i = 12.7 μA.

  In the current mirror 25, the actual current value flowing to each of the power supplies 31 to 33 differs depending on the element arrangement coordinates. However, if circuit simulation (corner analysis) is performed on the current values flowing to the power supplies 31 to 33 while ignoring the influence of the element coordinate values and the wiring parasitics, the current values flowing to the power supplies 31 to 33 are the same. In other words, the current value flowing to each of the power supplies 31 to 33 is substantially the same unless the difference in the current value flowing to each of the power supplies 31 to 33 can be accurately simulated.

  For example, when a circuit simulation is performed in consideration of the influence of element wiring parasitics, the difference in current value flowing to each of the power supplies 31 to 33 is small. On the other hand, when the circuit simulation is performed in consideration of both the wiring parasitic and the influence of the element coordinates, the difference between the current values flowing to the power supplies 31 to 33 increases. Therefore, an accurate circuit simulation can be performed by performing the circuit simulation in consideration of the influence of the element coordinates. As described above, even when the coordinate values of the elements are extracted from the layout data, the circuit simulation device 1 can perform the circuit simulation according to the arrangement of the elements. Thereafter, an integrated circuit is designed in consideration of variations in element characteristics, and a semiconductor device is manufactured using the designed integrated circuit.

  As described above, the circuit simulation apparatus 1 introduces the arrangement information of the elements constituting the integrated circuit into the variable of the model parameter used in the circuit simulation. Thereby, it is possible to execute a circuit simulation in consideration of the position dependency of the element. In other words, it is possible to analyze the influence of element matching depending on the layout pattern that cannot be achieved by the conventional circuit simulation method. This makes it possible to analyze systematic variations having a predetermined tendency as variations in element characteristics. Further, by combining the analysis of this embodiment and the conventional Monte Carlo analysis, it becomes possible to analyze random variations more accurately than in the past.

  In the present embodiment, the case where the circuit simulation apparatus 1 includes the analysis method setting unit 14, the layout data storage unit 16, and the element recognition data generation unit 17 has been described. However, the circuit simulation apparatus 1 The analysis method setting unit 14, the layout data storage unit 16, and the element recognition data generation unit 17 may not be provided. When the circuit simulation apparatus 1 does not have the layout data storage unit 16 or the element recognition data generation unit 17, the circuit simulation of the integrated circuit is performed by inputting the element coordinate values from the instruction input unit 15. When the circuit simulation apparatus 1 does not have the analysis method setting unit 14, the circuit simulation apparatus 1 performs circuit simulation of the integrated circuit by an analysis method using the element coordinates.

  Further, in the present embodiment, a case has been described in which a plurality of output values are subjected to circuit simulation and each output value is compared, but one output value may be subjected to circuit simulation. Even in this case, an accurate circuit simulation according to the coordinates of the element can be performed.

  As described above, according to the embodiment, since the element arrangement position is introduced into the variable of the model parameter used in the circuit simulation, the variation of the element characteristic (circuit characteristic) according to the element arrangement position can be accurately and accurately determined. It becomes possible to analyze easily.

  In addition, since the current circuit simulation flow and the processing flow are the same, it is possible to easily perform circuit simulation using the current circuit simulation program.

  In addition, since the element coordinate values are extracted from the layout data and the circuit simulation is performed using the extracted coordinate values, it is possible to accurately and easily analyze variations in element characteristics according to the arrangement positions of the elements. . In addition, since any one of the circuit simulation methods is set from among a plurality of types of circuit simulation methods, various circuit simulation methods can be performed.

It is a functional block diagram which shows the structure of the circuit simulation apparatus which concerns on embodiment. It is a figure which shows the hardware constitutions of the circuit simulation apparatus which concerns on embodiment. It is a flowchart which shows the operation | movement procedure of a circuit simulation apparatus. It is a figure which shows an example of the circuit which has a current mirror. It is a figure which shows an example of a structure of a current mirror. It is a figure for demonstrating the production | generation method of the element recognition drawing using layout data. It is a figure which shows an example of the net list produced | generated from the symbol which has a coordinate value. It is a figure which shows an example of the model parameter file at the time of giving the parameter which made the coordinate value of an element a variable to a model parameter. It is a figure which shows an example of the model parameter file at the time of giving the section for analyzing the coordinate dependence of an element to a model parameter. It is a figure which shows an example of the screen at the time of extracting the coordinate value of an element from layout data. It is a figure which shows the result of the circuit simulation using the coordinate value of an element. It is a figure which shows the result of the circuit simulation using the coordinate of the element extracted from layout data.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1 Circuit simulation apparatus, 12 Schematic data generation part, 14 Analysis method setting part, 17 Element recognition data generation part, 18 Net list creation part, 19 Circuit simulation processing part, 61 Symbol information, 62, 63 Model parameter file

Claims (5)

A position information setting step for setting position information related to the arrangement position of the element in a symbol of the element used when designing the circuit of the integrated circuit;
A simulation step of performing a circuit simulation of the integrated circuit using a model parameter of the element in which a variable corresponding to the position information of the element is set, and position information set in the symbol;
A circuit simulation method comprising: The position information setting step includes:
2. The circuit simulation method according to claim 1, wherein position information of the element is extracted from layout data of the integrated circuit and set to the symbol.   The circuit simulation method according to claim 1, further comprising a simulation method setting step of setting a circuit simulation method so as to perform a circuit simulation using the position information from among a plurality of types of circuit simulation methods.   A circuit simulation program for causing a computer to execute the circuit simulation method according to claim 1. A position information setting unit for setting position information related to the arrangement position of the element in a symbol of the element used when designing the circuit of the integrated circuit;
A simulation unit that performs a circuit simulation of the integrated circuit using a model parameter of the element in which a variable corresponding to the position information of the element is set, and position information set in the symbol;
A circuit simulation apparatus comprising:

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