JPH02285971A - Gate drive circuit for inverter - Google Patents

Abstract

PURPOSE:To suppress distortion of waveform by detecting reverse current discharged from the gate of a switching element and suppressing driving of pair elements. CONSTITUTION:An inverter main circuit comprises a pair of switching elements 17, 18, as one unit component thereof, where the elements 17, 18 are driven through inverters 1, 2 and photocouplers 3, 4 based on drive signals A1, B1. The gate drive circuit comprises FETs 11, 12, gate drive transistors 13, 14, gate discharge transistors 15, 16, photocouplers 5, 6 and limit resistors 7-10. Discharge current of the elements 15, 16 is detected and provision of driving signal for the pair of photocouplers 5, 6 is suppressed when the elements 15, 16 are conducting.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Field of Application 1] The present invention relates to a gate drive circuit for an inverter that uses a switching element such as an IGBT or FET that does not have an accumulation time in its main circuit.

[Conventional technology]

FIG. 4 is a circuit diagram showing the configuration of a conventional gate drive circuit for this type of inverter, and FIG. 5 is a timing chart showing the operation of this conventional example.

A pair of switching elements 17 and 18 connected in series are one component of the inverter main circuit, and are connected between the positive and negative poles P and N of the DC power supply, and alternately repeat on and off operations.
Inverter 41 and inverter 42 perform power conversion
drive the transistors 17 and 18, respectively, when the negative logic drive signals A- and BtC are at low level)
Input, invert and output. The on-delay circuit 43 is composed of a shaping circuit, a resistor, a capacitor, and a diode, and delays the inverted signal of the inputted drive signal A2 by a certain period of time to force the photocoupler 3 to output the signal. Photocoupler 3, FET II, and gate drive transistor 1
3, the transistor 15 for gate charge discharge, and the limiting resistor 9 form a gate driving port or path for the switching element 17, and turn the switching element 17 on or off according to an input signal. Regarding the switching element 17 side,
On-delay circuit 44 and gate drive circuit (4, 12, 1
4, 16, 10) are completely the same as the switching element 17 side.

Next, the operation of this conventional example will be explained with reference to a timing diagram.

Now, at time 0, the negative logic drive signals Ax and B* are at high level and low level, respectively. Therefore, the switching element 17 is in the off state and the switching element 18 is in the on state.At time tI, the drive signal A x , Bz
When the delay circuit 44 is inverted, the input of the delay circuit 44 is inverted to low level, so the electric charge charged in the capacitor starts discharging (waveform D), and the input of the photocoupler 4 is immediately inverted to high level, turning off the photocoupler 4. shall be. On the other hand, the human power of the delay circuit 43 is at time 1. It is reversed and becomes a high level (waveform F), and charging of the capacitor starts, but since the time constant of the circuit is larger in charging than in discharging, the input of photocoupler 3 is input to photocoupler 4. Later than time t! When the waveform E) is inverted to low level, the photocoupler 3 is turned on. Next, the switching element 18 is turned off at approximately time t by the outputs of the photocouplers 4 and 3 via their respective gate drive circuits, and the switching element 17 is turned on slightly later at approximately time t2. Ru.

Next, the operation when the drive signal A2 and the drive signal B2 are switched at time t is exactly the same. In this way, the difference t0 between time t1 and time t2 is the on-delay time, and one switching element is turned on after the other switching element is turned off, so the positive and negative poles P, N
This can prevent short circuits between the two.

Further, an arm short-circuit prevention circuit for a transistor converter similar to the conventional example described above is disclosed in Japanese Patent Laid-Open No. 272878 of 1988. This circuit is a power converter that uses power transistors as switching elements. A pair of series-connected power transistors has a means for detecting a reverse bias voltage applied between the base and emitter of each, and a means for detecting a reverse bias voltage applied between the base and emitter of each transistor. and means for issuing a supply command to the forward bias current supply means of the other transistor when it is detected that a reverse bias voltage is applied. That is, the example of the present disclosure focuses on the fact that when a reverse bias current is applied to the base of one transistor in an on state to turn it off, a reverse bias voltage is generated between the base and emitter after the accumulation time elapses. When trying to turn on one transistor, it is detected that the other transistor is in the off state from the reverse voltage generated between its base and emitter, and this detection signal is used to supply the base current of one transistor to turn it on. By incorporating this into the conditions, one transistor is turned on at the same time when the accumulation time of the other transistor ends and the collector current becomes zero, and the on-delay circuits 43 and 44 as in the conventional example described above are not required. .

[Problem to be solved by the invention]

In the conventional example described above, it is necessary to set the on-delay time t of the on-delay circuit by taking into account variations in the on/off times of each switching element, and also taking into account variations in the characteristics of the components of the on-delay circuit. ,
The delay time is set to a large value. For this reason, when driving an AC motor with an inverter, distortion occurs in the current waveform, causing torque ripples and rotational ripples, and depending on the operating frequency, disturbances may occur and operation may become impossible. The PWM carrier frequency of the inverter is lowered to reduce the ratio of the on-delay time to the carrier period, and the motor terminal voltage is fed back to form a voltage compensation loop. However, the former method of lowering the carrier frequency has the disadvantage of generating noise, and the latter method requires insulation between the main circuit and the control circuit, using an isolation amplifier, isolation transformer, photocoupler, etc. Therefore, there is a drawback that the circuit configuration becomes complicated and costs increase.

In addition, the above-mentioned disclosed example uses a power transistor with an accumulation time as a switching element, so the situation is different from the case of the present application, but since a reverse bias current is always flowing through the transistor that is turned off, The disadvantage is that the power loss in the base circuit is large.

An object of the present invention is to reduce torque ripple and rotational ripple by omitting an on-delay circuit and reducing waveform distortion when switching the switching element in an inverter that uses a switching element such as an IGBTIFET in the main circuit that does not involve an accumulation time. It is an object of the present invention to provide a low cost gate drive circuit.

[Means to solve the problem]

The gate drive circuit for an inverter according to claim 1 of the present invention controls a reverse current discharged from the gate of a pair of switching elements when one of the switching elements in the driving state is reversed to the blocking state. The device according to claim 2, comprising: a current detector for detecting the current; and a blocking circuit for suppressing the generation of a drive signal that drives the other switching element during the energization period of the reverse current detected by the current detector. is a voltage detector that detects the gate voltage of a switching element, and suppresses the generation of a drive signal that drives the other switching element in the pair during a period when the gate voltage detected by the voltage detector is at a positive potential. It has a blocking circuit.

[Function J] The inverter main circuit has one pair of switching elements connected in series as one component, and multiple pairs are connected between the positive and negative electrodes of a DC power supply, and one switching element of the multiple pairs is sequentially connected to the other. The switching element performs power conversion by repeatedly turning on and off alternately.
An inverter to which the gate drive circuit of the present invention is applied has a switching element such as an IGBT or FET, which has an accumulation of current flowing for a certain period of time even after being switched to reverse bias while the switching element is forward biased and is conducting current. A switching element with no time is used.

According to the first aspect of the present invention, the discharge current is detected by utilizing the fact that the charge charged in the gate of the switching element is discharged when the switching element is turned off during energization, and the energization of the discharge current is performed. During the period, by suppressing the transmission of the drive signal of the switching element of the pair, a short circuit between the positive and negative electrodes of the power supply is caused. , by utilizing the fact that the gate potential is at a positive potential to suppress the transmission of the drive signal of the switching element of the pair during the period when the gate voltage is at a positive potential, the power supply is controlled as in claim 1. Short circuit between the positive and negative electrodes can be prevented.

[Example] Next, an example of the present invention will be described with reference to the drawings.

FIG. 1 is a circuit diagram showing the configuration of an embodiment of an inverter gate drive circuit according to the present invention, and FIG. 2 is a timing diagram illustrating the operation of this embodiment.

The configuration of this embodiment differs from the circuit configuration of the conventional example shown in FIG.
An inverter 1 is installed instead of the inverter 1, an inverter 2 is installed instead of the inverter 42 and the on-delay circuit 44, and a limiting resistor 7 and a limiting resistor 7 are installed in parallel with the limiting resistors 9 and 10 of the gate input circuit of the switching element 17 and 18, respectively. A photocoupler 5, a limiting resistor 8, and a photocoupler 6 are arranged, and the output side of the photocoupler 5 is connected between the base of the gate driving transistor 14 and the ground, and the output side of the photocoupler 6 is connected to the gate driving transistor 14. Everything else is the same except that it is connected between the base of No. 13 and ground.

Next, the operation of this embodiment will be explained with reference to timing charts.

Now, time t. The drive signals At and B+ are at high level and low level, respectively, and the switching element 17 is on and the switching element 18 is off. When the drive signal A1 changes from a high level to a low level and the drive signal B changes from a low level to a high level at time tl, the output of the inverter 1 changes from a low level to a high level, so the photocoupler 3 is turned off.
A high level voltage +V is applied to the gate of FETII to turn on FETII, while the output of inverter 2 changes to low level, turns on photocoupler 4, and turns FETII on.
Since the gate of ET12 is connected to ground, FET12 is turned off. Therefore, the bases of the gate driving transistor 13 and the gate charge discharging transistor 15 are grounded, while the high level voltage +V is applied to the bases of the gate driving transistor 14 and the gate charge discharging transistor 16. is input. Therefore, on the side of the switching element 17, the transistor 13 is turned off and the transistor 15 is turned on, thereby connecting the gate of the switching element 17 to ground. Then, the electric charge that had been charged in the gate of the switching element 17 during its ON period starts discharging to the ground, and the discharge current 11 (waveform H) shunts the limiting resistor 7°9, and the current 111 ( Waveform J) turns on the photocoupler 5 at approximately the same time as time t. Subsequently, at time 1.1, the switching element 17 turns off (eL, type M). When the photocoupler 5 is turned on, the bases of the transistors 14 and 16 receive a current of 12
The drive transistor 1 remains grounded (waveform K) while it is energized, and even if it receives the above-mentioned high-level voltage +V, the drive transistor 1 remains grounded (waveform K).
Gate drive of 4 is blocked. When the discharge of the current ip ends at time t and the photocoupler 5 turns off again, the transistor 14 turns on and drives the switching element 18, and at time t, the switching element 18 turns on. When the drive signal B changes from a high level to a low level and the drive signal AI changes from a low level to a high level, the gate of the switching element 17 is driven through the photocoupler 6 in exactly the same way during the discharge period of the gate of the switching element 18. At time t6, when the signal is blocked, the blocking is released and the gate of the switching element 17 starts charging (waveform H), and the gate voltage starts to rise, as shown in waveform G.
), the switching element 17 is turned on at time ty. Hereinafter, the same operation is repeated, that is, in the timing diagram, the period from time t1 to t3 and time ts-ta is
Each represents the blocking period mentioned above.

In this way, switching element 17. By alternately blocking the drive of the other party during the gate discharge period during conversion of the drive signals AI and BI between ts, it is possible to reliably prevent a short circuit between the positive and negative electrodes.

Next, another embodiment of the present invention will be described using the circuit diagram of FIG.

This embodiment uses the photocoupler 5 of the embodiment shown in FIG.
．． 6, a photocoupler 33 and a photocoupler 34 are used, respectively, to prevent the gates of the switching elements 17 and 18 from being driven while the gate voltages of the switching elements 17 and 18 are at a positive potential. In this way, after confirming that one switching element has turned off, the other switching element can be turned on, thereby preventing short circuits between the positive and negative poles.

[Effects of the Invention] As explained above, the present invention according to claim 1 detects the discharge reverse current from the gate of the switching element, and suppresses the driving of the switching element on the other side during that period. Accordingly, the second aspect monitors the gate voltage of the switching element and suppresses the driving of the switching element on the other side of the pair during the period when the gate voltage of the switching element is at a positive potential.
It is possible to easily obtain a gate drive circuit that has small waveform distortion and therefore produces small torque ripples and rotational ripples without using a complicated and costly circuit configuration as in the conventional example.

[Brief explanation of drawings]

Fig. 1 is a circuit diagram showing the configuration of one embodiment of the inverter gate drive circuit of the present invention, Fig. 2 is a timing diagram explaining the operation of this embodiment, and Fig. 3 shows the structure of another embodiment. FIG. 4 is a circuit diagram showing the configuration of a conventional example of an inverter gate drive circuit, and FIG. 5 is a timing diagram showing the operation of the conventional example shown in FIG. 4. 1.2... Inverter, 3.4, 5, 6, 33. 34... Photocoupler 7.
8,9.10.31.32...Control resistance, II, +
2...FET, 13, 14... Gate drive transistor, 15, 16
...Gate charge discharge transistor, 17, 18...
・Switching element, 11... charging/discharging current of switching element 17 gate,
ip...discharge current of switching element 17 gate, P
, N...positive and negative electrodes, +■...high level power supply, t, ~t7...time, At, B+...drive signal,
M... Waveform.

Claims (1)

[Scope of Claims] 1. In an inverter gate drive circuit in which a main circuit includes a pair of series-connected switching elements without accumulation time, the gate drive circuit includes: When one switching element is reversed to the blocking state,
It has a current detector that detects the reverse current discharged from its gate, and a blocking circuit that suppresses the generation of a drive signal that drives the other switching element during the conduction period of the reverse current detected by the current detector. An inverter gate drive circuit featuring: 2. In an inverter gate drive circuit whose main circuit includes a pair of series-connected switching elements without accumulation time, a voltage detector detects the gate voltage of the switching element, and a voltage detector detects the voltage detector. 1. A gate drive circuit for an inverter, comprising a blocking circuit that suppresses generation of a drive signal that drives the other switching element of the pair during a period when the gate voltage is at a positive potential.