JPH02285719A - Buffer memory circuit - Google Patents

Abstract

PURPOSE:To reduce the storage capacity of a buffer memory without causing any hindrance for consecutive readout by writing an audio data of one sector's share while one block data written just before is read. CONSTITUTION:When an audio data of one sector's share is fed to a write circuit 2a of a readout/write control circuit 2, the data is sequentially written in an address of buffers A, B of a work RAM 1. When the data of one sector's share is written, a readout signal is fed to a readout circuit 2b and the data in the buffers A, B is sequentially read out. A detection circuit 2c measures the readout elapsed time by the circuit 2b, detects a point of time when a half the capacity of the buffer A or B is read, supplies a write signal to the circuit 2a and the succeeding one block data is written to an area whose data is finished for readout. Thus, the storage capacity is reduced without causing any hindrance to the consecutive readout.

Description

DETAILED DESCRIPTION OF THE INVENTION "Field of Industrial Application" This invention is applicable to, for example, CD-1
The present invention relates to a buffer memory circuit suitable for use when decoding ADPCM data read from a computer such as an interactive computer into PCM data.

"Prior Art" A real-time file on a CD-1 is a file in which audio data, video data, and a program are interleaved and arranged on a disc, and playback is performed by synchronizing each data. This real-time file contains PCM data of 1/2.1/4.1
/8. ADP for real-time playback compressed to 1/16
CM data is also included.

Here, ADPCM data compressed from PCM data is
FIG. 5 shows the state of data when data blocks are interleaved in sectors on the disk so that they can be processed in real time correctly. The symbol “*” shown in the diagram is
Indicates the location where the audio data is stored.
” indicates a position where other data (eg, video data, program data, etc.) can be inserted by interleaving. Further, FIG. 6 shows the relationship between the amount of audio data on a CD-I disc and the playback time. When reproducing the interleaved audio data on the CD-1 disc, the reproduction time of the audio data is longer than the transfer rate (reading time) to the audio data controller as shown in the figure. For this reason, in the CD-1 system, if the audio data supplied from the disc is not reproduced in synchronization with the timing, data may be lost or gaps may occur in the reproduced sound. Therefore, in order to actually play back compressed audio data continuously in real time, it is necessary to temporarily store the audio data (prepare a buffer memory of one sector or more, and store the audio data currently being played and the next one). It is necessary to temporarily store the audio data.

Therefore, in a conventional CD-1 system, first and second buffer memories are used to store two sectors worth of audio data, and these first and second buffer memories are used to store two sectors worth of audio data. Audio data from the CD-1 disc is written sector by sector into the second buffer memory.

In this case, first, one sector worth of audio data is written into the first buffer memory. The audio data in the first buffer memory is then read out and played back. When the first buffer memory is played back, the next audio data is written to the second buffer memory. When the reproduction of the first buffer memory is completed, the audio data of the second buffer memory is subsequently read out and reproduced. Furthermore, when playing back the second buffer memory, the next sector of audio data is written into the first buffer memory whose playback has already been completed.

When the reproduction of the second buffer memory is completed, the audio data of the first buffer memory described above is reproduced. During reproduction of the first buffer memory, audio data of the next sector is further written to the second buffer memory. In this way, while the audio data in one buffer memory is being played back, the next audio data is written in the other buffer memory and the audio data is put on standby, thereby enabling continuous playback.

"Problems to be Solved by the Invention" By the way, the buffer memory circuit described above requires two sectors of buffer memory, so the memory capacity is large (and the number of parts is large, and the buffer memory circuit is A problem arises in that the occupied area becomes large.

This invention was made in view of the above-mentioned problems.
It is an object of the present invention to provide a buffer memory circuit whose memory capacity can be reduced.

"Means for Solving the Problems" In order to solve these problems, the present invention writes compressed block data to a -H buffer memory, reads out the compressed block data sequentially, and outputs the data.
In a buffer memory circuit configured to write the next compressed block data before the reading is completed, the amount of data that can be read in the time W required to write one block of compressed block data plus the data amount of one block is A buffer memory means for storing data, and l block data written immediately before in this buffer memory means are sequentially read out at a time R (a read control unit and a time (R-W) from the start of reading by this read control unit). a detecting section for detecting the elapsed time; and a detecting section for detecting the elapsed time;
A read system consisting of a write control unit that allocates a portion of the block data other than the area for which reading has not yet been completed as a write area for the next block of data, and sequentially writes the next block of data to this write area. It is characterized by comprising a write control means.

"Effect" AD equal to the amount of data that can be read in the time W required to write one block data plus the amount of data for one block.
A buffer memory means for storing PCM data is prepared, and 1 block data written immediately before in the buffer memory means is read out at a time R by a read control section. On this occasion,
■The time from the start of reading by the reading control unit is a predetermined time (
The detection unit detects that the time period R−W) has elapsed.

Based on the output signal of the detection section, the write control section transfers the data of one block of data currently being read to the next one block onto the buffer memory means, except for the area where the reading has not yet been completed. It is allocated as a data write area, and the next one block data is written in this write area.

In this way, the operations ① to ② described above are repeated while taking proper timing until the data is exhausted.

"Embodiments" Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention.

In this figure, ■ is a work RAM that temporarily stores audio data, and corresponds to a buffer memory for data decoding. In this case, when attempting to continuously reproduce audio data, it is necessary to pay attention to the following points.

(1) Before the reproduction of one sector is finished, the next sector of audio data is written to the buffer memory.

(2) New audio data must not be written to a memory area in which audio data has not yet been read.

From the conditions (1) and (2) above, the storage capacity of the work RAMI is the amount of data that can be read in this time W and the data for one sector, assuming that the time required to write one sector is time W. Only the amount required is the sum of the amount.

Here, the time W required for writing is shown below (i)
, (ii).

(i) Signal s1 from detection circuit 2c is sent to write circuit 2a
Processing time of CPU (Central Processing Unit) from when audio data is supplied to when audio data is actually written.

(ii) DAM (Direct Access Memory)
Time to transfer audio data by etc.

By the way, if the writing time W is the same for each level shown in FIG. , for level A stereo, which has the shortest readout time. In this embodiment, the time to read one sector of audio data from a CD-I disc is 1/75 seconds, and the level A stereo playback time R takes 2/75 seconds for the reasons described above. Also, CD
-1, the audio data is ADP within 1775 seconds.
It must be sent to the CM decoder. Therefore, the storage capacity of the buffer memory required to store the amount of data that can be read in the write time W is at least 0.5 sectors.

As a result of the above, the storage capacity of the work RAMI only needs to be 1.5 sectors. Therefore, the work RAM 1 has a physical size ranging from relative address "0" to r as shown in FIG.
It has a storage capacity of 1.5 sectors up to 3455J, and addresses "0" to "2303" are stored in buffer A1 addresses "0" to "1151" and addresses r2304J to r3.
455J is designated as buffer B. In this case, the address "
0'' to rl151J are shared by buffer A and buffer B. Further, this work RAMI is designed to be able to simultaneously write and read audio data. However, it is not possible to write and read to one buffer at the same time, and buffer A
When buffer B is on the write side, buffer B is on the read side, and conversely, when buffer A is on the read side, buffer B is on the write side.

Reference numeral 2 denotes a read/write control circuit, which is composed of a write circuit 2 a +read circuit 2 b, and a detection circuit 2C. The write circuit 2a generates a write address for the work RAMI, and writes the work RAMI based on the write address.
One sector worth of audio data is written to MI in time W. The read circuit 2b is a work RAMI.
Based on this read address, one sector worth of audio data is read from the work RAMI in time R and supplied to the ADPCM decoder 3. The detection circuit 2C detects that the time (R-W) has elapsed since the start of reading by the reading circuit 2b, and supplies the signal S1 to the writing circuit 2a. The audio data read out by the reading circuit 2b is supplied to the ADPCM decoder 3.

The ADPCM decoder 3 converts the audio data into PCM
The data is converted into data and supplied to a D/A converter (path shown) via a digital filter (path shown) as necessary. PCM data is converted into an analog signal by a D/A converter.

Next, the operation of this embodiment with the above configuration will be explained with reference to the timing chart shown in FIG.

First, one sector worth of audio data is supplied from the CD-I disc to the writing circuit 2a. In the write circuit 2a,
Time 1. At this point, the WRITE signal is output to the work RAMI, and address data from "0" to r2303J is generated.

Then, the audio data for the first 22 minutes is written into the buffer A by the write circuit 2a based on the address data.

When writing of one sector worth of audio data to buffer A is completed, RE is sent to readout circuit 2b at time t3.
AD A signal is provided. This causes the first switching between buffers A and B. In other words, the first buffer switching timing is for buffer A or B.
This occurs when writing of one sector worth of data is completed. The read circuit 2b supplied with the READ A signal generates address data from "0" to r2303J. Based on this address data, read circuit 2b
The audio data in buffer A is sequentially read out according to the playback time, and the ADPCM decoder 3
supplied to

Furthermore, the detection circuit 2C measures the passage of time from the reading start time t by the reading circuit 2b. In this embodiment, this is specifically achieved by detecting the point in time when the address becomes "1152", that is, the point in time when reading (1-0,5) of buffer A is completed, but this is achieved using a separate timer. Of course, it is also possible to provide a device such as the above and perform measurement using this. Then, at time t4, that is, when time (R-W) has elapsed from read start time t3, signal Sl is supplied from detection circuit 2C to write circuit 2a. In this case, the data read operation is performed at address rl1.
52J, and a writable area for one sector is secured in the work RAM 1. In the write circuit 2a to which the signal S1 is supplied, WRIT is executed at time t.
The E signal is output to the work RAMI, and the time t
, to t8, the audio data of the next sector is at address "0" to N15N and address r2304J to r3.
The data is divided into 455J and 172 sectors each and written. The write operation by the write circuit 2a is performed in parallel with the read operation by the read circuit 2b described above.

Next, at time t, the readout circuit 2b receives READ.
A B signal is supplied. This causes a second buffer switch. That is, the second and subsequent buffer switching timings occur at the time when reading of one sector worth of data from buffer A or B is completed. In this way, when the readout operation of the audio data by the readout circuit 2b is completed, the audio data written in the addresses rOJ to rl151J and addresses r2304J to r3455J assigned to Ba Nofa B from time t onward are read out. The readout circuit 2b sequentially reads out the signals and supplies them to the ADPCM decoder 3.

Further, the detection circuit 2c measures the passage of time from the read start time t7 by the read circuit 2b (specifically, detects the value of the read address).

Then, at time t8, that is, reading start time t7
When the time (R-W) has elapsed, the signal S1 is supplied from the detection circuit 2C to the write circuit 2a. Write circuit 2a
Then, at time tll, the WRITE signal is sent to work RA.
At the same time as being output to MI, the audio data of the next sector is written to addresses "0" to r2303J assigned to buffer A from time t to too.

Then, at time tll, when the reading operation of the buffer B by the reading circuit 2b is completed, the audio data of the buffer A is continuously read by the reading circuit 2b and is supplied to the ADPCM decoder 3.

In this way, when the first audio data is written to buffer 8, the next audio data is written to buffer B, and the next sector of audio data is written to buffer A, and so on. Buffer A → Buffer B → Writing is repeated from buffer A to buffer B... until there is no audio data left. Further, in the same way as writing, reading is repeated in the order of buffer A→buffer B→buffer A→buffer B, and so on.

Next, a second embodiment of the invention will be explained. The electrical configuration of this embodiment is the same as that of the first embodiment shown in FIG.

FIG. 4 is a conceptual diagram for explaining the logical configuration of the work RAM of this embodiment. In this figure, workpiece R
AMI has physical size from relative address "0" to r3
There are 1.5 sectors up to 455J, addresses "0" to r
Up to l151J are shared between buffer A and buffer B,
Addresses N152'' to r2303J are shared by buffer A and buffer C, and addresses r2304J to [34
55'' are shared by buffer B and buffer C.

According to the above configuration, first, the first sector worth of audio data is written into the buffer A by the write circuit 2a. Then, the audio data in the buffer A is sequentially read out by the readout circuit 2b, and this readout reaches the final part of the first half (2) of the audio data, that is, the address rl151J (then, the next one sector worth of audio data is read out from the buffer B In this case, the audio data is written into buffer B so as to be continuous with the second half of the audio data in buffer A, as shown in the figure.

Next, when all the audio data in the buffer A mentioned above is read out, the reading circuit 2b continues to read out the audio data in the buffer B.
■ The first half of the audio data.

(2) are read out sequentially. Then, this read is performed in buffer B.
When the last part of the first half of the audio data (2) reaches the address r3455J, the next one sector of audio data is written to the buffer C. In this case as well, as with buffer B, the second half of the audio data in buffer B is written in a continuous manner.

Then, similar to the above-described transfer of the read operation from buffer A to buffer B, when all the audio data in buffer B is read out, the audio data in buffer C is subsequently read out by the readout circuit 2b.

Next, when the read operation reaches the final part of the first half of the audio data in buffer C, the process starts again.

The next one sector worth of audio data is written to file A. Similarly, read operation and write operation are performed from buffer A → buffer B → buffer C → buffer A, etc.
...is repeated.

As described above, this embodiment is characterized in that audio data is written in a ring format from addresses "0" to "3455" of the work RAM 1. Therefore, the address data generated by the write circuit 2a and the read circuit 2b is "0-3455.0-3455. . .
A simple continuous pattern such as "..." is sufficient, and the burden on hardware or software is reduced.

Note that in the first and second embodiments described above, l/
When two sectors worth of audio data are read, the next one sector worth of audio data is written, so that the work RAM is
This has the advantage of reducing the storage capacity of I by 25%.Also, if the writing time W of audio data to the buffer memory is shorter, the work RAMI
The storage capacity of may be even smaller than 1.5 sectors. In addition, if you prepare a work RAMI with a storage capacity of 1.5 sectors or more and make it compatible with each buffer memory, you can have more margin in the writing time W, and you can use it for CD-ROMs with slow CPUs, etc.
It is also effective for one system.

"Effects of the Invention" As explained above, according to the present invention, when reading one block of data written immediately before in the buffer memory means, one sector worth of ADPC is stored in the buffer memory means.
As soon as the area where M data can be written is secured, the next 1.
Writing a sector's worth of ADPCM data has the advantage that the storage capacity of the buffer memory means can be reduced without interfering with continuous reading.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention, FIG. 2 is a conceptual diagram illustrating the configuration of a buffer memory of the embodiment, and FIG. 3 explains the operation of the embodiment. FIG. 4 is a conceptual diagram for explaining the configuration of the buffer memory of the second embodiment of the present invention, and FIG. 5 shows the state on the disk when audio data is arranged in an interleaved manner. FIG. 6 is a timing chart for explaining the time relationship between audio data on a disc and reproduced sound. 1... Work RAM (buffer memory means),
2... Read/write control circuit (read/write control means)
, 2a...Write circuit (write control section), 2b.
...readout circuit (readout control section), 2c...
Detection circuit (detection section).

Claims (1)

[Claims] Once compressed block data is written to a buffer memory,
When sequentially reading and outputting the compressed block data, in a buffer memory circuit configured to write the next compressed block data before the reading is completed, data that can be read in the time W required to write one block of compressed block data. buffer memory means for storing data equal to the amount of data plus one block of data; a read control unit that sequentially reads out one block of data written immediately before in this buffer memory means at a time R; and this read control unit. a detecting section for detecting that a time period (R-W) has elapsed since the start of reading by the buffer memory means;
A read system consisting of a write control unit that allocates a portion of the block data other than the area for which reading has not yet been completed as a write area for the next block of data, and sequentially writes the next block of data to this write area. A buffer memory circuit comprising write control means.