JPH02203690A - Two buffer memory switching method for picture signal decoder - Google Patents

Abstract

PURPOSE:To eliminate useless waiting period and to utilize the processing capability of a decoding processing section to the utmost by starting a decoding processing of other memory picture even when the other memory picture is under post-processing after the decoding processing of one memory picture is finished. CONSTITUTION:When post-processing by one frame to one memory picture 31 is finished, the termination of the decoding processing by one frame of other memory picture 32 is detected, the post-processing is switched to the other memory picture 32 and the write address for decoding is controlled so as not to pass over the readout address of the post-processing and the post-processing and the decoding processing are switched independently. Even when the other memory picture 32 is subject to post-processing after the decoding processing of one memory picture 31 is finished in this way, the decoding processing of the other memory picture is initiated, useless wait period of the decoding processing is eliminated and frame elimination is reduced and the average loading design is attained.

Description

Detailed Description of the Invention (Technical Field to Which the Invention Pertains) The present invention relates to switching of a two-sided buffer memory between a decoding processing section and a subsequent processing section in an image signal decoding device used for video conferences and video telephones. It is about the method.

(Prior art) In an image signal decoding device used for video conferences and video calls, the period required to decode one frame of encoded data such as camera output (NTSC signal, etc.) is If the transmission speed of the transmission path or the processing speed of the decoding device is low, and the cycle is longer than one frame, two A surface buffer memory may be provided.

The image signal decoding device receives the 1 signal sent from the encoding device.
After the decoding processing unit decodes one frame's worth of encoded data, the decoded data is written to one memory surface of the two-sided buffer memory. In parallel with this decoding process, the other memory is written before that. The post-processing unit reads out the decoded data written on the screen for post-processing, and converts the decoded data into an NTSC signal 1 etc. that can be reproduced on a monitor screen.

A video signal is synthesized from the luminance signal and chrominance signal of the decoded data, horizontal and vertical synchronization signals and color burst signals are added to this, and D/A conversion and the like are performed.

FIG. 4 shows a flowchart of a switching method for a two-sided buffer memory in a conventional image signal decoding device. In the figure, side A is one side of the two-sided buffer memory, side B is the other side, and the power is turned on. It is assumed that at the start of processing such as time, post-processing for side A is started, and decoding processing is started for side B.

When the post-processing started on side A is completed (YE of (a)
If the decoding process for side B is not finished in S) (No in (B)), the post-processing of the next frame will start again on side A), the same decoded data will be played repeatedly. This results in a piece being dropped.

In general, the post-processing period for one frame does not change equal to the frame period of an NTSC signal, etc. However, the encoding processing period and decoding processing period for one frame in interframe coding Since it varies depending on the degree of change in the image signal between frames, the number of dropped frames also varies.

On the other hand, at the point when the post-processing that has started for Side A is completed ((A)
If the decoding process for side B has finished with (YES)
b) YES), the post-processing side is on side B, and the decoding side is on side A.
(1).

Conversely, when viewed from the standpoint of the decoding process started on side B, the situation is as follows. If the post-processing for side A has not finished (NO in (force)) when the decoding process for side B has finished (YES in (E)), wait for it to finish, and when the post-processing has finished (( YES) to switch the post-processing side to side B and the decoding process side to side A at the same time (1).

After that, the post-processing side and the decoding side are processed in the same way.
Simultaneous switching between side A and side B is repeated.

FIG. 5 shows an example of a circuit that realizes a switching method for a two-sided buffer memory in a conventional image signal decoding device. In the figure, 1 is a post-processing circuit, 2 is a post-processing start signal generation circuit,
3 is a two-sided frame memory; 31 and 32 are A and B sides of the frame memory; 4 is a memory surface switching control circuit; 41 is a memory surface specifying circuit composed of a 1-bit counter and the like in the memory surface switching control circuit 4; 42 is a decoding processing end signal holding circuit composed of a set-reset type flip-flop, etc.; 43 is an AND circuit; 5 is a readout control circuit;
51 is a switch for switching the readout surface in the readout control circuit 5; 52 is a readout address counter; 6
is a post-processing end signal generation circuit, 7 is a decoding processing circuit, 8 is a decoding processing start signal generation circuit, 9 is a write control circuit,
91 is a switch for switching the writing surface in the write control circuit 9; 92 is a write address counter; 1
0 is a decoding process end signal generation circuit.

This circuit operates as follows.

First, post-processing and decoding processing are performed as follows.

When handling NTSC signals, the post-processing start signal generation circuit 2 periodically generates the post-processing start signal at a rate of approximately 30 times per second.

The address counter 52 in the read control circuit 5 is reset by this post-processing start signal.

Memory plane designation circuit 41 in memory plane switching control circuit 4
The post-processing circuit 1 is connected to either side of the frame memories 31 and 32 specified by the output Q of the frame memory 32 by the switch 51 in the read control circuit 5, and the post-processing circuit 1 starts reading post-processing data from the first address. .

By supplying a clock to the address counter 52, the post-processing circuit 1 sequentially reads post-processed data while advancing the address value of the frame memory. Then, the post-processing end signal generation circuit 6 outputs a post-processing end signal to the memory surface switching control circuit 4 at the time when the end of the post-processing is detected.

On the other hand, triggered by the inversion of the outputs Q and Q of the memory surface specifying circuit 41, the decoding process start signal generating circuit 8 generates a decoding process start signal. The address counter 92 in the write control circuit 9 is reset by this decoding processing start signal, and the decoding processing circuit 7 is connected to either surface of the frame memories 31 and 32 specified by the output Q of the memory surface specifying circuit 41. It is connected by a switch 91 in the write control circuit 9.

The decoding processing circuit 7 starts writing data for decoding processing from the first address.

By supplying a clock to the address counter 92, the decoding processing circuit 7 sequentially writes decoded data without advancing the address value of the frame memory. Then, the decoding process end signal generating circuit 10 outputs a decoding process end signal to the memory surface switching control circuit 4 at the time when the end of the decoding process is detected.

Next, switching control between the post-processing surface (reading surface) and the decoding processing surface (writing surface) in the two-sided frame memory 3 is performed as follows.

From the viewpoint of post-processing, when the post-processing end signal generating circuit 6 generates the post-processing end signal for one side of the two-sided frame memory 3, the decoding process end signal generating circuit 10
If the decoding process end signal has not been generated for the other side, this means that the decoding process end signal has not been input to the holding circuit 42.

There is no change in the output of the AND circuit 43 that ANDs the output of the post-processing end signal generation circuit 6 and the Q output of the holding circuit 42. Therefore, since there is no change in the output of the memory surface designation circuit 41 and the readout surface is not switched, the post-processing circuit 1 reads the same data again as the next frame data on the same memory surface.

Conversely, if the decoding process end signal generation circuit IO has already generated the decoding process end signal for the other side and the holding circuit 42 holds the decoding process end signal, the output of the AND circuit 43 is It rises to It I 11, and the outputs Q and Q of the rememory plane designation circuit 41 are inverted.

Therefore, the writing surface and the reading surface are switched at the same time,
The post-processing circuit 1 reads the decoded data as the next frame data on the other memory surface, and the decoding processing circuit 7 writes the next decoded data on one memory surface.

Note that the decoding process end signal held by the holding circuit 42 is reset by the output of the AND circuit 43 for switching the memory plane of the two-sided frame memory 3.

Conversely, from the viewpoint of the decoding process, at the time when the decoding process end signal generation circuit 10 generates the decoding process end signal for the other side of the two-sided frame memory 3, the post-processing end signal generation circuit 6 When the post-processing end signal for one side is not generated, the holding circuit 42 only holds the decoding processing end signal, and the output of the AND circuit 43 does not change. Therefore, there is no change in the output of the memory surface specifying circuit 41, and the writing surface is not switched, so the decoding process start signal generating circuit 8 does not generate a decoding process start signal.

The decoding processing circuit 7 waits for the start of the next decoding process until the writing surface is switched.

As described above, when the post-processing end signal generation circuit 6 generates the post-processing end signal, the post-processing side and the decoding side are simultaneously switched.

Of course, if the post-processing end signal is generated at the same time as the decoding end signal is generated, the post-processing side and the decoding side are immediately switched at the same time, so there is no need to wait for the start of the decoding process.

FIG. 6 shows a switching transition diagram between the post-processing side and the decoding process side in the conventional two-sided buffer memory switching method shown in FIGS. 4 and 5 above. In the figure, Wl, W2. W
3. ... is the decoding processing period, R1, R2, R3,
... is the post-processing period, the A side is one side of the two-sided buffer memory, and the B side is the other side. Further, the shaded post-processing period means a frame in which the same decoded data is repeatedly reproduced and frames are dropped.

In FIG. 6, (a) shows the case where the decoding processing period W is within the post-processing period R1 for one frame, that is, within the frame period of the reproduced video signal, and (b) shows the case where the decoding processing period W is within the frame period of 1 to 2 frames. (c) shows the case where the period is 2 to 3 frames.

In FIG. 6(a), if the decoding processing period W for one frame is always within the frame period, the difference period becomes a wasted period in which no decoding processing is performed, but the Since all frames received are decoded and post-processed, there is no frame dropout. However, in this case, considering that the decoding processing period W varies depending on the change in the image signal as mentioned above, it is necessary to design the peak load so that the maximum value of the decoding processing period W is within the frame period. becomes.

In FIG. 6(b), if the decoding processing period W for one frame is always within 1 to 2 frame periods, decoding processing is not performed during the difference period from the 2 frame period. It will be a wasted period. In this case, the encoding device sends 1/2 (W 2 ) of the entire frame to the decoding device.

W4. Only even frames (corresponding to W6, etc.) can be sent, and the post-processing unit has to play back the same decoded frame data twice, so 1
/2 frame becomes a piece drop. Furthermore, in this case too,
It is necessary to design a peak load such that the maximum value of the decoding processing period W is within two frame periods.

In FIG. 6(c), if the decoding processing period W for one frame is always within 2 to 3 frame periods, decoding processing is not performed during the difference period from the 3 frame period. It will be a wasted period. In this case, the encoding device can only send 1/3 of the total frames (even frames corresponding to W3, W6, W9, etc.) to the decoding device, and the post-processing unit sends the same decoded frame data to the decoding device. The data is played back three times, and two-thirds of the frames in the playback image signal are omitted. Furthermore, in this case as well, a peak load design is required such that the maximum value of the decoding processing period W is within three frame periods.

The shortcomings of such conventional switching methods for two-sided buffer memory can be summarized as follows.

The first drawback is that even if the decoding process for one frame on one memory plane is completed, the decoding process for the next frame cannot be started until the post-processing on the other memory plane is finished. First, there is a needless waiting period.

The second drawback is that the decoding processing period is the frame period N~(
N+1) times, the total number of frames that the encoding device can send to the decoding device is 17 (N+1). Furthermore, the same decoded data must be repeatedly reproduced N times during the decoding process of one frame, resulting in frame drop N/(N+1), which tends to cause frame drop.

The third drawback is the maximum drop rate N/(N+1), that is, if the same decoded data is allowed to be played back N times, the maximum value of the decoding processing period is the frame period (N+1).
1) It requires a peak load design to reduce the peak load by 1), and 1) it requires a decoding device with a high processing speed that can handle the peak load, although this is usually not necessary.

(Object of the Invention) An object of the present invention is to eliminate such drawbacks by decoding data from one memory surface after the decoding process for the other memory surface is completed, even if the other memory surface is undergoing post-processing. An image signal decoding device that eliminates wasteful waiting periods in decoding processing, reduces dropped frames of frames sent from an encoding device to a decoding device, and enables average load design by starting the decoding process of An object of the present invention is to provide a two-sided buffer memory switching method.

(Structure of the Invention) (Characteristics of the Invention and Differences from the Prior Art) In order to achieve the above object, the present invention provides a two-sided buffer memory between a decoding processing section and a subsequent processing section of a single image signal decoding device. In the switching method, 1 for one memory surface
When post-processing for frames (fields) is completed,
Detects that the decoding process for one frame (field) on the other memory plane is completed, switches the post-processing plane to the other memory plane, and detects that the other memory plane is in the process of decoding. Then, the next post-processing is continued on one memory surface, and when the decoding process on the other memory surface is completed, the next decoding surface is immediately switched to the one memory surface being post-processed, and the decoding is continued. The main feature is that the write address for encoding does not overtake the read address for post-processing, and that the post-processing and decoding processes can be switched independently.

This differs from the prior art in that after the decoding process for one memory plane is completed, the decoding process for the other memory plane is started even if the other memory plane is being processed.

This eliminates the wasteful waiting period of the decoding process as in the prior art, and reduces the number of dropped frames sent from the encoding device to the decoding device.

(Example) FIG. 1 shows a flowchart related to a method for switching two-sided buffer memories when the method of the present invention is implemented in an image signal decoding device. In FIG. 1, side A is one side of the two-sided buffer memory. It is assumed that side A and side B are the other sides, and at the time of starting processing such as when the power is turned on, post-processing of side A is started, and decoding processing is started on side B.

When the post-processing started on side A is completed (YE of (a)
In S), if the decoding process for side B has not finished (No in (B), the post-processing of the first frame should be started again on side A), the same decoded data can be repeatedly played back. , and the piece is dropped.

On the other hand, if the decoding process for side B has finished (YES in (b)), switch the post-processed side to side B (1), and then use the same method to change the post-processed side to side A. and side B are alternately switched over and over again.

From the perspective of the decoding process started on side B, the situation is as follows. If the post-processing side is A side, or the post-processing side is B side.
If the post-processing address precedes the decoding address on the side B (YES in (e)), the decoding process is continued on the side B (power). Then, when the decoding process for side B is completed (YES in (g)), the decoding process side is switched to side A (ri). Thereafter, the decoding processing plane is repeatedly switched between the A side and the B side in a similar manner.

Further, as is clear from FIG. 1, switching between the post-processing side and the decoding process side is independent.

FIG. 2 shows an example of a circuit for implementing the method for switching the two-sided buffer memory in the image signal decoding device according to the present invention. In FIG. 46 is a comparison circuit that compares the outputs of the memory surface designation circuits 44 and 45; 47 is an AND circuit; 93 is an AND circuit in the write control circuit 9; 111 is a comparison circuit that compares the read address and write address in the address control circuit 11, 112 is a NAND circuit in the address control circuit 11, and circuit blocks with other numbers are This circuit is the same as that shown in FIG. 5, and its explanation will be omitted.

The circuit of FIG. 2 operates as follows.

First, post-processing and decoding processing are performed as follows.

When handling NTSC signals, the post-processing start signal generation circuit 2 periodically generates the post-processing start signal at a rate of approximately 30 times per second. With this post-processing start signal, the readout control circuit 5
The address counter 52 in the memory surface switching control circuit 4 is reset, and either surface of the frame memories 31 and 32 specified by the output Q1 of the memory surface specifying circuit 44 in the memory surface switching control circuit 4 and the post-processing circuit 1 are selected by the switch in the read control circuit 5. 51, and the post-processing circuit 1 starts reading post-processing data from the first address. Post-processing circuit 1
By supplying a clock to the address counter 52, the post-processing data is sequentially read out while advancing the address value of the frame memory, and the post-processing end signal generating circuit 6 starts the post-processing data at the point when it detects the end of the post-processing. A processing end signal is output to the memory surface switching control circuit 4.

On the other hand, triggered by the inversion of the output Q2 of the memory surface specifying circuit 45, the decoding process start signal generating circuit 8 generates a decoding process start signal. The address counter 92 in the write control circuit 9 is reset by this decoding processing start signal, and the decoding processing circuit 7 is connected to one of the surfaces of the frame memories 31 and 32 specified by the output Q2 of the memory surface specifying circuit 45. It is connected by the switch 91 in the write control circuit 9, and the decoding processing circuit 7 starts writing the decrypted data from the first address. The decoding processing circuit 7 sequentially writes the decoded data without advancing the address value of the frame memory by supplying a clock to the address counter 92, and the decoding processing end signal generating circuit 10 starts the decoding processing. When the end of the decoding process is detected, a decoding process end signal is output to the memory surface switching control circuit 4.

Next, switching control between the post-processing surface (reading surface) and the decoding processing surface (writing surface) in the two-sided frame memory 3 is performed as follows.

From the viewpoint of post-processing, when the post-processing end signal generation circuit 6 generates the post-processing end signal for one side of the two-sided frame memory 3, the outputs Q1 and Q2 of the memory side specifying circuits 44 and 45 are The output of the comparator circuit 46 rises to 44171 only while the output of the post-processing end signal generating circuit 6 is equal to 44171, and only when the output of the AND circuit 47 that ANDs the output of the comparator circuit 46 and the output of the post-processing end signal generating circuit 6 rises to "1". , the output Q1 of the memory surface designation circuit 44 is inverted, and the output Q1 of the memory surface designation circuit 44 is inverted,
starts reading post-processing data for the next frame from the other memory surface.

If this is not the case, the output of the comparison circuit 46 has not risen to 1'', so there is no change in the outputs of the AND circuit 47 and the memory surface designation circuit 44, the readout surface is not switched, and the post-processing circuit 1 is connected to the same memory surface. The same data is read out again as the next frame data from the previous frame. In other words, if the same memory surface is being decoded at the end of post-processing for one memory surface, the other memory surface is free. The next post-processing is performed by switching to the other memory surface.
If the other memory plane is being decoded, the primary post-processing will be performed again on one memory plane.

Conversely, from the viewpoint of the decoding process, when the decoding process end signal generation circuit 10 generates the decoding process end signal for the other side of the two-sided frame memory 3, the output of the memory side specifying circuit 45 is immediately Q2 is reversed. Therefore, the writing surface is switched without waiting for the decoding process, and the decoding processing circuit 7 writes the next decoded data to one memory surface.

In this case, there will be a period when the post-processing surface and the decoding processing surface are on the same surface, but if the write address for decoding processing overtakes the read address for post-processing during this period, the read data will span two temporally different frames. Therefore, it is necessary to control the write address. For example, when writing data for decoding processing line by line, the address counters 52 and 9
2 line address values are compared and if they are the same, the output rises to "1", so if the output of the comparison circuit 46 rises to 1", the N of the outputs of the comparison circuits 111 and 46 rises to "1".
The output of the NAND circuit 112 that performs the AND operation falls to 0''.Then, the output of the NAND circuit 112 and the clock output of the encoding processing circuit 7 are output to the address counter 92 by the AND circuit 93 that ANDs the output of the NAND circuit 112 and the clock output of the encoding processing circuit 7. It is possible to control the write address from overtaking the read address by stopping the clock supply to the read address and preventing the read address from advancing.

In addition, 8 or 16 pixels in the horizontal direction and 1 precept in the vertical direction
When reading is performed for each block of 6 lines, the comparator circuit 111 needs to raise its output to "1" every time the write line address value catches up to the read line address value by 8 or 16 lines.

FIG. 3 shows a switching transition diagram between the post-processing side and the decoding process side in the switching method of the two-sided buffer memory according to the present invention. In the figure, Wl, W2°, W3. ... is the decoding processing period, R1, R2, R3, ... is the post-processing period,
The A side is one side of the 2-sided buffer memory, and the 8th side is the other side. Further, the shaded post-processing period means a frame in which the same decoded data is repeatedly reproduced and is omitted.

In FIG. 3, (a) shows the case where the decoding processing period W is within the post-processing period R1 for one frame, that is, within the frame period of the reproduced video signal, and (b) shows the case where the decoding processing period W is within the frame period of 1 to 2 frames. (c) shows the case where the period is 2 to 3 frames.

In Fig. 3(a), as long as the decoding processing period W for one frame is always within one frame period on average in time, the same decoded data can be processed even if it exceeds one frame period from time to time. A maximum of 2 frame cycles can be tolerated without repeating playback. Further, it is possible to design an average load such that the time average value of the decoding processing period is within one frame period.

In FIG. 3(b), if the decoding processing period W for one frame is always within 1 to 2 frame cycles on time average, it is possible to change the decoding process from the encoding device to the decoding device compared to the conventional method. The number of frames that can be sent to can be increased. Furthermore, even if the period exceeds two frames from time to time, a maximum of three frame periods can be tolerated without repeatedly reproducing the same decoded data three times or more. Furthermore, it is possible to design an average load such that the time average value of the decoding processing period W is within two frame cycles.

In FIG. 3(e), if the decoding processing period W for one frame is always within 2 to 3 frame cycles on time average, it is possible to change the decoding process from the encoding device to the decoding device compared to the conventional method. The number of frames that can be sent to can be increased. Furthermore, even if the period exceeds 3 frames at times, a maximum of 4 frame periods can be tolerated without repeatedly reproducing the same decoded data more than 4 times. Furthermore, it is possible to design an average load such that the time average value of the decoding processing period W is within three frame periods.

Note that for convenience of explanation, post-processing is started on the A side and decoding processing is started on the 8th side when the power is turned on, etc., but the reverse may be used. In addition, since the post-processing and decoding processing sides are switched independently, if you prevent the decoding processing address from overtaking the post-processing address, you can start post-processing and decoding processing on the same plane. Good, furthermore, 1 consisting of 2 fields
If the number of pixel data for one frame is too large in terms of processing speed, only the pixel data for one odd or even field may be handled.

(Effects of the Invention) As explained above, according to the present invention, after the decoding process for one memory plane is completed, even if the other memory plane is undergoing post-processing, the decoding process for the other memory plane can be continued. By starting, there are advantages as follows.

The first advantage is that the processing capacity of the decoding processing section can be utilized to the maximum extent possible, since unnecessary waiting periods for decoding processing can be eliminated compared to the conventional method.

The second advantage is that if the time average value of the decoding processing period is N to (N+1) times the frame period, the number of frames that can be sent from the encoding device to the decoding device can be reduced to (N-1) times the total frame period.
/N-N/(N+1), which is more than the conventional method. In other words, the same decoded data is repeatedly played back from (N-1) to N times during the decoding process of one frame, and the frame drop rate is (N-1)/N-N/(N+
1), the frame drop rate can be reduced compared to the conventional method.

The third advantage is that when the maximum dropout rate is set to N/(N+1), the time average value of the decoding processing period is set to N of the frame period.
Since it is possible to design the average load so that the average load is less than double, the processing speed of the decoding device can be slower than in the past.

[Brief explanation of the drawing]

FIG. 1 is a flowchart for switching the two-sided buffer memory according to the present invention, FIG. 2 is a diagram showing an example of a circuit for implementing the two-sided buffer memory switching method according to the present invention, and FIG. FIG. 4 is a switching flowchart of a conventional two-sided buffer memory; FIG. 5 is a diagram showing an example of a circuit for implementing the conventional two-sided buffer memory switching method; FIG. FIG. 3 is a conventional switching transition diagram between a post-processing side and a decoding process side. 1...Post-processing circuit, 2...Post-processing start signal generation circuit, 3...2-sided frame memory, 31...
・ Frame memory (A side), 32... Frame memory (8 sides), 4...Memory side switching control circuit, 4
4.45...Memory surface specification circuit, 46.111.
・Comparison circuit, 47.93 ・Logic product circuit, 5 ・
・Reading control circuit, 51, 91 ・Switch, 5
2.92...Address counter, 6...Post-processing end signal generation circuit, 7...Decoding processing circuit, 8
...Decoding process start signal generation circuit, 9...Write control circuit, 10...Decoding process end signal generation circuit, 11...Address control circuit, 112...NAND circuit. Patent applicant Nippon Telegraph and Telephone Corporation

Claims (1)

[Claims] In a method for switching a two-sided buffer memory between a decoding processing unit and a post-processing unit of an image signal decoding device, when post-processing for one frame (field) on one memory plane is completed, the other memory It detects that the decoding process for one frame (field) of one frame has been completed, switches the post-processing plane to the other memory plane, detects that the other memory plane is in the process of decoding, and then switches the post-processing plane to the other memory plane. Post-processing is continued for one memory surface, and when the decoding process for the other memory surface is completed, the next decoding surface is immediately switched to the one memory surface that is being post-processed, and the decoding process is continued for the other memory surface. 2 of an image signal decoding device characterized in that the write address of the image signal is controlled so as not to overtake the read address of the post-processing, and the post-processing and decoding processing sides can be independently switched.
How to switch area buffer memory.