JPS61127031A - Buffer memory device - Google Patents

Abstract

PURPOSE:To make data buffuring high efficiency and at a reading speed which is prescribed by the working speed of a signal processing system at the follow ing state as well as the writing data quantity, by setting at least three buffer memories in parallel with each other. CONSTITUTION:The data DATA to be sent from a coding device 1 synchronously with a frame signal FRM is sent to a buffer memory device 2. The writing operation is carried out to a buffer memory A23. When the next frame signal FRM is produced after the writing operation is through with the memory A23, the data are written to a buffer memory B24. At the same time, the data are read out of the memory A23 and sent to a transmission line. When all data are read out of the memory A23, an end signal END-A is delivered. Thus a reading control part 26 enables the reading of the memory B24 with the next frame signal. Hereafter the similar operations are carried out cyclically in the order of memories A, B, C, A and B.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a buffer memory device, and more particularly to a buffer memory device that efficiently buffers data applied at fixed cycle timing.

[Prior art and problems to be solved by the invention]
The buffer memory device according to the present invention is used, for example, in an image encoding system for video conferences.

In an image encoding system for a video conference, a video signal from a television camera is converted into a data format for transmission in an encoding device, and then the data on the transmitting side is transferred to a transmission path via a buffer memory device. I am trying to send it to. Here, the buffer memory device is provided for the purpose of temporarily storing data to be transmitted and adjusting the speed difference between the transmitting side and the speed of the transmission path and/or the receiving side.

Since the images in the video conference are so-called moving images,
This means that all the video signals from the television camera must be transmitted, but if all the data were to be transmitted, the amount of information transmitted would be very large and the transmission costs would be considerable, and the entire system would have to be constructed using high-speed operating circuits. It will have to come true. Therefore, normally, for example, in the above-mentioned encoding device, a change image between the image data up to the previous time and the currently scanned image data is extracted, and only the change is transmitted, thereby reducing the amount of information transmitted.

In addition, the image encoding system for video conferencing is basically
For example, since it is operated in accordance with NTSC, the data to be transmitted is sent to the transmission line via a buffer memory device every frame at a fixed period, and is converted into an image on a receiver, such as a CRT monitor, on the receiving side. It has become so.

Since the video conferencing system is currently in the practical stage,
It is intended to pursue a cost of 47 ohms. From this point of view, we would like to use a relatively low-speed transmission line and implement it with a relatively low-speed circuit. Sending out only the above-mentioned changed image data is in accordance with this purpose. On the other hand, from the viewpoint of transmitting only changed image data, the amount of data that can be sent during a frame period is set based on the normal amount of changed image data, and the system is designed accordingly.

Therefore, if image data that changes more than the data amount predicted at the design stage is generated, it can be sent within one frame period, and if the data sending is synchronized with the frame period, the image data may be sent in the middle of the image data transmission. Since the next frame is transferred and new changed image data is transmitted from the beginning, the untransmitted data described above is not visualized on the receiving side, and the lower part of the CRT monitor remains as before. This creates an unnatural state.

Therefore, the present applicant has already proposed a multi-field evacuation method to solve this problem.

In other words, the multi-field dropout method is a method in which, if the changed image data to be transmitted cannot be sent within the frame period, the changed image data continues to be sent without refreshing in the next frame. When the amount of changed image data is large, multiple field data are not sent out, resulting in so-called multi-field omission. However, since the above-mentioned unnaturalness is removed, there is no real problem.

(7) Multi-field deletion is normally performed in an encoding device, and the data processed in this way by the encoding device is applied to a buffer memory device for transmission to a transmission path.

Conventionally, double buffer memories and single backup memories have been proposed as configurations of such buffer memory devices.

FIG. 2 shows an example of a configuration using double pack memory. FIG. 2 shows the transmitting side on the left side and the receiving side on the right side across the transmission path. The transmitting side includes an encoding device 1', a double buffer memory device 2', and switches 8w1 . S
'w2 is shown. On the receiving side, a double buffer memory device 5, switches before and after it, SW4, and a receiver 6 are shown. However, below, only the transmitting side will be described.

As mentioned above, the data DATA to be transmitted by the encoding device 1'
1 is determined and applied to the buffer memory device τ.

In the buffer memory device 7, first, in the I-th frame, the switch sw1 is selected as the A-side buffer memory BM-A, and the data DATA is written to BM-A.

In the next frame, the switch sw2 is selected to the BM-A side, allowing the written data to be output to the transmission path, and the switch sw2 is selected to the B-side buffer memory BM-H, and the encoder 1 'The data DATA 1 from BM
-Written to B. Furthermore, in the next frame, the data written in BM-B is output to the transmission path, and data DATA 1 from the encoding device 1' is written in BM-A. The same process is repeated alternately.

The above operation timing is shown in FIG. 3(-) shows a frame synchronization signal of a constant period, FIG. 3(b) shows the data DATA 1 to be transmitted, FIG. 3(e) and (d) show the operation modes of buffer memories A and B, R indicates a read operation, W indicates a write operation, and FIG. 3 (,) indicates the transmission data DATA 2 on the transmission path. Due to the intervention of the buffer memory device 2', the transmitted data DATA2 is delayed by one frame.

In the above operation, it should be noted that the buffer memory device is switched and operated in synchronization with a frame signal of a constant period. This is due to the fact that the video conference system in this example operates based on frame signals.

Due to the fact that the buffer memory is switched according to the frame, when the data to be transmitted continuously at one time spans multiple frames, especially when transmitting data based on multi-field elimination, case,
When viewed from the receiving side, one screen is converted into an image based on data read out over several frames, but memory switching is performed for continuous data, but it has sufficient capacity especially as a buffer memory. In such a case, the memory switching operation becomes wasteful.

On the other hand, in the case of a single buffer memory device, a large memory capacity is required due to the maximum amount of information sent,
Additionally, as the memory capacity increases, the time lag until the written data is read out increases, resulting in a problem of decreased responsiveness.

Such issues will be discussed in detail later in connection with the examples.

[Means to solve the problem]

In view of the above-mentioned problems, the present invention provides a buffer memory device that stores a data string applied in response to a periodic timing control signal and sends it to a subsequent signal processing system, the buffer memory device having at least three The three buffer memory sections are connected to one buffer memory section in synchronization with a predetermined timing control signal. The data string is written to the buffer memory section, and the written data string is read out in synchronization with the next timing control signal, and at the same time, the data string is written to the next buffer memory section, and this operation is performed cyclically. The control section is configured to perform the control section when the amount of data written to the buffer memory section exceeds the amount of data that can be accepted by the subsequent signal processing system within a certain period of time defined by the timing control signal. A buffer memory device is provided that is operative to stop the transmission of applied data in response to a timing control signal.

[Effect]

In other words, at least three buffer memories are installed in parallel, and the control unit takes into account the read speed determined by the number of written data and the operating speed of the subsequent signal processing system, and performs efficient data buffering. It is.

〔Example〕

Embodiments of the present invention will be described below with reference to the accompanying drawings.

FIG. 1 is a diagram showing the configuration of a buffer memory device as an embodiment of the present invention, and is a diagram showing a case where the buffer memory device is used in a video conference encoding system. Therefore, the encoding device 1 is connected to the front stage of the buffer memory device 2, and the interface 3 connected to the transmission path is connected to the rear stage. The buffer memory device 2 shown in FIG. 1 includes three buffer memories 23 to 25 provided in parallel, a write control section 22, a read control section 26, and an external control section 27 for controlling these. It is being In this embodiment, the data DATA- from the encoding device 1 is temporarily held in the flip-flop 7'21.

The buffer memories 23 to 25 have the same configuration, and a specific circuit diagram thereof is shown in FIG. Taking the buffer memory 23 as an example, the memory 23 to which write data is written and read
1. Address counter 232 that counts the number of write data
, a latch circuit 234 that holds the value of the address counter,
A controller 235 for comparing addresses and a timing control circuit 233 for controlling these circuits are connected as shown.

In this embodiment, the memory 231 has a write clock W
CK and read clock RCK are designed to operate with different clocks. Of course, the write clock WCK and the read clock RCK can also be set to the same value. However, writing and reading are not performed at the same time.

A specific circuit diagram of the write control section 22 is shown in FIG.

The write control unit 22 receives the last pulse L from the encoding device 1.
A rise detection circuit 221 that detects the rise of AST, a ternary counter 222 that updates the count value based on the output of the rise detection circuit, and a ternary counter 222 that decodes the output of the counter and stores it in one of the memories 23 to 25. Write enable signal πN-A-W
It consists of a decoder 223 that outputs EN-C.

The ternary counter 222 is made up of three buffer memories 2.
This is because it corresponds to 3 to 25, and 0.1, 2, 0
, 1... is a ring counter.

A specific circuit diagram of the read control unit 26 is shown in FIG. 6.The read control unit 26 includes flip rollers 7'261. A rising edge detection circuit 262.0Rf-) 263. A ternary counter 262 and a decoder 265 are connected as shown in the figure.

A specific circuit diagram of the external control section 27 is shown in FIG.

The external control unit includes a counter 271 and a flip flora f27.
4, adder 275, delay circuit 275, counter 277,
A comparator 278, a rise detection circuit 273, and a fall detection circuit 272 are configured as shown.

The external control unit 27 sets the amount of data to be sent to a predetermined reference value R.
When the value is larger than EF, a strag signal STP is output to the encoding device 1 to stop sending out the data to be written to the buffer memory device 2. For this reason, a counter 271 counts the data to be sent using the write clock WCK. Prior to this counting, the falling edge detection circuit 272 detects the falling edge of the last (last) 14th pulse, and the counter 27
I'm asking you to clear 1. On the other hand, the rise detection circuit 2
At step 73, the rising of the last nine pulses LAST is detected, and the value of the counter 271 before being cleared is latched in the flip-flop 274. The latched value is added to the counter 277 via the adder 275, and compared with the reference value REF by the comparator 278.
When the value exceeds F, the strag signal STP is output. The counter 277 is cleared by a signal from the rise detection circuit 273 at the timing when the value of the counter 271 is latched in the flip-flop 274 described above, and after a certain period of time from this clearing, the value of the counter 271 is cleared by a signal from the delay circuit 276. value is decoded. The value of the counter 277 is decremented by the read clock RCK.

The operation of the buffer memory device shown in FIGS. 1 and 4 to 7 will be explained below.

The frame signal FRM is emitted at regular intervals (Fig. 8 (^
)), data DATA to be sent from the encoding device 1 is sent to the buffer memory device 2 in synchronization with this signal FRM. Each data of data DATA is write clock WC
It is synchronized with K.

Each data of the data DATA is once latched by the flip-flop 21 and applied to the descendant buffer memories 23-25. The flip roller f21 is provided for the purpose of operational reliability and is not essentially necessary. Although data is applied in parallel to each of the buffer memories 23 to 25, writing is performed only for valid (invalid) data at the top of the write permission signal outputted from the write control section 22. Therefore, first, since (1)NA is enabled, writing is performed on the buffer memory A23. That is, as shown in FIG. 4, the data applied to the terminal DATA-I is written into the buffer memory section 231 following the write clock WCK. In this case, the write clock W
CK is counted by address counter 232 and write permission signal ■
The number of data written during the period when N is valid is counted. The count value of address counter 232 is used when reading is performed in the next frame.

In parallel with the above operation, the external control unit 27 outputs the write clock W.
CK is counted and the number of data written to the buffer memory A23 is counted. Normally, this count value does not reach the reference value, so the strag signal STP is not output.

The encoding device 1 generates a last pulse L indicating the end of the data.
Output AST.

The write control unit 22 detects the rise of this last pulse LAST and switches the write permission signal to ①NA or 1) WIDN-B. The external control unit 27 controls this last cruise LAS.
Clear the counter 271 with T.

When the next frame signal FRM is issued, the buffer memo! Data is written in the J-824 in the same manner as described above, and in parallel, the data written in the buffer memory A23 is sent out to the transmission line via the bladder outlet interface 3. Data reading is performed by the read control unit 26
This is performed in synchronization with the read clock RCK in a state where the read enable signal REN-A is output from the read enable signal REN-A. When the entire number of write data stored in the latch circuit 234 of the buffer memory A23 has been read, an end signal END-A is output. In response to this end signal END-A, the read control unit 26 enables REN-B to enable reading of the data written in the buffer memory B24 in the next frame period.

Thereafter, data is written to the buffer memory B and data is read from the buffer memory B in the same manner.
4 B − + C and so on.

The above is the operation in a normal case where there is relatively little changed image data, but the transmission speed of the transmission path is slow compared to the operation of the encoding system, in other words, the write clock WC
When the read clock RCK is slow and the data written within one frame period cannot be transmitted within one frame period, or when the above-mentioned multi-field drop occurs and the data is not transmitted continuously. The case where it should be sent will be described with reference to the timing chart in FIG.

The controller 2780 reference value RIF shown in FIG. 7 is determined in consideration of such circumstances.

First, data DATA is sent out from the encoding device 1 in synchronization with the frame signal FRM, and written into the buffer memory A whose write permission WN is enabled (eighth
Figures (a) (b) (,) ).

The WEN signal is switched cyclically depending on the LAST signal on the encoder side.When the amount of information coming from the encoder side is small, the LAST signal is output once per video frame, so the In the case of a triple buffer, the earliest it is two frames after the signal is output until the WN signal of the A memory is output again. Therefore, if the data written in Memo+7A can be completely read within two frames, it is possible to avoid collision between the read control signal REN and the write control signal WEN. Therefore, if the amount of information for which the data cannot be read after two frames is expected to come from the encoder side, that is, the count value of the external control unit 27 is set to the reference value RE.
If F is exceeded, a coding stop signal STP is sent to the encoder side to stop data in the next frame.

When entering the next frame, data to be transmitted next should originally be output from the encoding device 1, but since the stop signal STP is still on, no data is output in this frame. On the other hand, read permission signal REN-A
is turned on and the above written data is transferred to buffer memory A.
Read from. In parallel with this read operation, the external control unit 2
7 counter 277 is decremented by the read clock RCK. When the appropriate number of data has been read out, the stop signal STP of the comparator 278 of the external control section 27 is turned off (FIG. 8(d)). This makes the next write possible, but since it operates in synchronization with the frame signal FRM, no write data is sent out from the encoding device 1 during this period.

In this case, the data DATA is a sufficient amount to be transmitted within one frame period, and the encoding device 1
The last signal I and AST are output without receiving the stop signal STP from 7.

The same applies to the next data DATAc.

Furthermore, even in the case where data should be sent over several frames in the multi-field drop state, the stop signal STP is sent from the external control unit 27 whenever necessary, as described above.
is issued, the WEN signal and the REN signal do not collide, and one REN signal can be kept enabled over a plurality of frames, allowing data to be read out regardless of the frame period.

It is obvious that the single buffer method is not suitable from the viewpoint of improving the efficiency of the entire system in the operation of temporarily storing data in a buffer memory and transmitting it to a subsequent signal processing system.

This is because write timing and read timing are clearly separated, making it impossible to perform write and read operations in parallel. Therefore, in order to establish efficient buffering, it is necessary to arrange two or more buffer memories in parallel.

However, it is not sufficient to simply configure the double buffer memory and switch it every frame period as in the prior art. In particular, when the speed of the transmission line is overflowing, and when a multi-field drop phenomenon occurs, the data is written to buffer memory A in the first frame, and read from buffer memory A in the second frame. At the same time, writing is done to backup memory B, but when the third frame is entered, the contents of buffer memory A are all read out.
Writing to buffer memory A is not possible, and buffer memory B cannot be read. Therefore, in the third frame, only the read operation of buffer memory A is performed. Back memory-A in the next 4th frame
During writing to buffer memory B, reading is performed, but in the next 5th frame, reading from buffer memory B is not completed, and writing to buffer memory IJ + B and reading from buffer memory A are performed. I can't.

The same applies below. Therefore, in the above example, dead time occurs in the third frame and the fifth frame. Furthermore, as described above, in order to operate in response to the write inhibit state, the configuration shown in FIG. 2 alone is not sufficient, and a control circuit is required.

On the other hand, in the embodiment based on the present invention described above, the external control unit 27 inputs data into the notnofa memory in consideration of the transmission speed of the transmission line, and three buffer memories are provided. They are installed in parallel to enable write and read operations. In particular, the provision of the third backup memory is effective for storing image data with a small amount of change after multi-field collapse, and prevents play from occurring in the transmission path.

It is also possible to have four or more buffer memory configurations.

However, the number of units (more than three) is determined by considering frame period, transmission path speed, cost performance, etc.

In the above embodiment, a buffer memory device in an image data encoding system for a video conference was illustrated, but the read operation is performed in synchronization with a timing signal that is issued at a constant cycle, and the subsequent circuit is prevented from overflowing. The present invention can be similarly applied to other cases where data that cannot be sent out within a certain period is occasionally generated and the most efficient buffering is desired.

〔Effect of the invention〕

As described above, according to the present invention, a buffer memory device capable of efficient buffering is provided.

[Brief explanation of drawings]

FIG. 1 is a configuration diagram of a buffer memory device as an embodiment of the present invention, FIG. 2 is a configuration diagram of a conventional image data transmission system, FIG. 3 is an operation timing diagram of the buffer memory in FIG. 2, and FIG. The figure is a circuit diagram as an example of the buffer memory section in FIG. 1, FIG. 5 is a circuit diagram as an example of the write control section in FIG. 1, and FIG. 6 is a circuit diagram as an example of the read control section in FIG. FIG. 7 is a circuit diagram as an example of the external control section in FIG. 1, and FIG. 8 is an operation timing chart of the buffer device in FIG. 1. (Explanation of symbols) 1... Encoding device, 2... Buffer device, 3...
Interface, 21...Flip 70 horn, 22
...Write control section, 23-25... Buffer memory section, 26... Read control section, 27... External control section. Figure 2 Figure 3

Claims (1)

[Claims] 1. A buffer memory device that stores a data string applied in response to a periodic timing control signal and sends it to a subsequent signal processing system, which comprises at least three buffer memory sections and a data string applied in response to a periodic timing control signal. The control unit includes a control unit that monitors the number of write data and read operation of the buffer memory units, and the three buffer memory units write the data string to one buffer memory unit in synchronization with a predetermined timing control signal. , the data string is written to the next buffer memory section at the same time as the written data string is read out in synchronization with the next timing control signal, and such an operation is performed cyclically. The part is applied in response to the timing control signal when the data written to the buffer memory part exceeds the amount of data that can be accepted by the subsequent signal processing system within a certain period of time specified by the timing control signal. A buffer memory device that operates to stop the transmission of data.