JPS63102482A - Picture encoding transmitter - Google Patents

Abstract

PURPOSE:To reduce unnaturalness in a reproduced picture on the receiving side, by selecting a frame omitting pattern in accordance with the value of the quantity of information accumulated in a memory so that continuous frame omission can be avoided. CONSTITUTION:Frame pulse 24 which is generated at every updating time are inputted to a frame counter 25 of module M constituting a frame omission controlling circuit 21 and the count signal 26a and overflow pulse 26b of the frame counter 25 are produced. The signal 26a is sent to a frame omitting pattern outputting device 31 and the signal 26b is sent to a latch circuit 29 which latches the mode signal that is frame-omitted at the moment when the overflow pulse is outputted. Thereafter, a frame omitting signal 28 is produced by a mode selector 27, to which information 16 accumulated in a memory is inputted, and supplied to the latch circuit 29. The frame omitting mode signal 20 of the circuit 29 is supplied to the frame omitting pattern outputting device 31 and the device 31 is caused to output the signal 30 as a frame omitting signal 22. Therefore, occurrence of a state where numerous frames are continuously omitted can be prevented and the movement of a picture is made smoother.

Description

[Detailed description of the invention] [Industrial application field] The present invention relates to an image encoding and transmitting device.

[Conventional technology]

A related invention to this invention is Japanese Patent Application No. 116931/1983, ``Encoding Control Circuit,'' filed by the same applicant as this invention. For example, consider the case of encoding and transmitting television images. If a television image between one vertical synchronization signal and the next vertical synchronization signal is one frame image, there are many identical image parts in images of temporally consecutive frames. This same image part is not transmitted, only the different image part is transmitted, and the receiving side stores the image information of the previous frame and reads the same image part from this memory to reproduce the image of one frame. For example, the amount of transmission can be reduced, and therefore the time required for transmission can be reduced. However, images of consecutive frames may change suddenly, so in order to deal with such cases, buffer memory is provided on both the sending and receiving sides, and buffer memory is provided on both the sending and receiving sides until the suddenly changed images are processed. You must remember this.

Since the required average transmission speed can be determined depending on the type of image to be transmitted, it is necessary to equip a transmission device (including a transmission area) with a transmission speed corresponding to this average transmission speed, and to prevent sudden changes in the image. Therefore, when the amount of information to be transmitted increases rapidly, a transmission device is used that stores it in a transmission buffer and sequentially transmits it.

In such a transmission device, overflow of the transmission buffer must be avoided. Therefore, if the amount of untransmitted memory in the transmission buffer exceeds a certain amount, measures are taken to prevent the transmission buffer from overflowing at the cost of sacrificing the quality of the image information to be transmitted.

FIG. 5 is a block diagram showing the configuration of a conventional device. In the figure, (1) is an analog image signal, (2) is an A/DI device, (3) is a digital image signal, and (4) is a one-frame image signal. A block divider that divides a digital image signal into multiple blocks, (5) is a previous frame reproduced image signal that reproduces the image signal of the same block of the previous frame, (6) is a subtractor, and (7) is a difference between frames. signal, (8) is the difference signal (
7) a block encoding circuit that encodes in block units;
(9) is block encoding information, (No.) is the transmission buffer memory, (11) is the block decoding circuit, (12) is the decoded interframe difference signal, (13) is the adder, (
14) is a reproduced image signal, (15) is a frame memo IJ,
(16) is the amount of information stored in the transmission buffer memory, that is, the amount of unread storage in the transmission buffer memory (10), (
17) is the threshold control circuit, (18) is the threshold value, (1
9) is a comparator, (20) is a block judgment signal, (21)
is a frame drop control circuit, (22) is a frame drop signal, and (23) is block encoded information sent to the transmission path.

Next, the operation will be explained. In the initial state when transmission starts,
Since the frame memory (15) is cleared, the signal (5) does not exist, and the digital image signal (3) is divided into blocks by the block divider (41) and passes through the subtractor (6) as it is, and is converted into a block code. The encoder circuit (8) encodes each block to become block encoded information (9), which is written into the transmission buffer memory (10), read out at the writing node, and sent out onto the transmission path.By the way, the difference signal ( 7
) is encoded by the encoding circuit (8) and the decoding circuit (11)
Since signal (12) is decoded by , signal (12) is the same as signal (7), and since signal (5) does not exist for the first frame, signal (12) is stored as signal (14) in frame memory (15). written to. After the first frame is completed, from the next frame onwards, the signal from the previous frame corresponding to the signal input from the block divider (4) to the subtracter] 6) is the frame memo! j (15) as a previous frame reproduced image signal (5), and the difference between both signals is outputted as a difference signal 17 by a subtractor (6). The difference signal (7) becomes zero for a block that is an image that is exactly the same as the image one frame before. If the difference signal (7) is less than the threshold (18) in the comparison of the comparator (no), there is no need to transmit that information, so the block encoding circuit (8) is controlled by the block determination signal (20). There is no output from. Difference signal (
7) is written in the transmission buffer memory IJ (10) as block encoded information (9), and is sequentially read out and transmitted.

Further, the block encoded information (9) is decoded by the block decoding circuit (11) and is the same signal C as the difference signal (7).
12), and by adding the previous frame reproduced image signal (5) to this, the image signal of the current frame (portrait block) is obtained,
That is, the reproduced image signal (14) is written to the position of the block in the frame memory (15), and is output as the signal (51) for the next frame.

By the way, as explained earlier, in order to avoid the transmission buffer memory (lO) from overflowing, it is necessary to write to the transmission buffer memory (10) according to the memory storage information amount (16) even if it sacrifices the quality of the transmitted image information. limit. One block of difference signal (7) L is composed of data from ε□ to ε, and! =(ε□, ε2.・
...εk) and the absolute value of each d, -i is 1ε11, when d≧Th, the comparator (19) outputs l as block encoding information, and d('f”h When L
It is controlled so that it does not output (L is set to 0). If the amount of information stored in the memory (16) increases, the value of Th can be increased to limit convolution into the forwarding buffer memory (10).

When the memory storage information -m C16) increases further, a frame drop signal (22) is output and all block encoded information (9) is output regardless of the block judgment signal (20).
) to 0.

Figure 6 shows the amount of memory storage information (16
) T and threshold if! j (18) Th relationship and the value TB of T at the boundary point that outputs the frame drop signal (22)
FIG.

[Problem that the invention seeks to solve]

Since the conventional device is configured as described above, no information related to the image is input during the period when the memory storage information amount (16) exceeds TB, so when the image of this period is played back on the receiving side, the period is It is displayed as a still image, and the moment the memory storage information amount (16) becomes smaller than TB, a frame image that moves significantly is displayed, causing the image movement to become unnatural and the quality of the received image being played back to deteriorate. There was a problem of significant deterioration.

This invention was made in order to solve the above-mentioned problems, and its purpose is to provide an image encoding and transmitting device that can prevent the overflow of the transmission buffer memory while avoiding deterioration of the quality of received images as much as possible. shall be.

[Means for solving problems]

In this invention, as shown in FIG. 6, the amount of information stored in the memory (16
) Frame dropping is performed by selecting a frame dropping pattern that is adapted to each of the seven pieces depending on the value of T, thereby preventing the occurrence of a situation in which a large number of pieces are removed in succession.

[Effect]

If frame dropping is performed intermittently while avoiding continuous frame dropping as much as the memory storage information amount allows, the memory storage information amount will eventually decrease and there will be no need for frame dropping. Furthermore, even when frame dropping is in progress, if frames are dropped intermittently, the unnatural motion of the received and reproduced image will be reduced.

〔Example〕

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of the present invention,
Although only the frame drop control circuit (21) is shown in FIG. 1, the other parts are the same as the fifth factor.

Further, in FIG. 1, the same reference numerals as in FIG. 5 indicate the same or equivalent parts, or the same signals, and % (24) is a frame pulse. A frame pulse is a pulse generated every time a frame is updated, and when the image signal is a television signal, the frame pulse corresponds to a vertical synchronization signal.

(25) is a modulo M frame counter that counts frame pulses (24); (26a) is the output signal (f) of the parallel output terminal of the frame counter (25); (26b) is a signal representing the count value of the frame counter; ) is the overflow pulse from the frame counter, (27)
is a frame in which the buffer memory storage information it (16) is input, and as the buffer memory storage information amount (16) increases, the frame counter (25) outputs a frame drop signal (22) during one period of M frame phases. Phase number K(0
A mode selector that outputs a frame drop mode that increases <K × M), (28) is a frame drop mode signal, (29)
(30) is a mode latch (30) in which the #l run mode signal (28) is set when the overflow pulse (26b) is output from the frame counter (25).
Frame dropping mode signal set in (29), (31)
is the frame drop mode signal (3o) and the frame counter (25
) is a frame drop pattern output device that outputs a frame drop signal (22) according to the count value (26a) of .

FIG. 2 is a diagram showing an example of the operation of the device of this invention, and the horizontal axis is the 6th axis.
Similarly to the horizontal axis in the figure, the memory storage information amount (16) T, the line represented by Th is the threshold value, and the line represented by Md is the frame drop mode. The relationship between T and Th is the same as the relationship shown in FIG. Also, when T becomes equal to or greater than TB, piece dropping starts, but the 6th
In the example shown in the figure, snack frames that are over T or TB are not dropped as in the case of rice, but frames are dropped intermittently, and frames are dropped out of M frames, leaving the remaining frames. (M-K) frames are transmitted. Each block of the (M-K) frames to be transmitted is compared with the highest threshold Th, and blocks whose differential signal is below the threshold are not output. As T increases/M
When LT exceeds TA (a value determined by design), all frames are dropped by setting /M=1.

FIG. 3 is a block diagram showing an example of the frame drop control circuit (21) in FIG.
(251) is the first counter, (252) is the second counter, (311) to (314) are AND gates, (315)
) is an or gate. The example shown in Figure 3 is M=16, K
= 0, 4, 8, 12, and 16 buildings.

Figure 4 is an operation time chart showing the signal progress of the circuit in Figure 3. The left part is the bit pattern set in the mode latch (29), and the right part is the bit showing the progress of the frame drop signal (22). It's a pattern.

Hereinafter, the operation of the apparatus of the present invention will be explained using FIG. 3 and FIG. 4. Memory storage information it (16) T is T,
In the following cases, the mode selector (27) outputs 4 bits of 0000 J, and the content of the mode latch (29) is
As shown in the figure tal, it becomes [0000, J, and this logic "0" bit causes AND gates (311) to (3
14), the frame drop signal (22) is always roJ, and frame drop is not performed. When T exceeds TB, the frame drop mode Md changes to four stages as shown in Figure 2, and the contents of the mode latch (29) are fbl*tel as shown in Figure 4.

Like fdl and iel. By the way, the first counter (251) and the second counter (252) are each binary 2-bit counters, and the first counter (251)
2 bits are input to the frame drop pattern output device (31) and control the AND gates (311) to (314).
For example, when the content of the mode latch (29) is as shown in FIG. 4, 1cl, the frame drop signal (22) is logic "1" only for frames where the count value of the first counter (251) is 0 and 2. is output and frame dropping is performed.

When T exceeds T people, continuous frame dropping is performed as shown in FIG. 4, 1cl.

Note that the examples shown in FIGS. 3 and 4 are numerical examples used for convenience of explanation, and it goes without saying that the present invention is not limited to such numerical examples. In addition, the relative relationship between the threshold Th and the frame dropping mode Md in Fig. 2 (the relative position on the horizontal axis also shows one design example, for example, when the threshold It may be designed so that the frame drop mode Md is started before the frame drop mode.Furthermore, the frame drop mode Md can be controlled in relation to two variables: the memory storage information!(16) and the threshold value Th.

〔Effect of the invention〕

As described above, according to the present invention, since the continuous frame dropping is avoided as much as possible, it is possible to reduce the degree to which movement feels unnatural in the reproduced image on the receiving side.

[Brief explanation of the drawing]

Fig. 1 is a block diagram showing an embodiment of the present invention, Fig. 2 is a block diagram showing the operation of the invention, Fig. 3 is a block diagram showing a design example of Fig. 1, and Fig. 4 is a block diagram showing the design example of Fig. 3. FIG. 5 is a block diagram showing the configuration of a conventional device; and FIG. 6 is a diagram showing the operation of the device shown in FIG. 5. (3) is a digital image signal, (4) is a block divider, (5) is a previous frame reproduced image signal, (6) is a subtractor,
(8j is a block encoding circuit, ('0) is a transmission buffer memory, (11) is a block decoding circuit, (16) is a memory storage information amount, (17) is a threshold control circuit, (19)
) is a comparator, (21) is a frame drop control circuit, (22) is a frame drop signal, (25) is a frame counter, (251) is a first counter, (252) is a second counter, (27)
) is the mode selector, (29) is the mode latch, (31
) is a frame dropping pattern output device. Note that the same reference numerals in each figure indicate the same or corresponding parts.

Claims (3)

[Claims] (1) (a) means for dividing a temporally continuously changing image into predetermined frame periods and generating an image signal digitally encoded for each frame; (b) digitally encoded for each frame; (c) a block divider that divides the image signal into a plurality of blocks corresponding to the image position within the frame; (d) a block encoding circuit that converts the output of the differentiator into a block code; (e) (f) a transmission buffer memory that temporarily stores the output of this block encoding circuit, reads this memory in the order in which it was written, and outputs it to the transmission path; means for setting predetermined values in a threshold control circuit and a frame drop control circuit, respectively; (g) means for comparing the threshold set in the threshold control circuit with the output of the difference device; means for stopping the output of the block coding circuit for the block when the output of the block is below a threshold, and stopping the output of the block coding circuit for one frame according to the output logic of the frame drop control circuit; In the image encoding transmission device, the frame dropping control circuit includes: (p) a mode selector that outputs a mode signal of a frame dropping mode corresponding to the amount of unread storage in the transmission buffer; (q) changes in the frame; a modulo M frame counter that counts frame pulses output every time; (r) a mode latch that sets a mode signal of the output of the mode selector every time an overflow pulse is output from this frame counter; s) a frame drop pattern output device that inputs the mode signal set in the mode latch and the count value of the frame counter and outputs a frame drop signal according to a predetermined frame drop pattern corresponding to these two inputs; An image encoding and transmitting device characterized by comprising: (2) The mode selector outputs a frame drop signal at any K phases (0≦K≦M) in one period in which the count value of the frame counter goes around M phases from 0 to (M-1). Outputs
Frame dropping modes for controlling not to output frame dropping signals in the remaining (M-K) phases are provided for K types (predetermined in advance by design), increasing the amount of unread storage in the transmission buffer. 2. The image encoding and transmitting apparatus according to claim 1, wherein the image encoding and transmitting apparatus outputs a mode signal of a frame dropping mode in which the value of K increases as the number of frames increases. (3) The frame counter includes a first counter modulo n that counts frame pulses, and an arbitrary k phase (0≦k≦n
) for outputting a frame dropping signal in the remaining (n-k) phases and controlling not to output a frame dropping signal in the remaining (n-k) phases, the number k types of frame dropping modes are provided, and unread storage in the transmission buffer memory is provided. 3. The image encoding and transmitting apparatus according to claim 2, wherein as the amount increases, a signal is output for selecting a frame dropping pattern with a larger numerical value k in the frame dropping pattern.