JPH02284423A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPH02284423A JPH02284423A JP10625389A JP10625389A JPH02284423A JP H02284423 A JPH02284423 A JP H02284423A JP 10625389 A JP10625389 A JP 10625389A JP 10625389 A JP10625389 A JP 10625389A JP H02284423 A JPH02284423 A JP H02284423A
- Authority
- JP
- Japan
- Prior art keywords
- hydrogen fluoride
- hydrofluoric acid
- buffered hydrofluoric
- acid solution
- film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 28
- 238000004519 manufacturing process Methods 0.000 title claims description 5
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 claims abstract description 73
- 229910000040 hydrogen fluoride Inorganic materials 0.000 claims abstract description 27
- 229910021341 titanium silicide Inorganic materials 0.000 claims abstract description 20
- DDFHBQSCUXNBSA-UHFFFAOYSA-N 5-(5-carboxythiophen-2-yl)thiophene-2-carboxylic acid Chemical compound S1C(C(=O)O)=CC=C1C1=CC=C(C(O)=O)S1 DDFHBQSCUXNBSA-UHFFFAOYSA-N 0.000 claims abstract description 10
- 238000005530 etching Methods 0.000 claims abstract description 9
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 claims abstract description 8
- QGZKDVFQNNGYKY-UHFFFAOYSA-N Ammonia Chemical compound N QGZKDVFQNNGYKY-UHFFFAOYSA-N 0.000 claims abstract description 7
- 239000000758 substrate Substances 0.000 claims description 14
- 238000000034 method Methods 0.000 claims description 12
- 229910052751 metal Inorganic materials 0.000 claims description 9
- 239000002184 metal Substances 0.000 claims description 9
- 238000009792 diffusion process Methods 0.000 claims description 8
- 239000010410 layer Substances 0.000 claims description 8
- 239000011229 interlayer Substances 0.000 claims description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 14
- 239000010703 silicon Substances 0.000 abstract description 14
- 229910052710 silicon Inorganic materials 0.000 abstract description 14
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract description 6
- 229910052814 silicon oxide Inorganic materials 0.000 abstract description 6
- 239000007789 gas Substances 0.000 abstract description 4
- 230000003647 oxidation Effects 0.000 abstract 3
- 238000007254 oxidation reaction Methods 0.000 abstract 3
- 230000002269 spontaneous effect Effects 0.000 abstract 3
- 239000000243 solution Substances 0.000 description 14
- 239000010936 titanium Substances 0.000 description 5
- 235000012431 wafers Nutrition 0.000 description 4
- 238000001020 plasma etching Methods 0.000 description 3
- MHAJPDPJQMAIIY-UHFFFAOYSA-N Hydrogen peroxide Chemical compound OO MHAJPDPJQMAIIY-UHFFFAOYSA-N 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 238000010438 heat treatment Methods 0.000 description 2
- 239000012535 impurity Substances 0.000 description 2
- 238000002955 isolation Methods 0.000 description 2
- 239000011259 mixed solution Substances 0.000 description 2
- 229910021332 silicide Inorganic materials 0.000 description 2
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 2
- 238000004544 sputter deposition Methods 0.000 description 2
- PXGOKWXKJXAPGV-UHFFFAOYSA-N Fluorine Chemical compound FF PXGOKWXKJXAPGV-UHFFFAOYSA-N 0.000 description 1
- 229910021529 ammonia Inorganic materials 0.000 description 1
- 238000000889 atomisation Methods 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000005380 borophosphosilicate glass Substances 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 229910052731 fluorine Inorganic materials 0.000 description 1
- 239000011737 fluorine Substances 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 238000001459 lithography Methods 0.000 description 1
- 239000003595 mist Substances 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は半導体装置の製造方法に関し、特に拡散層表面
上の一部にチタンシリサイド膜が形成されたシリコン半
導体装置の製造において、良好なシリコン半導体／金属
配線接続及びチタンシリザイド／金属配線接続を得るた
めのシリコン上及びチタンシリサイド上の自然シリコン
酸化膜の除去方法に関する。Detailed Description of the Invention [Industrial Application Field] The present invention relates to a method for manufacturing a semiconductor device, and particularly in manufacturing a silicon semiconductor device in which a titanium silicide film is formed on a portion of the surface of a diffusion layer. The present invention relates to a method for removing native silicon oxide on silicon and titanium silicide to obtain semiconductor/metal interconnect connections and titanium silicide/metal interconnect connections.
従来、この種の自然酸化膜の除去方法としては、フッ化
水素と水との混合液により除去する方法か、又はフッ化
水素の含有率（フッ化水素／フッ化アンモニウム＋フッ
化水素（重量比））が３〜５％であるようなフッ化アン
モニウム、フッ化水素、及び水とからなるバッファード
フッ酸溶液により除去する方法があった。Conventionally, this type of natural oxide film has been removed by using a mixture of hydrogen fluoride and water, or by reducing the hydrogen fluoride content (hydrogen fluoride/ammonium fluoride + hydrogen fluoride (by weight)). There is a method of removing the fluorine using a buffered hydrofluoric acid solution consisting of ammonium fluoride, hydrogen fluoride, and water, with a ratio of 3 to 5%.
上述した従来の自然酸化膜の除去方法で用いられている
フッ化水素と水との混合溶液又はバッファードフッ酸液
に対してはチタンシリサイド膜はエツチングされ、その
エツチングレートはシリコン１ｔ４１Ｊのエツチングレ
ートよりも高い。The titanium silicide film is etched by a mixed solution of hydrogen fluoride and water or a buffered hydrofluoric acid solution used in the conventional natural oxide film removal method described above, and the etching rate is the same as that of silicon 1t41J. higher than
したがって、第３図のようにチタンシリサイド膜３０２
とシリコン表面３０３が混在する半導体基板上の自然酸
化膜を従来法によ除去する時、シリコン表面３０３上の
自然酸化膜の除去を十分に行うとチタンシリサイド膜３
０２の除去量も多くなるという問題があり、これは半導
体装置の特性を劣下させる。Therefore, as shown in FIG.
When removing the natural oxide film on the semiconductor substrate on which the silicon surface 303 and the silicon surface 303 coexist by the conventional method, if the natural oxide film on the silicon surface 303 is sufficiently removed, the titanium silicide film 3
There is a problem that the amount of 02 removed also increases, which deteriorates the characteristics of the semiconductor device.
したがって、チタンシリサイド膜の除去量をできるだけ
少なくするために、チタンシリサイド膜のエッチレート
がシリコン酸化膜のエッチレートよりも小さくなるよう
な、自然酸化膜の除去方法が望まれていた。Therefore, in order to reduce the amount of titanium silicide film removed as much as possible, a method for removing the natural oxide film has been desired in which the etch rate of the titanium silicide film is lower than the etch rate of the silicon oxide film.
本発明の自然酸化膜の除去方法は、フッ化水素の含有率
がフッ化水素／フッ化アンモニウム＋フッ化水素（重量
比）５０．５％であるようなフッ化アンモニウム、フッ
化水素及び水とからなるバッファードフッ酸溶液を用い
る。The natural oxide film removal method of the present invention uses ammonium fluoride, hydrogen fluoride and water whose hydrogen fluoride content is hydrogen fluoride/ammonium fluoride + hydrogen fluoride (weight ratio) 50.5%. A buffered hydrofluoric acid solution consisting of
シリコン酸化膜とチタンシリサイド膜とのエッチレート
の比のバッファードフッ酸溶液のフッ化水素含有率に対
する依存性を第４図に示す。この図かられかるように、
フッ化水素の含有率が０．５％以下ではチタンシリサイ
ド膜のエツチングレートはシリコン酸化膜のエツチング
レートよりも小さくなる。FIG. 4 shows the dependence of the etch rate ratio of the silicon oxide film and the titanium silicide film on the hydrogen fluoride content of the buffered hydrofluoric acid solution. As you can see from this diagram,
When the content of hydrogen fluoride is 0.5% or less, the etching rate of the titanium silicide film is lower than the etching rate of the silicon oxide film.
したがって、フッ化水素の含有率０．５％以下のバッフ
ァードフッ酸溶液を用いることにより、チタンシリサイ
ド膜の除去量が従来よりも少なくして、シリコン表面上
の自然酸化膜が除去できる。Therefore, by using a buffered hydrofluoric acid solution with a hydrogen fluoride content of 0.5% or less, the amount of titanium silicide film removed can be reduced compared to the conventional method, and the native oxide film on the silicon surface can be removed.
したがって、良好なシリコン半導体／金属配線接続、及
びチタンシリサイド／金属配線接続が得られ、半導体装
置の特性が向上するという効果がある。Therefore, good silicon semiconductor/metal wiring connections and titanium silicide/metal wiring connections can be obtained, and the characteristics of the semiconductor device are improved.
次に、本発明について図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.
第１図（ａ）〜（ｈ）は本発明の第１の実施例を説明す
るための縦断面図である。FIGS. 1(a) to 1(h) are longitudinal sectional views for explaining a first embodiment of the present invention.
まず、第１図（ａ）に示すように、Ｓｉ基板１０上にＬ
ＯＣＯ８法により膜厚６０００人の素子分離酸化膜１１
を形成する。First, as shown in FIG. 1(a), L is placed on the Si substrate 10.
Element isolation oxide film 11 with a thickness of 6000 using the OCO8 method
form.
次に、第１図（ｂ）に示すように、Ａｓイオンを７０
ｋ ｅＶ、 ５ Ｘ １０１５ｃ＋＋ｒ−２の条件で半
導体基板１０に注入し、９００℃の温度で３０分間熱処
理し、不純物を活性化し、Ｎ＋拡散層１２を形成する。Next, as shown in FIG. 1(b), As ions were added at 70%
The impurities are implanted into the semiconductor substrate 10 under the conditions of keV, 5 x 1015c++r-2, and heat treated at a temperature of 900°C for 30 minutes to activate the impurities and form the N+ diffusion layer 12.
次に、第１図（ｃ）に示すようにＣＶＤ法により半導体
基板全面に膜厚５００人の酸化膜１３を形成した後、一
部のＮ＋拡散層１２上の酸化膜をリアクティブイオンエ
ツチングにより除去する。Next, as shown in FIG. 1(c), an oxide film 13 with a thickness of 500 nm is formed on the entire surface of the semiconductor substrate by the CVD method, and then the oxide film on a part of the N+ diffusion layer 12 is etched by reactive ion etching. Remove.
次に、第１図（ｄ）に示すように、スパッタ法により半
導体基板全面に膜厚１０００人のＴｉ膜１４を形成する
。Next, as shown in FIG. 1(d), a Ti film 14 having a thickness of 1,000 wafers is formed over the entire surface of the semiconductor substrate by sputtering.
次に、第１図（ｅ）に示すように、窒素雰囲気の６００
℃の熱処理により、酸化膜１３におおわれていないＮ＋
拡散層上にＴｉシリサイド膜１５を形成し、板応Ｔｉ膜
１４をアンモニア、過酸化水素、水の混合液により除去
する。Next, as shown in FIG.
Due to the heat treatment at ℃, the N+ that is not covered with the oxide film 13
A Ti silicide film 15 is formed on the diffusion layer, and the plate-forming Ti film 14 is removed using a mixed solution of ammonia, hydrogen peroxide, and water.
次に、第１図（「）に示すように、ＣＶＤ法により膜厚
６０００人のボロンリンガラス（Ｂ Ｐ Ｓ Ｇ）膜１
６を半導体基板全面に形成した後、９００℃３０分の熱
処理によりＢＰＳＧ膜１６をリフローさせる。Next, as shown in FIG.
6 is formed on the entire surface of the semiconductor substrate, the BPSG film 16 is reflowed by heat treatment at 900° C. for 30 minutes.
次に、第１図（ｇ）に示すように、通常のリングラフイ
ー法により１μｍ径のコンタクト形成領域をパターニン
グ後、リアクティブイオンエツチングによりコンタクト
穴１７を形成する。Next, as shown in FIG. 1(g), a contact formation region with a diameter of 1 μm is patterned using the usual phosphorography method, and then a contact hole 17 is formed using reactive ion etching.
次に、第１図（ｈ）に示すように、本発明の請求の範囲
に含まれるフッ化水素含有率０．５％のバッファードフ
ッ酸溶液にこの半導体基板を２００秒入れ、Ｓｉ表面の
自然酸化膜を除去する。その後、スパッタ法により半導
体基板全面にＳｉ含有Ａ４１８を形成し、通常のリソグ
ラフィ法により、バターニング後リアクティブイオンエ
ツチングにより配線を形成する。Next, as shown in FIG. 1(h), this semiconductor substrate was placed in a buffered hydrofluoric acid solution with a hydrogen fluoride content of 0.5%, which is included in the scope of the claims of the present invention, for 200 seconds to remove the Si surface. Remove natural oxide film. Thereafter, Si-containing A418 is formed on the entire surface of the semiconductor substrate by sputtering, and wiring is formed by patterning and reactive ion etching by ordinary lithography.
このようにして、製作されたシリコン半導体装置におい
ては、チタンシリサイド膜１５とＳｉ含有アルミニウム
配線１８とのコンタクト抵抗は３Ω、Ｎ＋拡散層１２と
Ｓｉ含有アルミニウム配線１８とのコンタクト抵抗は２
０Ωと良好なコンタクト特性が得られた。In the silicon semiconductor device thus manufactured, the contact resistance between the titanium silicide film 15 and the Si-containing aluminum wiring 18 is 3Ω, and the contact resistance between the N+ diffusion layer 12 and the Si-containing aluminum wiring 18 is 2Ω.
Good contact characteristics of 0Ω were obtained.
また、自然酸化膜除去のエツチング時間を１００秒から
３００秒まで変えて、コンタクト抵抗の評価を行ったが
、上記と同様のコンタクト抵抗が得られた。したがって
、本発明のバッファードフッ酸溶液はエツチング時間の
マージンが広く、十分使用できるものと確認された。Contact resistance was also evaluated by changing the etching time for removing the native oxide film from 100 seconds to 300 seconds, and the same contact resistance as above was obtained. Therefore, it was confirmed that the buffered hydrofluoric acid solution of the present invention has a wide etching time margin and can be used satisfactorily.
第２図は、本発明の第２の実施例で用いた、自然酸化膜
を除去する装置の縦断面図である。すなわち、第１の実
施例で作成した半導体装置の自然酸化膜を除去するプロ
セス（第１図（ｇ））でこの装置を用いた。FIG. 2 is a longitudinal sectional view of an apparatus for removing a native oxide film used in a second embodiment of the present invention. That is, this apparatus was used in the process of removing the natural oxide film of the semiconductor device produced in the first embodiment (FIG. 1(g)).
この装置を用いた処理プロセスを簡単に説明する。本発
明の特許請求の範囲に記されたバッファードフッ酸溶液
が入れられたバッファードフッ酸溶液タンク２４中の溶
液をバッファードフッ酸霧状化装置２３により霧状化し
、パイプ２５によりこの霧状化した気体をチャンバー２
０に輸送する。The treatment process using this device will be briefly explained. The buffered hydrofluoric acid solution in the buffered hydrofluoric acid solution tank 24 containing the buffered hydrofluoric acid solution described in the claims of the present invention is atomized by the buffered hydrofluoric acid atomizing device 23, and this mist is passed through the pipe 25. The converted gas is transferred to chamber 2.
Transport to 0.
この霧状化気体により、Ｓｉウェハ支えピン２２上のＳ
ｉウェハー２１を処理し、自然酸化膜を除去する。This atomized gas causes the S on the Si wafer support pin 22 to
The i-wafer 21 is processed to remove the native oxide film.
この装置によれば、第１の実施例で得られたと同じ効果
が得られ、更に、消費されるバッファードフッ酸溶液は
低減されるという利点を有する。According to this device, the same effects as obtained in the first embodiment can be obtained, and the additional advantage is that the consumed buffered hydrofluoric acid solution is reduced.
以上説明したように本発明は、フッ化水素の含有率が０
．５％以下のバッファードフッ酸溶液に対するチタンシ
リサイド膜のエツチングレートはシリコン酸化膜のエツ
チングレートよりも小さくなるという特性を用いること
により、チタンシリサイド膜の除去量が従来よりも少な
くて、シリコン表面の自然酸化膜が除去できる。As explained above, the present invention has a hydrogen fluoride content of 0.
．． By using the characteristic that the etching rate of a titanium silicide film in a buffered hydrofluoric acid solution of 5% or less is lower than that of a silicon oxide film, the amount of titanium silicide film removed is smaller than before, and the silicon surface can be removed. Natural oxide film can be removed.
したがって、良好なシリコン半導体／金属配線接続、及
びチタンシリサイド／金属配線接続が得られ、半導体装
置の特性が向上するという効果がある。Therefore, good silicon semiconductor/metal wiring connections and titanium silicide/metal wiring connections can be obtained, and the characteristics of the semiconductor device are improved.
含有Ａρ配線、２１・・・・・・Ｓｉウェハ、２０・・
・・・・チャンバー ２２・・・・・・Ｓｉウェハ支え
ピン、２３・・・・・・バッファードフッ酸溶液霧状化
装置、２４・・・・・・バッファードフッ酸タンク、２
５・・・・・・パイプ。Containing Aρ wiring, 21... Si wafer, 20...
... Chamber 22 ... Si wafer support pin, 23 ... Buffered hydrofluoric acid solution atomization device, 24 ... Buffered hydrofluoric acid tank, 2
5...Pipe.
代理人 弁理士 内 原 晋Agent: Patent Attorney Susumu Uchihara
【図面の簡単な説明】
第１図（ａ）〜（ｈ）は本発明の第１の実施例を説明す
るためのシリコン半導体装置の縦断面図である。第２図
は本発明の第２の実施例に用いた自然酸化膜除去装置を
説明するための縦断面図である。
第３図は従来の技術の問題点を説明するために用いた、
シリコン半導体装置の縦断面図である。第４図は本発明
のバッファードフッ酸溶液の特性を説明するグラフであ
る。
１１・・・・・・素子分離酸化膜、１０・・・・・・Ｓ
ｉ基板、１２・・・・・・Ｎ＋拡散層、１３・・・・・
・酸化膜、１４・・・・・・Ｔｉ膜、１５・・・・・・
Ｔｉシリサイド膜、１６・・・・・・層間絶縁膜、１７
・・・・・・コンタクト穴、１８・・・・・・Ｓｉ／７
コンタクト穴
第１図BRIEF DESCRIPTION OF THE DRAWINGS FIGS. 1(a) to 1(h) are longitudinal sectional views of a silicon semiconductor device for explaining a first embodiment of the present invention. FIG. 2 is a longitudinal cross-sectional view for explaining a natural oxide film removing apparatus used in a second embodiment of the present invention. Figure 3 is used to explain the problems of the conventional technology.
FIG. 2 is a longitudinal cross-sectional view of a silicon semiconductor device. FIG. 4 is a graph explaining the characteristics of the buffered hydrofluoric acid solution of the present invention. 11...Element isolation oxide film, 10...S
i-substrate, 12...N+ diffusion layer, 13...
・Oxide film, 14...Ti film, 15...
Ti silicide film, 16...Interlayer insulating film, 17
...Contact hole, 18...Si/7
Contact hole diagram 1
Claims (2)
形成する工程と、フッ化水素の含有率 （フッ化水素／フッ化アンモニウム＋フッ化水素（重量
比））が０．５％以下であるようなフッ化アンモニウム
、フッ化水素及び水とからなるバッファードフッ酸溶液
により上記半導体基板をエッチングする工程とを含むこ
とを特徴とする半導体装置の製造方法。(1) The process of forming a titanium silicide film on a part of the surface of the semiconductor substrate and the hydrogen fluoride content (hydrogen fluoride/ammonium fluoride + hydrogen fluoride (weight ratio)) of 0.5% or less. A method for manufacturing a semiconductor device, comprising the step of etching the semiconductor substrate with a buffered hydrofluoric acid solution containing ammonium fluoride, hydrogen fluoride, and water.
タンシリサイド膜を形成する工程と、前記半導体基板全
面に層間絶縁膜を形成する工程と、金属配線と前記拡散
層との接続及び、前記金属配線と前記チタンシリサイド
膜との接続をとるためのコンタクト穴を前記層間絶縁膜
に設ける工程と、フッ化水素の含有率（フッ化水素／フ
ッ化アンモニウム＋フッ化水素（重量比））が０．５％
以下であるようなフッ化アンモニウム、フッ化水素、及
び水とからなるのバッファードフッ酸溶液により前記半
導体基板をエッチングする工程と、前記金属配線を形成
する工程とを含むことを特徴とする半導体装置の製造方
法。(2) forming a titanium silicide film on a part of the surface of the diffusion layer provided on the semiconductor substrate; forming an interlayer insulating film on the entire surface of the semiconductor substrate; and connecting metal wiring and the diffusion layer; , a step of providing a contact hole in the interlayer insulating film for connecting the metal wiring and the titanium silicide film, and a hydrogen fluoride content (hydrogen fluoride/ammonium fluoride + hydrogen fluoride (weight ratio)). ) is 0.5%
A semiconductor characterized by comprising the following steps: etching the semiconductor substrate with a buffered hydrofluoric acid solution consisting of ammonium fluoride, hydrogen fluoride, and water; and forming the metal wiring. Method of manufacturing the device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1106253A JP2522389B2 (en) | 1989-04-25 | 1989-04-25 | Method for manufacturing semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1106253A JP2522389B2 (en) | 1989-04-25 | 1989-04-25 | Method for manufacturing semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH02284423A true JPH02284423A (en) | 1990-11-21 |
| JP2522389B2 JP2522389B2 (en) | 1996-08-07 |
Family
ID=14428940
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1106253A Expired - Fee Related JP2522389B2 (en) | 1989-04-25 | 1989-04-25 | Method for manufacturing semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2522389B2 (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH04215436A (en) * | 1990-12-14 | 1992-08-06 | Shin Etsu Handotai Co Ltd | Washing of silicon and its apparatus |
| US6210489B1 (en) | 1996-03-05 | 2001-04-03 | Micron Technology, Inc. | Methods and etchants for etching oxides of silicon with low selectivity |
-
1989
- 1989-04-25 JP JP1106253A patent/JP2522389B2/en not_active Expired - Fee Related
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH04215436A (en) * | 1990-12-14 | 1992-08-06 | Shin Etsu Handotai Co Ltd | Washing of silicon and its apparatus |
| US6210489B1 (en) | 1996-03-05 | 2001-04-03 | Micron Technology, Inc. | Methods and etchants for etching oxides of silicon with low selectivity |
| US6399504B1 (en) | 1996-03-05 | 2002-06-04 | Micron Technology, Inc. | Methods and etchants for etching oxides of silicon with low selectivity |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2522389B2 (en) | 1996-08-07 |
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| Date | Code | Title | Description |
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| LAPS | Cancellation because of no payment of annual fees |