JPH0228379A - Nonvolatile semiconductor memory - Google Patents

Abstract

PURPOSE:To shorten the manufacturing process, to reduce the cost, and to shorten the delivery period by constituting a word line and a bit line out of the same material formed in the same process. CONSTITUTION:A floating gate 5 consisting of polysilicon layer is formed through a gate oxide film 4 in the upper part of a channel region on a P-type silicon substrate 1. A word line 12 and a bit line 13 of Al wiring are formed in parallel with each other through an interlayer insulating film 11 on a floating gate 5. The metallic layers of word line 12 and the bit line 13 are formed in the same process, and their film thicknesses are approximately 5000-12000Angstrom . Hereby, the manufacturing process is simplified, and the delivery period is shortened, and the yield rate is elevated, whereby it can be manufactured cheaply.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention is applicable to EPROMs and E
It relates to nonvolatile semiconductor memories such as EPROMs.

(Prior Art) In a nonvolatile semiconductor memory equipped with a floating gate, information is written by changing the threshold voltage of a MOS transistor of a memory cell depending on whether charge is stored in the floating gate or not.

An example of a conventional FAMO8 type EPROM is shown in FIGS. 6 and 7. 6 is a plan view, and FIG. 7 is a sectional view at the C-0' position.

2 is a P-type silicon substrate, 2 is a drain formed by diffusion of N-type impurities, and 3 is a source formed by diffusion of N-type impurities. A floating gate 5 made of a first polysilicon layer is formed on the channel region with a gate oxide film 4 interposed therebetween, and a control gate 7 made of a second WJ polysilicon layer is formed thereon with a glabella insulating film 6 interposed therebetween. There is. The floating gate 5 is independent for each memory cell, and the control gate 7 is continuous for a plurality of memory cells arranged in the horizontal direction in FIG. 6, forming a word line.

Further, a bit line 8 of metal wiring made of, for example, Aff is formed via an interlayer insulating film.

The bit line 8 is connected to the drain 2 via a contact hole in an interlayer insulating film. The bit line 8 extends in a direction perpendicular to the word line 7 and is connected to a plurality of memory cells arranged vertically in the figure.

10 is a field oxide film, and 15 is a passivation film.

(Problems to be Solved by the Invention) Conventional FAMOS memory cells have a two-layer polysilicon structure, whereas MOS transistors in peripheral circuits have a single-layer polysilicon structure.

To manufacture a semiconductor integrated circuit device including FAMO8,
Two steps of depositing the polysilicon layer are required, two photolithography and etching processes are required for the memory area, and one photolithography and etching process is required for one peripheral area. Thus, the two-layer polysilicon structure lengthens the manufacturing process, resulting in lower yields and, as a result, higher manufacturing costs.

The present invention aims to provide a nonvolatile semiconductor memory that can be manufactured at low cost by simplifying the manufacturing process, shortening delivery time, and increasing yield by forming FAMOS memory cells with a single layer polysilicon structure. This is the purpose.

(Means for Solving the Problems) In the present invention, word lines and bit lines are formed in the same process and made of the same material.

(Example) Figure 1 is a plan view showing an example, and Figure 2 is A-A in Figure 1.
3 is a sectional view taken along the line A, and FIG. 3 is a sectional view taken along line B-BM in FIG.

10 is a field oxide film, with N in the field region.
Type impurities are diffused to form a drain 2 and a source 3. A floating gate 5 made of a polysilicon layer is formed on a channel region on a P-type silicon substrate 1 with a gate oxide film 4 interposed therebetween. The thickness of the floating gate 5 is about 1500 to 4000 people.

A word line 12 and a bit line 13 of AQ wiring are formed in parallel to each other on the floating gate 5 with an interlayer insulating film 11 interposed therebetween. For example, a PSG film, BPSG film, 5OGrfA, etc. is used as the interlayer insulating film 11,
The thickness of the film is about 5,000 to 10,000 people. The metal layers of the word line 12 and bit line 13 are formed by the same process, and have a thickness of about 5,000 to 12,000 layers. The metal layers of word line 12 and bit line 13 may be made of other materials than AQ.

In this example, the word line 12 intersects with the floating gate 5 on the field oxide film 10, and is formed extending over a plurality of memory cells arranged laterally in the figure.

The bit line 13 is formed to extend horizontally in the figure on the field region, and is connected to the drains 2 of a plurality of memory cells arranged in the horizontal direction. 14 is a contact.

15 is a passivation film.

In this embodiment, the EPROM memory cell and the peripheral MOS
The transistors are formed in the same process and can be fabricated with one polysilicon deposition and one photolithography and etching step.

In this embodiment, floating gate 5 and word line 1
Since the interlayer insulating film 11 between 2 and 2 is thick, the capacitance is small, and when a high voltage, for example 14V, is applied to the word line 12 during writing, the potential of the floating gate 5 does not rise sufficiently and E There is a possibility that the δ-inclusion of P ROM becomes shallow.

In order to increase the space between the floating gate 5 and the word line 12 to increase writing, an interlayer insulating film 11 is formed at the intersection of the word line 12 and the floating gate 5 as shown in FIG. 4 or FIG. It is desirable to reduce the film thickness or use a material with a high dielectric constant.

In FIG. 4, an extra photomask process is provided to reduce the thickness of the interlayer insulating film 11 at the intersection of the word line 12 and the floating gate 5 to, for example, about 500 layers.

FIG. 5 shows that after removing the interlayer insulating film 11 at the intersection of the word line 12 and the floating gate 5, a film 161 of a material with a high dielectric constant, such as SiN, is formed.

A film such as Ta205 or a multilayer film of 5 in 2 is deposited thereon.

Even if a process is added to obtain the structure shown in FIG. 4 or 5, the overall process can be significantly shortened compared to the manufacturing process of a two-layer polysilicon structure.

By increasing the capacitance at the intersection of floating gate 5 and word line 12 in this manner, writing can be performed sufficiently.

Writing to and reading from memory cells in the present invention can be performed in the same manner as in the conventional case.

When writing, for example, 14V is applied to the word line 12 and 8V is applied to the bit line 13, so that the threshold voltage of the memory cell to which such a high voltage is applied becomes 7V.
It rises to ~8v. On the other hand, the threshold voltage of a memory cell to which the above-mentioned high voltage is not applied is about 2V.

On the other hand, when reading, for example, 5V is applied to the word line 12, and 2V is applied to the bit line 13, for example.

Since the threshold voltage is high in the memory cells to which writing has been performed, no current flows from the drain 2 to the source 3, whereas current flows in the memory cells to which writing has not been performed. This allows the written information to be read.

In the embodiment shown in FIG. 1, the word line 12 crosses the floating gate 5 on the field oxide film 10 via the interlayer insulating film 11, but this crossing portion can also be provided on the field region.

(Effects of the Invention) In the present invention, since the word line and the bit line are formed in the same process and made of the same material, the manufacturing process is shortened, the manufacturing cost is reduced, and the delivery time is shortened.

Even in the memory cell part, the polysilicon structure becomes a layered structure and one step difference is reduced, making it difficult for defects such as disconnections and short circuits to occur in the wiring, improving yields and reducing costs in this respect as well.

- The layered polysilicon structure provides compatibility with other processes such as the 0MO8 process, and enables on-chip integration of standard cells, EPROMs, and EEPROMs.

[Brief explanation of the drawing]

Fig. 1 is a plan view showing one embodiment, and Fig. 2 is A-A in Fig. 1.
3 is a sectional view taken along the line B-B in FIG. 1, and FIGS. 4 and 5 are sectional views taken at positions corresponding to FIG. 2 in other embodiments. Figure 6 is a plan view showing a conventional EPROM, and Figure 7 is c-c' in Figure 6.
It is a sectional view at a line position. 2...Drain, 3...Source, 5.
... Floating gate, 11 ... Interlayer insulating film, 12 ... Word line, 13 ...
...Bitline.

Claims (1)

[Claims] (1) A non-volatile semiconductor memory that includes a floating gate and has word lines and bit lines formed in the same process and made of the same material.