JPH02281344A - Program running monitor system - Google Patents

Abstract

PURPOSE:To surely monitor the abnormality by providing an order discriminating circuit and issuing an alarm signal a certain time after a restart signal and issuing the restart signal thereafter. CONSTITUTION:First data information or address information on an address bus 101 or a data bus 102 of a CPU 1 is monitored by a monitor means WDT 10. Second address information and plural monitor data information are preliminarily determined in an address information/data information storage circuit 2. First and second address information and data information are sent to comparing circuits 3 and 4. When plural comparisons result in coincidence, discriminating circuits 5 and 6 monitor the order of the occurrence of coincidence. An order discriminating circuit 7 outputs a restart signal 109 to the WDT 10 when circuits 5 and 6 discriminate that the occurrence of coincidence accords with a determined order, thereby surely monitoring the abnormality.

Description

DETAILED DESCRIPTION OF THE INVENTION (Industrial Application Field) Regarding the monitoring of program running status in a CPU, especially its watchdog timer (hereinafter referred to as WDT).
Regarding the method.

(Prior Art) Conventionally, the WDT monitoring method for monitoring the running state of a program includes restart signal sending means for outputting a timer restart signal to a position on the program that is always executed within a certain period of time. , it has been realized by including a WDT for outputting an alarm signal to the outside after a certain period of time has elapsed since the output of the restart signal. In the above monitoring method, when the program is running normally, the WD
T must be restarted within a certain period of time and no alarm signal will be output. In the event of an abnormality, restart is not performed and an alarm signal is output from the WDT. Due to the above-mentioned operation, in the prior art, a monitoring system is configured to monitor the operation of the CPU.

(Problems to be Solved by the Invention) In the conventional WDT monitoring method described above, even if there is an abnormality in the system, only the program that executes the VDT restart command runs, or the WDT restart signal The WDT has a drawback in that it cannot monitor abnormalities if it is output erroneously.

An object of the present invention is to constantly monitor address information on a CPU address bus and data information on a data bus, store a plurality of monitored address information and a plurality of monitored data information, and store address information and data on an address bus. The data information on the bus is compared with multiple pieces of monitored address information and multiple pieces of monitored data information, and if multiple matches are obtained, the order of the matched address information and data information is monitored, and the order is correct. In this case, a restart signal is output, and if the restart signal is not output after a certain period of time, an alarm signal is output to eliminate the above drawback and ensure that abnormalities can be monitored from the WDT4C. The object of the present invention is to provide a structured program running monitoring system.

(Means for Solving the Problems) The program run monitoring method according to the present invention includes a monitoring means,
The apparatus includes a storage means, a plurality of comparison means, a determination means, and a timer means with restart.

The monitoring means is for monitoring the first type of address information on the address bus of the CPU and the first type of data information on the data bus.

The storage means is for storing a plurality of predetermined first type of address information for monitoring and a plurality of predetermined second type of data information for monitoring.

Multiple comparison means are 1. This is for comparing the first and second types of address information and data information with each other.

The determining means is for monitoring the order in which the matches occur if a plurality of matches are obtained from the results of the plurality of comparisons, and outputting Lister No. 91 if the matches are in a predetermined order.

The restart timer means is for outputting an alarm signal when two predetermined times have elapsed since the output of the restart signal.

(Example) Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of a program running monitoring system according to the present invention.

In FIG. 1, 1 is a CPU, 2 is an address information/data information storage circuit, 3 and 4 are first and second comparison circuits, respectively, 5 and 6 are first and second determination circuits, respectively.
7 is an order determination circuit, 8 is a memory circuit, 9 is a peripheral circuit, 1
0 is WDT. Also, 101 is an address bus, 1
02 is a data bus, 103 is a control signal line, 104 is a reset signal line, 105 and 107 are each an address information signal line, 106 and 108 are each a data information signal line, 1
09 is a restart signal line, 110 is an alarm signal line, 1
11 is a clock signal line.

The CPU, memory circuit 8, and peripheral circuit 9 are connected to an address bus 101. Data bus 102. and are coupled by a control signal line 103 that determines their timing. Address bus 1 for the first and second comparator circuit 3.4
01 and a data bus 102 are connected. Information from address information/data information storage circuit 2 and bus 10
The comparison circuit 3.4 compares the information on 1 and 102 and outputs a match or mismatch from the comparison circuit 3.4. When the control signal on the signal line 103 indicates that the address and data have been output on the address bus 101 and the data bus 102, the first and second determination circuits 5.6 determine whether the address and data are identical or Determine line mismatch.

These match signals are input to the order determining circuit 7, and if the match signals are input in a predetermined order, a restart signal is output onto the signal line 109. WDTIO is counted up by the clock input of signal line 111,
After a certain period of time has elapsed, an alarm signal is output onto the signal line 110. When a restart signal is input from the signal line 109, WDTlo is reset and counted up from the initial value. This prevents an alarm signal from being output to the outside.

Although this embodiment shows the case where the address bus and data bus are independent, it is clear that the present invention is applicable even if these buses are common.

(Effects of the Invention) As explained above, the present invention provides the following advantages by monitoring addresses on the address bus and data on the data bus.
Since the running of the program on the CPU can be monitored, W
This has the effect that the program does not need an instruction to instruct the output of a restart signal to the DT. Furthermore, by monitoring whether a plurality of addresses and a plurality of data are running in a predetermined order on a program, the operation of the CPU can be reliably monitored.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of a program running monitoring system according to the present invention. l...CPU 2...Address information/data information storage circuit 3.4...
・Comparison circuit 5.6...Judgment circuit 7...Sequence judgment circuit 8...Memory circuit 9...Peripheral circuit 10...WDT 101.102...Bus 103-111...Signal line

Claims (1)

[Claims] a monitoring means for monitoring the first type of address information on the address bus of the CPU and the first type of data information on the data bus; and a plurality of predetermined second monitoring means.
storage means for storing address information of the type and a plurality of second types of data information for monitoring; and a plurality of storage means for storing the first and second types of address information and data information with each other. a comparing means; and a determining means for monitoring the order in which the matches occur if a plurality of matches are obtained from the results of the plurality of comparisons, and outputting a restart signal if the matches are in a predetermined order; 1. A program run monitoring system comprising: timer means with a restart for outputting an alarm signal when a certain period of time has elapsed since the output of the restart signal.