JPH02280216A - Standby system for data processor - Google Patents

Abstract

PURPOSE:To reduce the energy consumption of a data processor by interrupting the selection of equipment to be controlled which is selected by means of an address outputted on an address bus in a standby condition and reducing a current to flow to the equipment to be controlled. CONSTITUTION:Before a standby mode is in, one part or the whole part of a program at the time of the standby stored in a program area 200 for standby of a ROM 2 is copied to an area 120 of an internal RAM 11 by a controller 1. After the copying is completed, the controller 1 executes the processing while reading program data copied to the area 120, and the standby condition is made at the time of executing an instruction (STOP instruction, etc.) to get in the standby mode. In such a way, the controller 1 stops the access of the equipment to be controlled, all address buss to an address decoder 6 are made into a high level, and the selection line of the equipment to be controlled to be selected is turned off. Thus, in the standby mode, the current to flow to the equipment to be controlled can be suppressed, and the energy consumption can be reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a standby method for a data processing device, and in particular, to reading processing program data from a ROM and transmitting it to a selected controlled device using the output of an address bus. The present invention relates to a standby method for a data processing device that reduces power consumption when the data processing device is placed in a standby state while a controlled device is selected.

[Conventional technology]

The controller of the control device in this type of data processing device uses 8-bit or 16-bit ALU, RA
M, A/D converter, multi-function timer/event counter, general-purpose serial interface, etc. are integrated on a single chip, and memory (ROM/RAM) can be expanded externally, allowing up to 64 bytes of external or internal memory. For example, μP is a CMOS device that is directly addressable, has a standby function, and can hold data with low power consumption.
078G10 etc. (Nippon Denki type), HD6301V etc. (Newly manufactured by Hitachi Seisakusho) etc. are used.

In a data processing device using a controller as described above, when at least one of a plurality of controlled devices is selected, the selected controlled device becomes an operating state C, (active state), which is different from a non-operating state. The structure is such that a large amount of current flows.

Then, even when the controller enters the standby state, the selected control device remains in the active state.

[Problem to be solved by the invention]

In the above conventional technology, even when the data processing device selects a controlled device and enters a standby state (standby mode), the address bus stops accessing the controlled device, that is, the controller Of the outputs, the data bus becomes high impedance, but the address bus holds the next address and does not become high impedance or high level, and the controlled device corresponding to this address remains active and the corresponding There is a problem in that a large amount of current continues to flow through the controlled device, making it difficult to reduce power consumption.

An object of the present invention is to interrupt the selection of the controlled device to be selected by the address on the address bus in the standby state as described above, and to reduce the current that should flow through the controlled device. Accordingly, it is an object of the present invention to provide a standby system for a data processing device that can significantly reduce power consumption of the data processing device.

[Means to solve the problem]

The above purpose is to copy part or all of the standby program stored in the ROM to the controller's internal RAM during standby, and to set all address buses to either high impedance or high level. achieved by

[Effect]

In the standby state, the selection information (address data) of the selected controlled device is stored in the internal RAM of the controller, and the processing after standby is canceled is performed using this internal RAM.
Since it is started by accessing M, there is no need to keep the controlled device in an active state during standby, the current to the controlled device is suppressed, and the current consumption of the entire data processing device is reduced.

〔Example〕

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram of an embodiment of a data processing device according to the present invention, where l is a controller, IO is a CPU, and 1
1 is internal RAM, 2 is ROM, 3 is external RAM, 4 is address bus (AO~A15), 5 is data bus (DO~
D7), 6 is an address decoder, ? a, 7b, 7c, 7
d, 7e, 7f-- are selection lines of controlled devices. Note that both the ROM 2 and the external RAM 3 are controlled devices controlled by the controller l.

In the same figure, controller 1, ROM 2゜external RA
M3. and other breakouts? The Il1 device is connected via an address bus 4 and a data bus 5.
It is configured to be selected by a signal from an address decoder 6 connected to a part of the address decoder 6.

The ROM 2 stores processing programs for external devices and various other processing programs.

2 and 3 are explanatory diagrams of memory areas in the present invention, 20 is a ROM area, 200 is a standby program area in ROM2, 30 is an external RAM area, 110 is an internal RAM area, and 210 is a ROM2 A part of the standby program area 200, 120, is a standby program copy area of the internal RAM area IO.

As shown in the figure, in this example, the ROM area 20 is located at addresses 0000~, and the external RAM area 30 is located at addresses 8000~.
, the internal RAM area 110 is designated as FF00 to FFFF. Internal RAMll0 is fixed to FF00 to FFFF, but external RAM area 30 and ROM area 20 are selectable.

The controller (CPU) 1 reads program data stored in the ROM area 20 and performs processing such as controlling the controlled equipment.

The operation shown in FIG. 1 will be explained below in conjunction with FIGS. 2 and 3.

The controller (CPU) 1 reads program data stored in the ROM area 20 and performs processing such as controlling the controlled equipment.

Then, before entering standby mode, controller 1
copies part or all of the standby program stored in the standby program area 200 of the ROM 2 to the area 120 of the internal RAM II.

After this copying is completed, the controller l processes the program data copied to the area 120 while reading it, and enters the standby state when it executes an instruction to enter the standby mode (such as a STOP instruction).

In this way, the controller 1 stops accessing the controlled device, sets all address buses to the address decoder 6 to high level, and turns off the selection line of the selected controlled device.

The program copied to the internal RAM II also holds the address of the next external device to be selected when entering the standby state.

Thereby, in standby mode, the current flowing through the controlled device is suppressed.

When entering (returning) from the standby mode to the processing mode, the CPU 10 of the controller 1 accesses the copy area 120 of the internal RAM II.

As mentioned above, the copy area holds the address of the controlled device to be selected next after entering standby mode, so when standby mode is canceled, this address is transferred via address bus 4. is supplied to the address decoder 6, decoded and sent to the selection lines 73~
7f selects a predetermined controlled device.

〔Effect of the invention〕

As explained above, according to the present invention, in standby mode, the address bus of the controlled device (address output of the controller) is either high impedance or high level, thereby reducing the power consumption of the data processing device. Therefore, it is possible to provide a data processing device that consumes less power as a whole.

[Brief explanation of drawings]

FIG. 1 is a block diagram of an embodiment of a data processing apparatus according to the present invention, and FIGS. 2 and 3 are explanatory diagrams of a memory area in an embodiment of the present invention. ? 1...Controller, 10...Central processing unit (
CPU), 11...Internal RAM, 2...RO
M, 3...External RAM, 4...Address bus (
AO~A15), 5...Data bus (Do~D?)
, 6...address decoder, ? a, 7b, 7c, 7
d, 7e, 7f... Controlled device selection lines. Figure 3

Claims (1)

[Claims] In a standby system for a data processing device that includes a controller having an internal RAM, a plurality of controlled devices including a ROM connected to the controller via an address bus and a data bus, and an address decoder that provides selection signals to these controlled devices. , when the controller enters a standby state with at least one of the plurality of controlled devices selected, copying part or all of the program at the time of entering the standby state to the internal RAM; A standby method for a data processing device, characterized in that selection of the controlled device is interrupted by setting an address bus to high impedance or high level.