JPH05210623A - Microprocessor and data processor - Google Patents

Abstract

PURPOSE:To connect a data processor to a general purpose microprocessor by the small number of attached circuits by setting operation timing in a first operation mode and a second operation mode to the same. CONSTITUTION:In the case of connecting the data processor to a second microprocessor CPU#11, it is connected directly by signals such as a signal BS# for indicating the start of a bus access, a signal BAT for indicating the type of the bus access, an address for outputting an identifier peculiar to the microprocessor MPU concerned to a part of an output address, and a signal CPST for receiving a state from the microprocessor MPU concerned, etc., and operated by a first operation mode. On the other hand, in the case of connecting the data processor to a third microprocessor, it is connected through a smaller number of attached circuits such as a decoding circuit and an external port and operated by a second operation mode. Also, in this case, operation timing in the first operation mode and a second operation mode is set to the same. Accordingly, it is connected to the general purpose microprocessor, as well through the smaller number of attached circuits.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a technology for constructing a data processing device composed of a plurality of processors, and more particularly, it can be directly connected to a series of microprocessors designed according to the same design concept, and other general-purpose microprocessors. The present invention relates to a microprocessor that can be connected to a processor through a smaller number of accessory circuits, and a data processing device using the microprocessor.

[0002]

2. Description of the Related Art In a conventional microprocessor,
Although it is possible to configure a data processing device by directly connecting to a series of microprocessors designed with the same design concept, for a general-purpose microprocessor in general,
Since the design specifications are different, the data processing device could not be configured except through many attached circuits.

[0003]

Therefore, the conventional microprocessor has a problem that it is difficult to configure a data processing device by connecting to the general-purpose microprocessor.

The present invention solves the above problems,
By providing a first operation mode when directly connected to a series of microprocessors designed with the same design concept and a second operation mode when connected to a general-purpose microprocessor, It is another object of the present invention to provide a microprocessor that can be connected via less attached circuits and a data processing device using the microprocessor.

[0005]

In order to solve the above-mentioned problems, the microprocessor of the first feature of the present invention is as shown in FIG.
As shown in FIG. 2, the signal terminal BS has a bus access space identifier and indicates at least the start of bus access.
#, A signal terminal BAT indicating the type of bus access at the time of data transfer, an address terminal for outputting an identifier unique to the microprocessor to a part of the output address,
A first operation mode including a signal terminal CPST for receiving a state from the microprocessor and performing a variety of processes, and a third microprocessor performing a variety of processes. C
A second operation mode when connected to PU # 2 is provided, and operation timings in the first operation mode and the second operation mode are the same.

The microprocessor of the second aspect of the present invention is the microprocessor according to claim 1, wherein the microprocessor MPU is as shown in FIG.
Does not output the data to the external data bus DBUS for accesses other than the specific register 6 when performing read access when the microprocessor MPU is in the busy state in the first operation mode, The status information of the microprocessor MPU is output.

The microprocessor of the third aspect of the present invention is the microprocessor according to claim 1 or 2, wherein, as shown in FIG. 3, the microprocessor MPU operates in the first operation mode as described above. When performing write access in the busy state, the external data bus DBUS is used for accesses other than the specific register 5.
It does not take in the data from and outputs the status information of the microprocessor MPU.

The microprocessor of the fourth aspect of the present invention is the microprocessor according to claim 1, 2 or 3, wherein the microprocessor MPU has the first operation mode as shown in FIG. In the case where an access by an invalid address or an access to a privilege register occurs in the ready state in which the microprocessor MPU is not operating, error information is output,
The operation in the microprocessor MPU is continued.

The microprocessor of the fifth feature of the present invention is the microprocessor according to claim 1, 2, 3, or 4, wherein the microprocessor MPU is the first microprocessor as shown in FIG. In operating mode,
When access by an invalid address or access to a privilege register occurs in the busy state, the state information of the microprocessor MPU is output.

The microprocessor of the sixth aspect of the present invention is the microprocessor according to any one of claims 1, 2, 3, 4 or 5, wherein the microprocessor MPU is the first microprocessor as shown in FIG. In the operation mode of No. 2, when performing read access during the busy state,
A specific register 6 is accessed for every access.

The microprocessor of the seventh aspect of the present invention is the microprocessor according to claim 1, 2, 3, 4, 5, or 6, wherein the microprocessor MPU is, as shown in FIG. In the second operation mode, when performing write access during the busy state, error information is output for accesses other than the specific register 5.

Further, the data processing device having the characteristics of the present invention is
As shown in FIGS. 1 and 2, claims 1, 2, 3, 4, 5,
6. The microprocessor MPU described in 6 or 7, and the second microprocessor CPU # 1 or the third microprocessor
And a microprocessor CPU # 2 of.

[0013]

In the microprocessor of the first feature of the present invention, when connecting to the second microprocessor CPU # 1, as shown in FIG. 1, a signal BS # indicating the start of bus access and a bus access type. Is directly connected by a signal such as a signal BAT indicating the microprocessor MPU, an address for outputting the identifier unique to the microprocessor MPU to a part of the output address, and a signal CPST for receiving the status from the microprocessor MPU, and the first operation mode is set. To operate.
Further, when connecting to the third microprocessor CPU # 2, as shown in FIG.
02, the external port 103, and the like through a smaller number of attached circuits to operate in the second operation mode. At this time,
The operation timings in the first operation mode and the second operation mode are the same.

Therefore, it can be connected to a general-purpose microprocessor through a smaller number of attached circuits, and its operation is the same timing as when it is directly connected to a series microprocessor designed by the same design concept. Can work with.

Further, in the microprocessor of the second feature of the present invention, as shown in FIG.
When performing a read access in the busy state in the first operation mode, U does not output the data to the external data bus DBUS for access other than the specific register (busy register) 6, and the coprocessor status signal terminal The state information of the microprocessor MPU, that is, a signal indicating that the microprocessor is in the busy state is output to the CPST to notify the second microprocessor CPU # 1 of the state.

Further, in the microprocessor of the third feature of the present invention, as shown in FIG.
When performing a write access in the busy state in the first operation mode, U attempts to access a register other than the specific register (abort register) 5,
By not outputting data from the external data bus DBUS and outputting the status information of the microprocessor MPU, that is, a signal indicating the busy status, to the coprocessor status signal terminal CPST, the second microprocessor CPU # 1 To notify the status.

Further, in the microprocessor of the fourth feature of the present invention, as shown in FIG.
In the first operation mode, U is an access to an invalid address (a register address not in the microprocessor MPU) in the ready state, or a privileged register (a user level) at which access is not permitted (user cannot access, Even when an access to a register related to the operating system occurs, error information is output to the coprocessor status signal terminal CPST, and the second microprocessor CPU #
Although the status is notified to 1, the error is not reflected in the microprocessor MPU and the operation is not stopped.

Further, in the microprocessor of the fifth feature of the present invention, as shown in FIG.
In the first operation mode, when an access by an invalid address or an access to a privilege register occurs in the busy state in the first operation mode, U gives priority to the busy state and outputs error information to the coprocessor status signal terminal CPST. Then, the status is notified to the second microprocessor CPU # 1.

Further, in the microprocessor of the sixth feature of the present invention, as shown in FIG.
In the second operation mode, when the read access is performed in the busy state, the U always accesses the external data path DB by accessing the specific register (busy register) 6 regardless of accessing any other register.
Since the contents of the busy register 6 are output to the US, an indeterminate value is not put on the US, and therefore a malfunction of the system can be prevented.

Further, in the microprocessor of the seventh feature of the present invention, as shown in FIG.
When performing write access in the busy state in the second operation mode, U does not rewrite the contents of the register during operation, and therefore an error occurs in access to any register other than the specific register (abort register) 5, Notify the outside of error information.

[0021]

EXAMPLES First, terms are defined. The “co-pro mode” (first operation mode) means a second microprocessor having the following terminals (hereinafter, CPU # 1 for the sake of distinction).
(Hereinafter referred to as ")", the operating mode of the first microprocessor (hereinafter referred to as MPU).

A signal terminal indicating the start of bus access to the MPU (BS #: bus start signal terminal) A signal terminal having a bus access space identifier and indicating the type of bus access at the time of data transfer (BAT: bus) Access type signal terminal) Address terminal for outputting an identifier ID unique to MPU to a part of the output address Signal terminal for receiving a status signal from MPU (CPST: coprocessor status signal terminal) "Slave mode" (second Operating mode) means M when connected to a third microprocessor (hereinafter referred to as CPU # 2 for distinction) that does not have the above-mentioned terminals
Refers to the operating mode of the PU.

The symbol # added to the signal name and terminal name
Indicates that the signal is a negative logic signal. Next, an embodiment according to the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram of a data processing device constructed by connecting a microprocessor MPU and a microprocessor CPU # 1 according to an embodiment of the present invention, and FIG.
Microprocessor MPU and microprocessor CP
The block diagram of the data processing device comprised by connecting with U # 2 is shown. That is, the microprocessor MPU operates in the coprocessor mode in FIG. 1 and in the slave mode in FIG.

Whether the microprocessor MPU is in the coprocessor mode or the slave mode depends on the external terminal CP /
It is performed by setting the voltage level to SL (co-pro / slave). That is, when the CP / SL terminal is connected to the power supply Vcc, the co-pro mode is set, and when it is connected to the ground GND, the slave mode is set.

First, in the coprocessor mode shown in FIG. 1, the signal connection between the microprocessor CPU # 1 and the microprocessor MPU is direct connection. In this case, among the external terminals of the microprocessor MPU, the bus start signal terminal BS #, the bus access type signal terminal BAT, the ID address terminal CPID, the coprocessor status signal terminal CPST, and the coprocessor / slave signal terminal CP / SL are connected. In addition, a read / write signal terminal R / W # indicating a read bus cycle or a write bus cycle, a data bus DBUS
A data strobe signal terminal DS # indicating that the above data is a valid value, a data transfer end signal terminal DC # indicating that the data acquisition on the MPU side has ended, and terminals A0 to A31 of the 32-bit address bus ABUS. , 64
The terminals D0 to D63 of the bit data bus DBUS are used.

In the slave mode shown in FIG. 2, decoding circuits 101 and 102, external circuits such as an external port 103, etc. are required. A signal 111 obtained by decoding the output address of the microprocessor MPU and the bus access start signal 110 from the microprocessor CPU # 2 by the decode circuit 101 is connected to the chip select terminal CS #. Further, the microprocessor MPU asserts the busy signal terminal BUSY # when the instruction is started to notify that it is in the busy state. This busy signal BUSY #
By polling through the external port 103, the microprocessor CPU # 2 can know the state of the microprocessor MPU.

Also, the coprocessor status signal CPS
As for T, if the external circuit 102 such as a decoding circuit captures the value as data, the state of the microprocessor MPU can be known. still,
The terminal IRQ # is a terminal used when making an interrupt request to the microprocessor CPU # 2.

Next, the internal structure of the microprocessor MPU used in this embodiment will be described with reference to FIG. In the figure, the microprocessor MPU of the present embodiment
As its constituent elements, the arithmetic unit 1, the register unit 2, the internal control circuit 3, the register address generation circuit 4, the abort register 5, the busy register 6, the external bus control circuit 7, the decode circuit 8, the bus access determination circuit 9, and the error. An occurrence notification signal generation circuit 10, a coprocessor status generation circuit 11, and comparison circuits 12 and 13 are provided.

The microprocessor MPU of this embodiment is
The address output from the microprocessor CPU # 1 or CPU # 2 is always decoded by the decode circuit 8, and the microprocessor CPU # 1 or CP
Bus access start signal BS # or CS # from U # 2
Since the bus cycle is started immediately when the assertion of is asserted, high-speed co-pro mode operation and slave operation are possible.

In the coprocessor mode, the comparison circuit 12 compares a part of the address output from the microprocessor CPU # 1 with the ID unique to the microprocessor MPU. If they do not match, the microprocessor MPU is selected by itself. The bus access determination circuit 9 is notified by the signal 61 that there is not. In addition, the bus access type signal BAT from the microprocessor CPU # 1 having a bus access space identifier (herein, defined as BAT: Bus Access Type) is also compared by the comparison circuit 13 and the “microprocessor CPU If it does not indicate the “data transfer cycle from # 1 to the microprocessor MPU”, the bus access determination circuit 9 is notified by the signal 62. In either case, the signal 62 is sent to the external bus control circuit 7, and at this time, the external bus control circuit 7 does not perform the bus cycle even if the assertion of the bus start signal BS # is detected.

As mentioned above, the microprocessor CPU
The state in which the microprocessor MPU is operating after being activated by # 1 or the CPU # 2 is called a busy state. At this time, the internal control circuit 3 outputs a signal indicating the busy state and the external terminal BUSY. # Is asserted.

When the busy signal BUSY # is output as an assert from the internal control circuit 3 in the co-pro mode,
When a read access is made to a register other than the read-only register 6 (hereinafter referred to as a busy register) in the busy state, the following operation is performed. That is, when the result of decoding in the decoding circuit 8 is notified to the bus access determination circuit 9, the bus access determination circuit 9 notifies the external bus control circuit 7 by the signal 62 that the bus access is impossible,
The external bus control circuit 7 does not output data to the data bus DBUS. The coprocessor status generation circuit 11 generates signal information indicating that it is in the busy state, and the external terminal CPST
Output to. The microprocessor CPU # 1 knows from the coprocessor status signal CPST that the microprocessor MPU is busy.

Also, when there is a write access other than the write-only register 5 (hereinafter referred to as an abort register) in the busy state, similarly, the bus access determination circuit 9 notifies the external bus control circuit 7 that the bus cannot be accessed. Therefore, the external bus control circuit 7 does not take in data from the data bus DBUS. Therefore, the register is not accessed, and the contents of the register are not rewritten during operation. Further, as in the case of the read access, the coprocessor status generation circuit 11 outputs signal information indicating that it is in the busy state to the external terminal CPST.

Next, when the microprocessor MPU is busy in the slave mode and read access is performed, as a result of decoding by the decode circuit 8, no matter which register inside the microprocessor MPU is accessed, a register address is generated. The circuit 4 generates the busy register access signal 64, and the busy register 6 is always accessed. Therefore, the value of the busy register 6 is always output to the data bus DBUS, and an indeterminate value is not added, so that the entire data processing device is prevented from malfunctioning.

Further, as described above, the microprocessor M
When PU is busy, busy signal terminal BUSY #
Is asserted, the terminal BUSY # is connected to the external port 10
By polling through 3, microprocessor CPU # 2 knows that microprocessor MPU is busy. At this time, the coprocessor status generation circuit 11 generates signal information indicating a ready state and outputs the signal information to the external terminal CPST to indicate that the register (busy register 6) is accessed.

In the busy state, the abort register 5
If there is a write access other than the above, the bus access determination circuit 9 notifies the external bus control circuit 7 that the bus access is impossible based on the decoding result of the decoding circuit 8. Therefore, the external bus control circuit 7 outputs the chip select signal. Terminal CS
Data is not fetched internally even when # assertion is detected.

The difference from the operation in the co-pro mode is that in the slave mode, the write access to the registers other than the abort register 5 in the busy state causes an error. Therefore, the error occurrence notification signal generation circuit 10 notifies the internal control circuit 3 of the occurrence of the error by the signal 63, and the internal control circuit 3 notifies the outside of the microprocessor MPU that the error has occurred.
Assert Q #. Although the microprocessor MPU itself stops due to an abnormal end due to the occurrence of an error, the coprocessor status generation circuit generates signal information indicating the error and outputs it to the external terminal CPST.

In addition, an address of a register which is not included in the microprocessor MPU is input, or access to a privileged register (register related to an operating system that cannot be accessed by the user) at a level (user level) where access is not permitted is performed. When an error occurs, the bus access determination circuit 9 notifies the external bus control circuit 7 of the result of decoding by the decoding circuit 8, so that the external bus control circuit 7 causes the bus access start signal BS. No bus cycle is performed even if # or CS # is detected. That is, no data is output during a read access and no data is captured during a write access.

At this time, when the microprocessor MPU is in the ready state in the coprocessor mode, the coprocessor status generation circuit 11 generates signal information indicating an error and outputs it to the external terminal CPST. The microprocessor CPU # 1 knows that the current bus access is in error from the information of the terminal CPST, but the error occurrence notification signal IRQ # is not generated inside the microprocessor MPU, and the operation of the microprocessor MPU is caused by the error. There is no stopping. In the busy state, the busy state is prioritized, and the coprocessor status generation circuit 11 outputs busy information to the external terminal CPST even if an error occurs.

In the slave mode, the exception occurrence notification signal generation circuit 10 notifies the internal control circuit 3 of the occurrence of an error by the signal 63, and the microprocessor MP
U itself stops due to an abnormal termination due to the occurrence of an error. The coprocessor status generation circuit 11 also generates signal information indicating an error and outputs it to the external terminal CPST. Further, the internal control circuit 34 uses the interrupt signal IRQ to notify the outside of the microprocessor that an error has occurred.
Assert #.

Next, the bus access operation in the co-pro mode and the slave mode will be described with reference to the timing chart. 4 and 5 are timing charts of bus access in the co-pro mode. In FIG. 4, the basic 2 clock read cycle, the basic 2 clock write cycle, and the 4 clock read cycle are
In FIG. 5, 5 clock read cycles, operation at error occurrence, bus access type (BAT) and M
The operations when the PU unique IDs (CPIDs) do not match are shown.

In the coprocessor mode, the microprocessor MPU starts a bus cycle for data transfer when the assertion of the signal BS # indicating the start of the bus cycle output from the microprocessor CPU # 1 is detected.

At this time, a part of the address output from the microprocessor CPU # 1 is compared with the ID unique to the microprocessor MPU. If they do not match, the microprocessor MPU judges that it is not selected, Do not cycle. If they match, the bus cycle is performed assuming that it is selected. At the same time, the bus access type signal BA from the microprocessor CPU # 1
Even when T does not represent "a data transfer cycle from the microprocessor CPU # 1 to the microprocessor MPU", the bus cycle is not performed. Further, the chip select signal CS # is ignored.

FIGS. 6 and 7 are timing charts of bus access in the slave mode. In FIG. 6, the basic 2 clock read cycle, the basic 2 clock write cycle, and the 4 clock read cycle are
FIG. 7 shows a 5-clock read cycle and an operation when an error occurs.

In the slave mode, when the assertion of the chip select signal CS # is detected, the microprocessor MPU determines that it is selected and starts bus access, and performs a bus cycle. At this time, the bus start signal BS # is ignored.

In the slave mode, the bus access type signal BAT and the address terminal CPID having an ID unique to the microprocessor MPU are invalid.

[0048]

As described above, according to the present invention,
When connecting to the second microprocessor, a signal indicating the start of bus access, a signal indicating the type of bus access, an address for outputting a unique identifier of the microprocessor as part of the output address, and the microprocessor Is directly connected by a signal such as a signal for receiving the state of, and is operated in the first operation mode, and when connecting to the third microprocessor, it is connected through an attached circuit and is connected in the second operation mode. In this case, since the operation timings in the first operation mode and the second operation mode are the same, it is possible to connect to the general-purpose microprocessor through a smaller number of attached circuits,
In addition, it is possible to provide a microprocessor which can operate at the same timing as that of the case where it is directly connected to a series of microprocessors designed by the same design concept, and a data processing device using the microprocessor.

[Brief description of drawings]

FIG. 1 is a microprocessor M according to an embodiment of the present invention.
FIG. 3 is a configuration diagram (co-pro mode) of a data processing device configured by connecting a PU and a CPU # 1.

FIG. 2 is a microprocessor M according to an embodiment of the present invention.
It is a block diagram (slave mode) of a data processing device configured by connecting a PU and a CPU # 2.

FIG. 3 is a microprocessor M according to an embodiment of the present invention.
It is an internal block diagram of PU.

FIG. 4 is a timing chart of bus access in co-pro mode, which is a basic 2 clock read cycle;
It is an operation explanatory view of a basic 2 clock write cycle and a 4 clock read cycle.

FIG. 5 is a timing chart of bus access in the co-pro mode, showing 5 clock read cycles, operation when an error occurs, and bus access type (BA
FIG. 9 is an operation explanatory diagram when T) and the MPU unique ID (CPID) do not match.

FIG. 6 is a timing chart of bus access in slave mode, and is an operation explanatory diagram of a basic 2 clock read cycle, a basic 2 clock write cycle, and a 4 clock read cycle.

FIG. 7 is a timing chart of bus access in the slave mode, and FIG. 7 is an operation explanatory diagram when 5 clock read cycles and an error occur.

[Explanation of symbols]

 1 ... Arithmetic unit 2 ... Register unit 3 ... Internal control circuit 4 ... Register address generation circuit 5 ... Abort register 6 ... Busy register 7 ... External bus control circuit 8 ... Decode circuit 9 ... Bus access determination circuit 10 ... Error occurrence notification signal generation Circuit 11 ... Coprocessor status generation circuit 12, 13 ... Comparison circuit MPU ... (First) microprocessor CPU # 1 ... Second microprocessor CPU # 2 ... Third microprocessor BS # ... Bus start signal (terminal) BAT ... Bus access type signal (terminal) CPID ... MPU unique identifier ID address (terminal) CPST ... Coprocessor status signal (terminal) CP / SL ... Coprocessor / slave signal (terminal) R / W # ... Read / write signal ( Terminal) DS # ... Data strobe signal (terminal) DC # ... Data transfer Transmission end signal (terminal) ABUS ... (External) address bus A0 to A31 ... Address bus ABUS terminal DBUS ... (External) data bus D0 to D63 ... Data bus DBUS terminal CS # ... Chip select signal (terminal) BUSY # ... Busy signal (terminal) CPST ... Coprocessor status signal (terminal) IRQ # ... Interrupt signal (terminal) IAB ... Internal address bus IDB ... Internal data bus 51-53, 61-63 ... Signal 64 ... Busy register access signal 65 ... Abort Register access signals 101, 102 ... Decode circuit 103 ... External port 110 ... Bus access start signal

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Makoto Miyagawa 1015 Kamiodanaka, Nakahara-ku, Kawasaki-shi, Kanagawa Fujitsu Limited

Claims (8)

[Claims] 1. A signal terminal (BS #) having a bus access space identifier and indicating at least the start of bus access.
, A signal terminal (BAT) indicating the type of bus access at the time of data transfer, an address terminal for outputting an identifier peculiar to the microprocessor to a part of the output address, and a signal terminal for receiving the status from the microprocessor. (CPST) and a first operation mode in the case of being connected to a second microprocessor (CPU # 1) that performs various types of processing, and a third microprocessor (CPU # that performs various types of processing).
A microprocessor having a second operation mode when connected to 2), wherein the operation timings in the first operation mode and the second operation mode are the same. 2. The microprocessor (MPU) is
In the first operation mode, when read access is performed when the microprocessor (MPU) is busy, the data is transferred to the external data bus (DBUS) for accesses other than the specific register (6).
The microprocessor according to claim 1, wherein the status information of the microprocessor (MPU) is output without being output to the microprocessor. 3. The microprocessor (MPU) is
In the first operation mode, when performing write access during the busy state, data other than the specific register (5) is not fetched from the external data bus (DBUS), and the microprocessor (MPU) is not fetched. 3. The microprocessor according to claim 1 or 2, wherein the status information of (1) is output. 4. The microprocessor (MPU) comprises:
In the first operation mode, when an access by an invalid address or an access to a privilege register occurs in the ready state in which the microprocessor (MPU) is not operating, error information is output and the microprocessor (MPU) 4. The microprocessor according to claim 1, 2 or 3, wherein the operation of the microprocessor is continued. 5. The microprocessor (MPU) comprises:
In the first operation mode, in the busy state,
When an access by an invalid address or an access to a privilege register occurs, the microprocessor (M
The microprocessor according to claim 1, 2, 3, or 4, which outputs status information of (PU). 6. The microprocessor (MPU) is
The specific register (6) is accessed for all accesses when read access is performed during the busy state in the second operation mode. 5. The microprocessor according to 5. 7. The microprocessor (MPU) is
The error information is output for accesses other than a specific register (5) when performing write access in the busy state in the second operation mode. 5. The microprocessor according to 5 or 6. 8. The microprocessor (MPU) according to claim 1, 2, 3, 4, 5, 6, or 7, and the second.
A microprocessor (CPU # 1) or the third microprocessor (CPU # 2).