JPH02278760A - Semiconductor integrated circuit device - Google Patents
Semiconductor integrated circuit deviceInfo
- Publication number
- JPH02278760A JPH02278760A JP1099111A JP9911189A JPH02278760A JP H02278760 A JPH02278760 A JP H02278760A JP 1099111 A JP1099111 A JP 1099111A JP 9911189 A JP9911189 A JP 9911189A JP H02278760 A JPH02278760 A JP H02278760A
- Authority
- JP
- Japan
- Prior art keywords
- diffusion layer
- conductivity type
- semiconductor substrate
- layer
- buried
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 31
- 238000009792 diffusion process Methods 0.000 claims abstract description 54
- 239000000758 substrate Substances 0.000 claims abstract description 24
- 239000012535 impurity Substances 0.000 claims abstract description 12
- 238000000034 method Methods 0.000 abstract description 2
- 230000015556 catabolic process Effects 0.000 description 11
- 238000010586 diagram Methods 0.000 description 3
- 239000002184 metal Substances 0.000 description 3
- 230000000694 effects Effects 0.000 description 2
- 238000002955 isolation Methods 0.000 description 2
- 230000003068 static effect Effects 0.000 description 2
- 239000003795 chemical substances by application Substances 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 230000001771 impaired effect Effects 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 238000011084 recovery Methods 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
Landscapes
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野1
本発明は半導体集積回路装置の構造に関わり、特に半導
体集積回路装置の静11ii4量を増す構造に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application 1] The present invention relates to the structure of a semiconductor integrated circuit device, and particularly relates to a structure that increases the amount of static 11ii4 in a semiconductor integrated circuit device.
[従来の技術]
半導体集積回路装置の外部端子に加わる静電気等の過電
圧から内部素子を保護するために第5図(a)に示すよ
うな直列抵抗(R)と内部素子の破壊電圧より低い回復
可能なブレークダウン電圧をもつダイオード(Di)に
より構成される保コ舊回路が使用されている。また第5
図(b)の様にダイオードの拡散層抵抗を直列抵抗(R
)と兼用することもある。このダイオードは通常第6図
に示す様に半導体基板10と逆導電型の拡散層11とで
構成されるPN接合で構成されている。基板との接触は
拡散層11を取り囲むように配設された基板と同導電型
の拡散層12を介して表面に引き出される。[Prior Art] In order to protect internal elements from overvoltage such as static electricity applied to the external terminals of a semiconductor integrated circuit device, a series resistance (R) as shown in FIG. 5(a) and a recovery lower than the breakdown voltage of the internal elements are used. A protection circuit consisting of a diode (Di) with a possible breakdown voltage is used. Also the fifth
As shown in Figure (b), the diffusion layer resistance of the diode is the series resistance (R
) may also be used. As shown in FIG. 6, this diode is usually composed of a PN junction composed of a semiconductor substrate 10 and a diffusion layer 11 of the opposite conductivity type. Contact with the substrate is brought out to the surface through a diffusion layer 12 of the same conductivity type as the substrate, which is disposed so as to surround the diffusion layer 11.
[発明が解決しようとする課題]
しかしながら、前述の従来のダイオードは拡散ff1l
lのブレークダウン電圧が曲率半径の小さい拡散層周辺
で決まり、またそれを取り囲むように低抵抗の半導体基
板接触用拡散層12が存在するために主たる電流回路が
周辺部に限定される。そのために電流集中が起こり易く
またその電流集中による発熱による接合破壊或はリーク
電流の増大がおこり該半導体集積回路装置の機能を損な
う。[Problems to be Solved by the Invention] However, the conventional diode described above is a diffused ff1l
The breakdown voltage of 1 is determined around the diffusion layer with a small radius of curvature, and the low resistance diffusion layer 12 for contacting the semiconductor substrate exists surrounding it, so the main current circuit is limited to the periphery. Therefore, current concentration tends to occur, and the junction breakdown or leakage current increases due to heat generated by the current concentration, impairing the functionality of the semiconductor integrated circuit device.
電流経路が限定されていることにより該PN接合の内部
抵抗は高くなり易い、内部抵抗を小さくするためには周
辺長を長くする必要があり表面に占める面積が増大する
。また高い内部抵抗はブレークタウン電圧が低くても大
電流が流れるときその端子間電圧は高くなり保護素子と
しての機能を損なうという問題を有する。そこで本発明
はこのような問題点を解決するもので、その目的とする
ところは電流集中を起こしにくくまた内部抵抗の小さい
表面に占める面積の小さいダイオードを提供することに
ある。Since the current path is limited, the internal resistance of the PN junction tends to increase. In order to reduce the internal resistance, it is necessary to increase the peripheral length, which increases the area occupied on the surface. Further, a high internal resistance has the problem that even if the break-down voltage is low, when a large current flows, the voltage between its terminals becomes high and the function as a protection element is impaired. SUMMARY OF THE INVENTION The present invention is intended to solve these problems, and its purpose is to provide a diode that is less likely to cause current concentration, has a low internal resistance, and occupies a small surface area.
[課題を解決するための手段〕
本発明の半導体集積回路装置は、第1導電型半導体基板
とエピタキシャル層の間に第2導電型埋没拡散層が埋設
されてなり、該エピタキシャル層は第1導電型で半導体
基板の不純物濃度より高くされてなり、該埋没拡散層の
上部表面に該エピタキシャル層より高不純物濃度の第1
導電型拡散層を設けてなることを特徴とする。[Means for Solving the Problems] A semiconductor integrated circuit device of the present invention includes a buried diffusion layer of a second conductivity type buried between a semiconductor substrate of a first conductivity type and an epitaxial layer, and the epitaxial layer is a buried diffusion layer of a first conductivity type. The impurity concentration is higher than that of the semiconductor substrate in the epitaxial layer, and a first layer having an impurity concentration higher than that of the epitaxial layer is formed on the upper surface of the buried diffusion layer.
It is characterized by being provided with a conductive type diffusion layer.
外部端子は第2導電型埋没拡散層に接続されてなり該第
2導電型埋没拡散層と半導体基板及びエピタキシャル層
とでPN接合が形成される。該第1導電型エピタキシャ
ル層の不純物濃度は半導体基板の不純物濃度より高いた
めブレークダウンを埋没拡散層の上部表面側で起こすこ
とができる。The external terminal is connected to the second conductivity type buried diffusion layer, and a PN junction is formed between the second conductivity type buried diffusion layer, the semiconductor substrate, and the epitaxial layer. Since the impurity concentration of the first conductivity type epitaxial layer is higher than the impurity concentration of the semiconductor substrate, breakdown can occur on the upper surface side of the buried diffusion layer.
表面に形成された第1導電型拡散層は内部抵抗を小さ(
すると共に電流が埋没拡散層と対向する面全体で流れる
様に働くために電流集中を起こしにくくすることができ
る。The first conductivity type diffusion layer formed on the surface reduces the internal resistance (
At the same time, since current flows across the entire surface facing the buried diffusion layer, current concentration can be made less likely to occur.
〔実 施 例1
第1図から第3図は、本発明の実施例を示す要部であり
、第1図(a)はダイオードの平面図。[Embodiment 1] FIGS. 1 to 3 show main parts of an embodiment of the present invention, and FIG. 1(a) is a plan view of a diode.
(b)は平面図(a)のA−A’の断面図を。(b) is a sectional view taken along line A-A' in plan view (a).
(c)は断面図(b)のB−B“の不純物濃度を模式的
にあられす1例えば100cmのP型半導体基板lに選
択拡散によりN型拡散層を形成する。この上にエピタキ
シャル法によりP型1Ωcmのエピタキシャル層3を形
成する。このN型拡散層は埋没拡散層2となる。この後
選択酸化により分離酸化1114を形成し上部高濃度P
型拡散層5を、埋没拡散層の引き上げ電極用N型拡散層
6を形成する。5及び6に金属電極7を形成することで
完成する。外部電極は埋没拡散層2に接続され該埋没拡
散層2はP型の半導体基板l及びエピタキシャル層3と
の間でPN接合を形成する。エピタキシャル層の濃度が
半導体基板の濃度より高いためブレークダウンは上部エ
ピタキシャル層との間で起こる。この上部表面に高濃度
P型拡散層5が形成されているのでブレークダウン電流
は埋没It itt層2との対向部全面で、流れる。こ
れにより電流集中が防げるとともに内部抵抗を低くする
ことができる。(c) schematically shows the impurity concentration along line B-B" in cross-sectional view (b).1 For example, an N-type diffusion layer is formed on a 100 cm P-type semiconductor substrate l by selective diffusion. On this, an N-type diffusion layer is formed by epitaxial method. A P-type epitaxial layer 3 of 1 Ωcm is formed. This N-type diffusion layer becomes the buried diffusion layer 2. After that, an isolation oxide 1114 is formed by selective oxidation, and the upper high concentration P is formed.
A type diffusion layer 5 and an N-type diffusion layer 6 for a pulling electrode of a buried diffusion layer are formed. This is completed by forming metal electrodes 7 on 5 and 6. The external electrode is connected to a buried diffusion layer 2, which forms a PN junction with a P-type semiconductor substrate l and an epitaxial layer 3. Since the concentration of the epitaxial layer is higher than the concentration of the semiconductor substrate, breakdown occurs between the epitaxial layer and the upper epitaxial layer. Since the heavily doped P-type diffusion layer 5 is formed on this upper surface, the breakdown current flows over the entire surface facing the buried It itt layer 2 . This prevents current concentration and lowers internal resistance.
第2図(a)〜(C)は別の実施例でありブレークダウ
ン電圧を調整するために埋没拡散層2と高(成度P型拡
散層5との間に中濃度P型拡散層8を形成することによ
り、効果的な保護素子となる。FIGS. 2(a) to 2(C) show another embodiment, in which a medium concentration P-type diffusion layer 8 is placed between the buried diffusion layer 2 and the high (growth P-type diffusion layer 5) to adjust the breakdown voltage. By forming this, it becomes an effective protection element.
また第3図(a)〜(c)は別の実施例でありP型半導
体基板にN型エピタキシャル層を形成し埋没拡散層2を
P型中濃度拡散層8で内包するように形成し第2図の実
施例と同様な構造を形成したものである。このとき中濃
度拡散層8は半導体基板lまで到達している必要がある
。FIGS. 3(a) to 3(c) show another embodiment in which an N-type epitaxial layer is formed on a P-type semiconductor substrate, and a buried diffusion layer 2 is formed so as to be enclosed by a P-type medium concentration diffusion layer 8. This embodiment has a structure similar to that of the embodiment shown in FIG. At this time, the medium concentration diffusion layer 8 must reach the semiconductor substrate l.
第4図は埋没拡散層を保護ダイオードであると同時に保
護抵抗として使用する場合の例を第1図の構造を使用し
てしめす。第4図(a)は平面図を、(b)は断面図を
あられす、ダイオード部の構造は前述の実施例第2図、
第3図であってもよいのはいうまでもない。FIG. 4 shows an example in which the buried diffusion layer is used as a protection diode and a protection resistor at the same time using the structure shown in FIG. 1. FIG. 4(a) shows a plan view, and FIG. 4(b) shows a cross-sectional view.The structure of the diode part is shown in FIG.
It goes without saying that the image shown in FIG. 3 may also be used.
なお、この発明はP、Nの導電型を入れ換えても同様な
効果を持つことはいうまでもない。It goes without saying that the present invention has the same effect even if the conductivity types of P and N are switched.
〔発明の効果1
以上述べたようにこの発明によれば外部端子に接続され
た埋没拡散層とエピタキシャル層とで形成されるPN接
合のブレークダウンを埋没拡散層の上部表面側で起こし
、表面に形成された第1導電型拡散層は内部抵抗を小さ
くすると共に電流が埋没拡散層と対向する面全体で流れ
る様に働(ために電流集中を起こしにくくすることがで
きる。[Effect of the invention 1] As described above, according to the present invention, the breakdown of the PN junction formed between the buried diffusion layer and the epitaxial layer connected to the external terminal occurs on the upper surface side of the buried diffusion layer, and the breakdown occurs on the surface side. The formed first conductivity type diffusion layer reduces the internal resistance and allows current to flow over the entire surface facing the buried diffusion layer (thereby making it difficult to cause current concentration).
これにより保護素子の性能向上がはかられ半導体集積回
路装置の信頼性を向上することができた。This has made it possible to improve the performance of the protection element and improve the reliability of the semiconductor integrated circuit device.
第1図から第4図は本発明の半導体集積回路装置の一実
施例を示す図であり、各々(a)は平面図、(b)はA
−A’の断面図、(c)はB−B′の不純物濃度プロフ
ァイルを示す。
第5図は保護回路の例を示す図。
第6図は従来の保護ダイオードの構造を示す図であり、
(a)は平面図、(b)はA−A’の断面図を示す。
半導体基板
埋没拡散層
エピタキシャル層
分離酸化膜
上部高濃度拡散層
埋没拡散層の引き上げ電橋用拡散層
金属電極
中濃度拡散層
絶縁膜
半導体基板
拡散層
半導体基板接触用拡散層
分離酸化膜
絶1tIll
金属電極
以
出願人 セイコーエプソン株式会社
代理人 弁理士 鈴 木 喜三部(他1名)扇
、A
t。
(&)1 to 4 are diagrams showing one embodiment of the semiconductor integrated circuit device of the present invention, in which (a) is a plan view, and (b) is an A
-A' cross-sectional view, (c) shows the impurity concentration profile of B-B'. FIG. 5 is a diagram showing an example of a protection circuit. FIG. 6 is a diagram showing the structure of a conventional protection diode,
(a) shows a plan view, and (b) shows a cross-sectional view taken along line AA'. Semiconductor substrate buried diffusion layer Epitaxial layer isolation oxide film Top high concentration diffusion layer Pulling up buried diffusion layer Diffusion layer for electrical bridge Metal electrode Middle concentration diffusion layer Insulating film Semiconductor substrate diffusion layer Semiconductor substrate contact diffusion layer Separation oxide film 1tIll Metal electrode Applicant Seiko Epson Co., Ltd. Agent Patent Attorney Kizobe Suzuki (and 1 other person) Ohgi, At. (&)
Claims (1)
電型埋没拡散層が埋設されてなり、該エピタキシャル層
は第1導電型で半導体基板の不純物濃度より高くされて
なり、前記埋没拡散層の上部表面に該エピタキシャル層
より高不純物濃度の第1導電型拡散層を設けてなること
を特徴とする半導体集積回路装置。A buried diffusion layer of a second conductivity type is buried between the first conductivity type semiconductor substrate and the epitaxial layer, the epitaxial layer is of the first conductivity type and has an impurity concentration higher than that of the semiconductor substrate, and the buried diffusion layer is of the first conductivity type and has an impurity concentration higher than that of the semiconductor substrate. 1. A semiconductor integrated circuit device comprising a first conductivity type diffusion layer having a higher impurity concentration than the epitaxial layer on an upper surface thereof.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1099111A JPH02278760A (en) | 1989-04-19 | 1989-04-19 | Semiconductor integrated circuit device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1099111A JPH02278760A (en) | 1989-04-19 | 1989-04-19 | Semiconductor integrated circuit device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH02278760A true JPH02278760A (en) | 1990-11-15 |
Family
ID=14238711
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP1099111A Pending JPH02278760A (en) | 1989-04-19 | 1989-04-19 | Semiconductor integrated circuit device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH02278760A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2013042071A (en) * | 2011-08-19 | 2013-02-28 | Seiko Instruments Inc | Semiconductor device |
-
1989
- 1989-04-19 JP JP1099111A patent/JPH02278760A/en active Pending
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2013042071A (en) * | 2011-08-19 | 2013-02-28 | Seiko Instruments Inc | Semiconductor device |
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