JPH02278734A - Semiconductor integrated circuit device - Google Patents
Semiconductor integrated circuit deviceInfo
- Publication number
- JPH02278734A JPH02278734A JP1099542A JP9954289A JPH02278734A JP H02278734 A JPH02278734 A JP H02278734A JP 1099542 A JP1099542 A JP 1099542A JP 9954289 A JP9954289 A JP 9954289A JP H02278734 A JPH02278734 A JP H02278734A
- Authority
- JP
- Japan
- Prior art keywords
- region
- resistor
- pad
- integrated circuit
- semiconductor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 36
- 239000000758 substrate Substances 0.000 claims description 14
- 238000009792 diffusion process Methods 0.000 claims description 10
- 239000004020 conductor Substances 0.000 claims description 2
- 239000010410 layer Substances 0.000 description 20
- 239000011229 interlayer Substances 0.000 description 4
- 230000015556 catabolic process Effects 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 238000000034 method Methods 0.000 description 3
- 230000006866 deterioration Effects 0.000 description 2
- 230000001681 protective effect Effects 0.000 description 2
- 241000270666 Testudines Species 0.000 description 1
- 210000000078 claw Anatomy 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical group [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 230000002265 prevention Effects 0.000 description 1
- 230000001568 sexual effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/0212—Auxiliary members for bonding areas, e.g. spacers
- H01L2224/02122—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body
- H01L2224/02163—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body on the bonding area
- H01L2224/02165—Reinforcing structures
- H01L2224/02166—Collar structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
Abstract
Description
【発明の詳細な説明】
（イ）産業上の利用分野
本発明は半導体集積回路装置に係り、特にＴ極パッド部
や保護抵抗部に於ける電流のリーク防止に関する。DETAILED DESCRIPTION OF THE INVENTION (A) Field of Industrial Application The present invention relates to a semiconductor integrated circuit device, and particularly to prevention of current leakage in a T-pole pad portion or a protective resistor portion.
（ロ）従来の技術
第３図は、抵抗及びダイオードを用いた入力保護回路の
回路図である。入力パッド（１）は、保護抵抗（２）を
介して入力バッファ（３）に接続され、この人力バッフ
ァ（３）の出力が集積回路装置の内部回路に供給きれる
。そして、保護抵抗（２）と入力バッファ（３）との間
は、一対のダイオード（４）（５）が電源と接地とに夫
々逆方向接続される。このような構成に依れば、入力電
位を電源電位と接地電位との間に補償し、保護回路とし
て働く。(b) Prior Art FIG. 3 is a circuit diagram of an input protection circuit using a resistor and a diode. The input pad (1) is connected to an input buffer (3) via a protective resistor (2), and the output of this manual buffer (3) can be supplied to the internal circuit of the integrated circuit device. Between the protection resistor (2) and the input buffer (3), a pair of diodes (4) and (5) are connected in opposite directions to the power supply and ground, respectively. According to such a configuration, the input potential is compensated between the power supply potential and the ground potential, and the circuit functions as a protection circuit.
次に第４図は、抵抗及びＭｏＳトランジスタを用いた入
力保護回路の回路図である。この入力保護回路に於いて
は、第３図のダイオード（４）（５）に換えてＭＯＳト
ランジスタ（６）が接続される。即ち、抵抗（２）と大
力バッファ（３）との接続点がＭＯＳトランジスタ（６
〉を介して接地され、ＭＯ３Ｉ−ランジスタ（６）のゲ
ートがそのソースに接続される。従って、入力電位が高
くなり、抵抗（２）と出力バッファ（３〉との間の電位
がＭＯＳトランジスタ（６）のソース・ドレイン間耐圧
電位以下に補償される。Next, FIG. 4 is a circuit diagram of an input protection circuit using resistors and MoS transistors. In this input protection circuit, a MOS transistor (6) is connected in place of the diodes (4) and (5) in FIG. That is, the connection point between the resistor (2) and the large-power buffer (3) is the MOS transistor (6
) and the gate of the MO3I transistor (6) is connected to its source. Therefore, the input potential becomes high, and the potential between the resistor (2) and the output buffer (3>) is compensated to be equal to or lower than the source-drain withstand voltage potential of the MOS transistor (6).
第５図は、上述の如き入力保護回路を備えた半導体集積
回路装置の要部平面図であり、第６図は第５図に示すｘ
−ｘ’線断面図である。FIG. 5 is a plan view of a main part of a semiconductor integrated circuit device equipped with the input protection circuit as described above, and FIG.
-x' line sectional view.
Ｎ型の半導体基板（１０）の表面には、ＳｉＯ，からな
る絶縁層（１１）を介してＰｏ１ｙ−５ｉからなる抵抗
（１２）が形成される。そして、ＰＳＧからなる層間絶
縁層（１３）が形成され、この層間絶縁層（１３）上に
Ａ！からなる配線（１４）が形成される。この配線（１
４）は、半導体基板（１０）の端部まで延在されてパッ
ド（１５）を構成すると共に、抵抗（１２）の上部まで
延在され、層間絶縁膜（１３）に設けられたコンタクト
ホール＜１６）を介して抵抗（１２〉に接続される。さ
らに、パッド（１５）領域を除く領域にＳｉＮからなる
表面保護層（１７）が形成される。A resistor (12) made of Po1y-5i is formed on the surface of an N-type semiconductor substrate (10) via an insulating layer (11) made of SiO. Then, an interlayer insulating layer (13) made of PSG is formed, and A! A wiring (14) consisting of the following is formed. This wiring (1
4) extends to the edge of the semiconductor substrate (10) to form a pad (15), and extends to the top of the resistor (12), forming a contact hole provided in the interlayer insulating film (13). 16) to the resistor (12>).Furthermore, a surface protection layer (17) made of SiN is formed in the region excluding the pad (15) region.
そして、パッド（１５）に金線等のワイヤ（１８）がボ
ンディングされて入力信号が供給される。Then, a wire (18) such as a gold wire is bonded to the pad (15) to supply an input signal.
くハ）発明が解決しようとする課題
上述の如き半導体集積回路装置に於いては、高集積化に
伴なって絶縁層（１１）及び層間絶縁層（１３）の層厚
が薄くなると、抵抗（１２）、配線（１４）及びパッド
（１５）と半導体基板（１０）との間の耐圧が低下する
虞れがある。この耐圧の低下に依り、抵抗（１２）やパ
ッド（１５）から半導体基板（１０）側に電流がリーク
し易くなり、装置の信頼性を低下させる。C) Problems to be Solved by the Invention In the semiconductor integrated circuit device as described above, as the thickness of the insulating layer (11) and the interlayer insulating layer (13) becomes thinner as the integration becomes higher, the resistance ( 12) There is a possibility that the breakdown voltage between the wiring (14) and the pad (15) and the semiconductor substrate (10) will decrease. Due to this reduction in breakdown voltage, current tends to leak from the resistor (12) and pad (15) to the semiconductor substrate (10) side, reducing the reliability of the device.
特に、抵抗（１２）の抵抗値が高くなると、パッド（１
５）側からの電流が抵抗（１２）を通らずに半導体基板
（１０）に流れ易くなる。In particular, when the resistance value of the resistor (12) becomes high, the pad (1
5) The current from the side easily flows to the semiconductor substrate (10) without passing through the resistor (12).
また、ワイヤ（１８）をパッド（１５）上にボンディン
グする際、ボンディングの圧力に依って絶縁膜（１１）
や層間絶縁膜（１３）或いは表面保護膜（１７）にクラ
ックが入り、パッド（１５）と半導体基板（１０）との
間の耐圧を低下させる場合がある。Also, when bonding the wire (18) onto the pad (15), the bonding pressure may cause the insulating film (11) to
Cracks may occur in the interlayer insulating film (13) or the surface protection film (17), reducing the breakdown voltage between the pad (15) and the semiconductor substrate (10).
そこで本発明は、パッド（１５）や抵抗（１２）からの
電流のリークに起因する信頼性の低下を防止することを
目的とする。Therefore, an object of the present invention is to prevent a decrease in reliability caused by current leakage from the pad (15) or the resistor (12).
（ニ）課題を解決するための手段
本発明は上述の課題を解決するためのもので、−導電型
の半導体領域上に絶縁層を介して導体或いは半導体の配
線層を形成してなる半導体集積回路装置に於いて、上記
配線層の形成される半導体領域中に逆導電型の拡散領域
を形成すると共に、この拡散領域を上記配線層と同一電
位とし、上記配線層から上記絶縁層を通して上記半導体
領域側への電流の漏−れを防止することを特徴とする。(d) Means for Solving the Problems The present invention is intended to solve the above-mentioned problems, and provides a semiconductor integrated circuit in which a conductor or semiconductor wiring layer is formed on a conductive type semiconductor region via an insulating layer. In the circuit device, a diffusion region of the opposite conductivity type is formed in the semiconductor region where the wiring layer is formed, and the diffusion region is set to the same potential as the wiring layer, and the semiconductor is formed from the wiring layer through the insulating layer. It is characterized by preventing current leakage to the area side.
（＊）作用
本発明に依れば、配線層の下に設けた拡散領域を配、１
ｉ層と同一の電位にバイアスすることで、配線層と拡散
領域との間の電位差がなくなり、絶縁層の耐圧が劣化し
た場合でも、配線層から半導体領域への電流のリークが
生じることがなくなる。(*) Function According to the present invention, the diffusion region provided under the wiring layer is disposed and
By biasing to the same potential as the i-layer, there is no potential difference between the wiring layer and the diffusion region, and even if the withstand voltage of the insulating layer deteriorates, current leakage from the wiring layer to the semiconductor region will not occur. .
くべ）実施例 本発明の一実施例を図面に従って説明する。Kube) Example An embodiment of the present invention will be described with reference to the drawings.
第１図は本発明半導体集積回路装置の要部平面図であり
、第２図は第１図に示すｘ−ｘ’線断面図である。これ
らの図は、第５図及び第６図と同様に抵抗（１２）、パ
ッド（１５）及びこれに連続する配線（１４）部分°を
示しており、第５図及び第６図と同一部分には同一符号
が付しである。FIG. 1 is a plan view of essential parts of the semiconductor integrated circuit device of the present invention, and FIG. 2 is a sectional view taken along the line xx' shown in FIG. 1. These figures show the resistor (12), the pad (15), and the interconnection (14) continuous thereto, similar to FIGS. 5 and 6, and show the same parts as FIGS. 5 and 6. are given the same reference numerals.
本発明の特徴とするところは、抵抗（１２〉及びパッド
（１５）の形成される領域にＰ−Ｗｅｌｌ領域（２０）
を形成し、乙のＰ−Ｗｅｌｌ領域（２０）を抵抗（１２
）やパッド（１５）と同一の電位とすることにある。即
ち、抵抗（１２）及びパッド（１５）を形成すべき領域
に、他のＰ−Ｗｅｌｌ領域と同一の工程でＰ−Ｗｅｌｌ
領域（２０）が形成された後、このＰ−Ｗｅｌｌ領域（
２０）内に抵抗（１２）及びパッド（１５〉が形成され
、抵抗（１２）に接続される配線（１４〉が絶縁膜（１
１）の開口部（２１）からＰ−Ｗｅｌｌ領域（２０）に
接続される。尚、Ｐ−Ｗｅｌｌ領域（２０）の配線（１
４）が接続される領域には、コンタクト抵抗を低減させ
るため、Ｐ−Ｗｅｌｌ領域（２０〉より高濃度のＰ＋領
域（２２〉が形成されている。従って、Ｐ−Ｗｅｌｌ領
域（２０）の電位が抵抗（１２）及びパッド（１５）の
電位の変動に追従し、抵抗（１２）及びパッド（１５）
の電位と略同−電位となるため、電流のリークが発生し
にくく、仮に抵抗（１２）やパッド（１５）から電流が
Ｐ−Ｗｅｌｌ領域（２０）にノークしたとしても、半導
体基板（１０〉上に形成される他の素子の動作に支障を
来すことはない。The feature of the present invention is that a P-well region (20) is provided in the region where the resistor (12) and the pad (15) are formed.
, and connect the P-Well region (20) of B to the resistor (12
) and the pad (15). That is, a P-Well is formed in the region where the resistor (12) and the pad (15) are to be formed in the same process as other P-Well regions.
After the region (20) is formed, this P-Well region (
A resistor (12) and a pad (15>) are formed inside the resistor (12), and a wiring (14>) connected to the resistor (12) is connected to the insulating film (1
1) is connected to the P-Well region (20). Note that the wiring (1) in the P-Well area (20)
4) is connected with a P+ region (22) with a higher concentration than the P-Well region (20) in order to reduce the contact resistance. Therefore, the potential of the P-Well region (20) follows the fluctuation of the potential of the resistor (12) and pad (15), and the resistor (12) and pad (15)
Since the potential is approximately the same as that of the semiconductor substrate (10), current leakage is unlikely to occur, and even if current leaks from the resistor (12) or pad (15) to the P-Well region (20), It does not interfere with the operation of other elements formed above.
このような構造の半導体集積回路装置は、Ｐ −Ｗｅｌ
ｌ領域（２０）やＰ＋領域（２２）を、この半導体基板
（１０）上に形成される他の素子を形成する際の各工程
で同時に形成することが可能であるため、新たな工程の
追加を伴うことなく、従来の工程をそのまま用いて製造
できる。ただし、通常のＰ−Ｗｅｌｌ領域は、一般に接
地電位に固定されるものであり、リーク電流を受けるた
めのＰ−Ｗｅｌｌ領域（２０）は他の領域と電気的に分
離して島状に形成する必要がある。A semiconductor integrated circuit device having such a structure has a P-Wel
Since it is possible to form the l region (20) and the p+ region (22) simultaneously in each step of forming other elements formed on this semiconductor substrate (10), a new step is added. It can be manufactured using conventional processes without any additional steps. However, a normal P-Well region is generally fixed at a ground potential, and the P-Well region (20) for receiving leakage current is electrically isolated from other regions and formed in an island shape. There is a need.
尚、本実施例に於いては、リーク電流を受けるＰ −Ｗ
ｅｌｌ領域（２０）を入力保護回路の抵抗（１２）及び
パッド（１５）部分に設ける場合を例示しているが、入
力保護回路とは関係のない抵抗に対してや、パッドのみ
に対して上述の如きＰ−Ｗｅｌｌ領域（Ｐ型の基板に対
してはＮ−Ｗａｌｌ領域となる）を形成することに依り
リーク電流対策を施すことも可能である。Incidentally, in this embodiment, P-W receiving leakage current
The case where the ELL region (20) is provided at the resistor (12) and pad (15) of the input protection circuit is shown as an example, but the above-mentioned method may be applied to a resistor unrelated to the input protection circuit or only to the pad. It is also possible to take measures against leakage current by forming such a P-Well region (which becomes an N-Wall region for a P-type substrate).
（ト）発明の効果
本発明に依れば、半導体基板上に絶縁層を介して形成さ
れる配線層から電流のリークが防止でき、配線層と半導
体基板との間の耐圧の劣化に依る信頼性の低下を防止で
きる。(G) Effects of the Invention According to the present invention, it is possible to prevent current leakage from the wiring layer formed on the semiconductor substrate via the insulating layer, and to reduce reliability due to deterioration of withstand voltage between the wiring layer and the semiconductor substrate. It can prevent sexual deterioration.
さらに、パッド部分へのワイヤのポンディングの際に絶
縁層にクラックが入り、パッドから半導体基板に電流が
リークしたとしても、半導体基板上に形成された他の素
子の動作に支障を来すことはなく、製造時の歩留りの向
上が望める。Furthermore, even if a crack occurs in the insulating layer when bonding a wire to the pad, and current leaks from the pad to the semiconductor substrate, the operation of other elements formed on the semiconductor substrate may be affected. Therefore, it is possible to improve the yield during manufacturing.
第１図は本発明半導体集積回路装置の要部平面図、第２
図は第１図の断面図、第３図及び第４図は入力保護回路
の回路図、第５図は従来の半導体集積回路装置の要部平
面図、第６図は第５図の断面図である。
第１図
第３図
第２図
第４図
１ｏ：季桐Ｉ裁
１１ ’ ５ｉ０２逆縛１
】２−ＰｏＬｙ−５ｉ ＪＢ机
＋３： ＰＳＧ／ｉ閏絶坊１
１４− △し 自を美力（
１５； ）＼°７ド
１６二 コン９７ト本−ル
１７； Ｓ；Ｎ＆ｅηＪ（象１ 膚
１８： ワイヘＰ
２０； Ｐ−ＷｅＬＬ領１人
２に 関 口（ア
２２； Ｐ″４１入
１； 入ｎへ°７ド
２：（月１爪坑
３： 入カバ、ｙ］１
亀） ２−４オード
６： ＭＯＳトランジスタFIG. 1 is a plan view of essential parts of the semiconductor integrated circuit device of the present invention, and FIG.
The figure is a sectional view of FIG. 1, FIGS. 3 and 4 are circuit diagrams of the input protection circuit, FIG. 5 is a plan view of main parts of a conventional semiconductor integrated circuit device, and FIG. 6 is a sectional view of FIG. 5. It is. Figure 1 Figure 3 Figure 2 Figure 4 1o: Kigiri Isai 11 ' 5i02 Gyakubaku 1 ] 2-PoLy-5i JB desk + 3: PSG/i Banzetsubo 1 14- △shi Self-beauty ( 15 ; Input n to °7 de 2: (month 1 claw hole 3: input cover, y] 1 turtle) 2-4 ode 6: MOS transistor
Claims (3)
いは半導体の配線層を形成してなる半導体集積回路装置
に於いて、 上記配線層の形成される半導体領域に逆導電型の拡散領
域を形成すると共に、 この拡散領域を上記配線層と同一電位とし、上記配線層
から上記絶縁層を通して上記半導体基板側への電流の漏
れを防止せしめたことを特徴とする半導体集積回路装置
。(1) In a semiconductor integrated circuit device in which a conductor or semiconductor wiring layer is formed on a semiconductor region of one conductivity type via an insulating layer, diffusion of an opposite conductivity type is formed in the semiconductor region where the wiring layer is formed. What is claimed is: 1. A semiconductor integrated circuit device, characterized in that a region is formed, and the diffusion region is set at the same potential as the wiring layer to prevent leakage of current from the wiring layer to the semiconductor substrate side through the insulating layer.
他の拡散領域と電気的に分離されて島状に形成されるこ
とを特徴とする請求項第１項記載の半導体集積回路装置
。(2) The semiconductor integrated circuit device according to claim 1, wherein the diffusion region is formed in an island shape electrically isolated from other diffusion regions formed in the semiconductor region.
とで上記拡散領域を上記配線層と同一電位とすることを
特徴とする請求項第１項記載の半導体集積回路装置。(3) The semiconductor integrated circuit device according to claim 1, wherein the wiring layer is electrically connected to the diffusion region so that the diffusion region is at the same potential as the wiring layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1099542A JPH02278734A (en) | 1989-04-19 | 1989-04-19 | Semiconductor integrated circuit device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1099542A JPH02278734A (en) | 1989-04-19 | 1989-04-19 | Semiconductor integrated circuit device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH02278734A true JPH02278734A (en) | 1990-11-15 |
Family
ID=14250074
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1099542A Pending JPH02278734A (en) | 1989-04-19 | 1989-04-19 | Semiconductor integrated circuit device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH02278734A (en) |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6144454A (en) * | 1984-08-09 | 1986-03-04 | Fujitsu Ltd | Semiconductor device |
| JPS62293664A (en) * | 1986-06-12 | 1987-12-21 | Fujitsu Ltd | Protecting circuit of mos integrated circuit |
-
1989
- 1989-04-19 JP JP1099542A patent/JPH02278734A/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6144454A (en) * | 1984-08-09 | 1986-03-04 | Fujitsu Ltd | Semiconductor device |
| JPS62293664A (en) * | 1986-06-12 | 1987-12-21 | Fujitsu Ltd | Protecting circuit of mos integrated circuit |
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