JPH02278347A - Output circuit for debugging data - Google Patents

Abstract

PURPOSE:To automatically output data written in a certain area on a storage device by transferring data from an address shown in a first comparison address register in the storage device to an address shown in a second comparison address register to an output buffer when a counter has counted out. CONSTITUTION:When an execution control part 1 accesses the storage device 2, it outputs the address to an address bus 9. Comparison circuits 5 and 6 respectively compare a value outputted on the address bus 9 with values stored in the comparison address registers 3 and 4. An AND gate 8 outputs a count signal to the counter 10 when coincidence signals from the comparison circuits 5 and 6 come to '1'. A DMA transfer control part 7 DMA-transfers data from the address stored in the comparison address register 3 in the storage device 2 to the address stored in the comparison address register 4 to the output buffer by a count out signal from the counter 10. Thus, data in the storage device can be outputted as for debugging.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a debugging data output circuit for outputting data in a storage device provided in a central processing unit for debugging purposes.

[Conventional technology]

Conventionally, when attempting to view the contents of data that has not been written to a certain address range in the storage device of a central processing unit, if a write is made to the specified address range, the central processing unit must be stopped and the data specified manually. A method is used to read the contents of the address.

[Problem to be solved by the invention]

In the above-mentioned method of stopping the central processing unit, for example when using it as a communication buffer,
Data is written to a certain address range many times in a row, and the data is not collected for a certain number of times, but cannot be stopped during that time, or the output buffer runs out when all the data written multiple times is output. There is such a pressure.

[Means to solve the problem]

The configuration of the debug data output circuit of the present invention includes first and second comparison address registers for storing first and second address information of a storage device of an information processing device, and an address to be given to the storage device. first and second registers that compare the contents of the first and second comparison address registers, respectively;
When the comparison circuit and the first comparison circuit indicate a match, and the second comparison circuit indicates a match before and after that, a count is performed, and a countout is output when the count value reaches a specified value. and a counter to transfer data from the address indicated in the first comparison address register of the storage device to the address indicated in the second comparison address register to an output buffer when this counter counts out. It is characterized in that it is configured to include means for.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram of one embodiment of the present invention. In this figure, 1 is an execution control unit, 2 is a storage device, 3 and 4 are comparison address registers for storing first and second address information, and 5 and 6 are address and comparison registers 5 to be given to the storage device 2. and a comparison path for comparing the contents of 6 and 6, respectively;
7 is a DMA transfer control unit that performs DMA transfer of the data in the storage device 2 indicated by the addresses of the comparison address registers 3 and 4 to the output buffer; and 8 is a DMA transfer control unit that performs DMA transfer of the data in the storage device 2 indicated by the addresses of the comparison address registers 3 and 4; An AND gate for outputting a count signal to the counter 10 and resetting the match signals of the comparison circuits 5 and 6; This is a counter that stores a value indicating the number of times data is stored several times.

When the execution control unit 1 accesses the storage device 2, it outputs the address to the address bus 9. Comparison address registers 3 and 4 hold addresses set from the outside. Comparison circuits 5 and 6 compare the value output on address bus 9 and the values stored in comparison address registers 3 and 4, respectively, and when they match, send a match signal logic "1'" to AND gate 8, respectively. Output. and gate 8
In this case, both match signals from comparator circuits 5 and 6 are “1”
When this happens, a count signal is output to the counter 10, and the comparison circuits 5 and 6 are reset to set the coincidence signal to '0'.
''. The counter 10 is set externally, counts down based on the count signal from the AND gate 8, and outputs a count-out when the count is exhausted.The DMA transfer control unit 7 receives the count-out signal from the counter 10. As a result, data from the address stored in the comparison address register 3 of the storage device 2 to the address stored in the comparison address register 4 is DMA-transferred to the output buffer.

For example, if the execution control unit 1 uses addresses XX to YY of the storage device 2 as a buffer in which communication data is continuously stored many times, and you want to see the contents written there the Zth time. When the comparison address register 3 is
Set X, set YY in comparison address register 4, and set Z in counter 10. Addresses XX and YY are sequentially output to the address bus 9 in order for the execution control unit 1 to write data from addresses XX to YY in the storage device 2. Comparison circuit 5 compares the value output on address bus 9 with the value stored in comparison address register 3, recognizes a match when XX is output on address bus 9, and outputs a match to AND gate 8. The comparison circuit 6 compares the value output on the address bus 9 with the value stored in the comparison address register 4, and when YY is output on the address bus 9, the signal “1'° is output. The match is recognized and a match signal "°1pa" is output to the AND gate 8. AND gate 8 determines that the match signals from comparison circuits 5 and 6 are “1”.
When the match signal becomes "0", it sends a count signal to the counter 1o, resets the comparison circuits 5 and 6, and sets the match signal to "0".
Make it ``. In this way, when the count signal is received from the AND gate 8 seven times, the counter 10 outputs a count-out signal. The DMA transfer control unit 7 has a counter 10
In response to the count-out signal from the storage device 2, the contents of the comparison address register 3 and the comparison address register 4, ``'xx'' and ``Y Y'', are read out.
DMA transfers data from address XX to address YY to the output buffer.

〔Effect of the invention〕

The debugging data output circuit of the present invention includes first and second comparison address registers for storing first and second address information, and an address to be given to a storage device and the first and second comparison address registers. The first and second comparison circuits respectively compare the content and the first comparison circuit indicates a match, and when the second comparison circuit indicates a match before and after that, a count is performed and the specified value is reached. A counter that outputs a countout when the counter has counted out, and data from the address indicated in the first comparison address register of the storage device to the address indicated in the second comparison address register of the storage device to the output buffer when the counter has counted out. Having the transfer means has the effect that data written in a certain area on the storage device can be automatically output without stopping the central processing unit.

[Brief explanation of drawings]

FIG. 1 is an internal configuration diagram of a central processing unit to which a debugging data output circuit of the present invention is applied. 1... Execution control unit, 2... Storage device, 3, 4...
Comparison address register, 5, 6... Comparison circuit, 7...
・DMA transfer control unit, 8...and gate, 9...
Address bus, 10... counter.

Claims (1)

[Claims] first and second comparison address registers for storing first and second address information of a storage device of an information processing device;
First and second comparison circuits each compare the contents of a comparison address register of , and the first comparison circuit performs a count when the first comparison circuit indicates a match, and the second comparison circuit indicates a match before and after that. , a counter that outputs a count-out signal when its count value reaches a specified value, and a counter that outputs a count-out signal when the count value reaches a specified value;
1. A debugging data output circuit comprising means for transferring data from an address indicated in a comparison address register of a second comparison address register to an address indicated in said second comparison address register to an output buffer.