JPH02277303A - Oscillating circuit - Google Patents

Abstract

PURPOSE:To make the oscillating operation stable by obtaining an oscillating output when the phases of levels across a vibrator are opposite to each other. CONSTITUTION:The oscillation is stopped because a level of a signal S1 is at an L level, and since a level of terminals 53, 54 is at an H, a level of a terminal 71-3 is at an L and a signal R is at an L level, then a latch circuit 72 is reset and a signal at an L level is outputted from a terminal (q). Thus, an output side of a tri-state buffer (B) 80 is disconnected, a transistor(TR) 90 is turned on and a level of a terminal 52 goes to an H. With the signal S1 brought into an H level, the oscillation, is started, the TR 90 is turned off, but the terminal 52 keeps the state of H. The voltages at the terminals 53, 54 have a deviated phase and the amplitude increasing. When the voltage difference is sufficiently extended, the latch circuit 72 is set and the signal at the H level is sent from the terminal (q), then the buffer B 80 is in the through-state and an oscillating signal out is obtained from the output terminal 52.

Description

Detailed Description of the Invention (Industrial Application Field) The present invention is applicable to integrated circuits (IC, L
The present invention relates to an oscillation circuit using a resonator such as a crystal built in a SI, VLSI, etc., and particularly to an oscillation circuit that obtains an oscillation output after an unstable oscillation period immediately after the start of oscillation.

(Prior art) Conventionally, as a technology in this field, Japanese Patent Application Laid-Open No. 58-1
There was one described in Publication No. 70119. This oscillation circuit is used as an operating clock signal for a microcomputer, etc. that includes an integrated circuit, and in order to reduce the power consumption of the microcomputer, etc., the oscillation of the oscillation circuit is stopped. In an oscillation circuit using a resonator such as a crystal resonator, the oscillation operation is unstable during a period from when oscillation is started until a predetermined time has elapsed. Therefore, in order to overcome the unstable time when oscillation resumes, the following measures have been taken. The configuration will be explained below using figures.

FIG. 2 is a block diagram showing a conventional oscillation circuit.

This oscillation circuit has an input terminal 2 for a control signal 1)C, an output terminal 3 for oscillation output, and an external connection terminal 4.5 in an integrated circuit 1, and between the input and output terminals 2.3. Oscillator 1
0 and an oscillation control section 20. The oscillation unit 10 has a two-manufactured NAND gate 11, and its first input terminal 11
a is connected to the input terminal 2, and the second input terminal 11b is connected to the capacitor 13 via the external connection terminal 4, and the capacitor 13 is grounded. Further, the output side of the NAND gate 11 is similarly connected to a capacitor 15 via an external connection terminal 5, and the capacitor 15 is grounded. Also, a feedback resistor 16 is connected to the external connection terminal 4.5.
and a crystal resonator 17 are connected in parallel.

The oscillation control section 20 includes an inverter 21 and a flip-flop 22. The inverter 21 includes a P-channel type MO8FET (hereinafter referred to as P-MOS) 21a and an N
Channel type MO8FET (hereinafter referred to as N-MOS)
21b are connected in a complementary manner, and its input side 21c is connected to the external connection terminal 2, and its output side 21d is connected to the reset terminal R of the flip-flop 22. Furthermore, P
-MO32], a, N-A resistor 21e is connected between the train electrodes of MO321b. In addition, the reset terminal R is an external connection terminal 23 for the low power consumption mode signal MC.
The capacitor 24 is connected to a time constant capacitor 24 through the capacitor 24, and the capacitor 24 is grounded. The set terminal S of the flip-flop 22 is connected to the external connection terminal 2, and the output terminal Q is connected to the input terminal 30a of the NAND gate 30. The input terminal 301 of the NAND gate 30 is connected to the output 1 of the NAND gate, and the output 1 of the NAND 30 is connected to the output terminal 3.

The oscillation circuit configured as described above operates as follows.

First, when the control signal PC is at the "Lo" level, the output 2'1d of the inverter 21 becomes the "H" level, and the flip-flop 22 is placed in the reset state.

Next, when the control signal PC becomes H" level, the capacitor 24 starts to be charged via the N'LMO 321b which is in the on state. As a result, the output side 21-
The potential of d begins to decrease. Since the flip-flop 22 is in the reset state, even if the control signal PC is input to the set terminal S, the flip-flop 22 is placed in the reset state by the "H" level signal applied to the reset terminal R.

On the other hand, when the control signal PC reaches the H° level, the oscillator 10 starts oscillating at the same time. After a predetermined time, when the potential on the output side 21d of the inverter 21 falls below the threshold voltage of the Noritub flop 22, the flip-flop P2
2 is se... throated.

Because of this, a B HIT level signal is output to the first input terminal 30a of the N'AND gate 30, and after a delay determined by the time constant of the capacitor 24 and resistor 21e, the NANI) gate 30 is output. The oscillating unit 10 is opened.
The oscillation output of is supplied to the output terminal 3.

In this way, by delaying the oscillation output for a predetermined period of time using the capacitor 24 and the resistor 21e, the unstable time at the start of oscillation can be overcome.

Furthermore, the external connection terminal 23 is also used as an input terminal for a hair signal M'C that controls on/off the oscillation output due to its low power consumption.
- If the external connection terminal 23 is maintained at the #HII level by Ichi, the flip-flop block 22 with reset priority is thereby placed in the reset state, and its l
The NAND gate 30 is activated by the output of l L II level.
remains closed, and no oscillation output is supplied to the output terminal 31.

Thereby, the integrated circuit can be placed in a low power consumption mode without the need to newly provide external connection terminals.

(Problems to be Solved by the Invention) However, the oscillation circuit having the above configuration has the following problems.

Even if the oscillation output is turned off by the mode signal MC, the oscillation unit 1o continues to oscillate, so the oscillation itself continues. Therefore, in order to completely stop oscillation and achieve sufficiently low power consumption, it is necessary to apply the control signal pc from the outside, and one additional external connection terminal must be provided accordingly. This poses a problem in that the circuit formation area increases.

Moreover, the time from the start of oscillation to the activation of the oscillation output depends on the capacitor 24 and resistor 21e, which is unrelated to the oscillation state.
Depending on the power supply voltage and oscillation frequency, the oscillation output may become effective before the oscillation is sufficiently stabilized, or may not become effective even after it has already stabilized, or the oscillation output may become effective even after it has already stabilized. There is a possibility that the oscillation state may not respond appropriately depending on the oscillation state.

The present invention provides an oscillation circuit that solves the problems of the prior art, such as an increase in the circuit formation area and the fact that the oscillation output does not respond accurately to the oscillation state.

(Means for Solving the Problems) In order to solve the above problems, the first invention provides a vibrator that vibrates at a predetermined frequency, and a first control signal that is input to oscillate or oscillate the vibrator. In the oscillation circuit, the oscillation circuit includes an oscillation section having a gate circuit for stopping the vibrator, further comprising: a phase detection means for detecting whether the phases at both ends of the vibrator are in phase or in opposite phases, and outputting a second control signal corresponding thereto; and buffer means for validating or invalidating the oscillation output output from the gate circuit based on the second control signal.

A second invention provides an oscillation circuit including an oscillation section having a vibrator that vibrates at a predetermined frequency and a gate circuit that inputs a control signal to oscillate or stop the vibrator, in which the output from the gate circuit is A buffer means is provided for disabling the oscillation output when the phases at both ends of the vibrator are in the same phase and enabling it when the phases are opposite to each other.

(Function) In the first invention, since the oscillation circuit is configured as described above, the phase detection means detects whether the phases at both ends of the vibrator are in-phase or anti-phase, and outputs a second control signal in accordance with the detected phase. By doing so, it works to overcome the unstable period at the start of oscillation. Further, the buffer means operates based on the second control signal so that the oscillation output is disabled when the phases are in-phase and enabled when the phases are opposite.

In the second invention, since the buffer means is provided as described above, the buffer means disables the oscillation output when the phases at both ends of the vibrator are in the same phase, and enables it when the phases are opposite to each other. This serves to simplify the circuit configuration.

Therefore, the above problem can be solved.

(Embodiment) FIG. 1 is a configuration diagram of an oscillation circuit showing a first embodiment of the present invention.

This oscillation circuit generates a first control signal S] in the integrated circuit 50.
External connection terminal 51 for input. Oscillation signal Qu1. It has an output terminal 52 for output and external connection terminals 53 and 54,
An oscillator 6 is connected between the external connection terminal 51 and the output terminal 52.
o and phase detection means 7°.

The oscillation unit 60 is a circuit that is controlled on and off by the first control signal s1 and sends out an oscillation output of 0LIT, and has a two-manpower NAND game 1-61, and its first input terminal 6
], a is connected to the external connection terminal 51, and the second input terminal 61b is connected to the external connection terminal 51.
is the external connection terminal 53, and the output side 61c is the external connection terminal 5.
4 are connected to each other. External connection terminal 53.54
A feedback resistor 62 and a crystal oscillator 63 are externally connected in parallel, and a capacitor 64.6 is connected between the
5 are connected to each other. In addition, external connection terminal 53
．． 54 are respectively connected to input terminals 70-1 and 70-2 of an exclusive OR gate (hereinafter referred to as EX-OR gate) 7] of the phase detection means 7o.

The phase detection means 70 is a circuit that detects whether the phases at both ends of the crystal oscillator 63 are in-phase or out-of-phase, and outputs a second Ill# signal that is valid only when the phases are out-of-phase. O
It has an R gate 71 and a latch circuit 72. EX-
The OR gate 71 has its output 1 rule 71-3 as the latch time #
First input terminal 7 of I'JAND gate 72a of I72
2 Connected to a-1. The latch circuit 72 for hazard prevention consists of two NAND gates 72a, 72b, 7.
3C, and the second input terminal 72a-2 of the NAND gate 72a is connected to the output terminal 61c of the NAND gate 61 of the oscillation section 60. Furthermore, NAND gates 72b and 73c are cross-connected between the output side of the NAND gate 72a and the reset signal R connected to the external connection terminal 51. Further, the output terminal q of the NAND gate 72b is connected to the control terminal 80 of the tri-state buffer 80.
connected to a.

The tri-state buffer 80 is a circuit that is controlled by the second control signal S2 output from the output terminal q of the NAND gate 72b and supplies the oscillation signal out to the output terminal 52. The input terminal 80b is connected to the output terminal 61c of the NAND gate 61 of the oscillation section 60, and the output terminal 80c is connected to the drain of the pull-up P-M0890.

P'-MO390 has its gate connected to external connection terminal 51,
The sources are each connected to the power supply voltage VCC, and the trains are connected to the output terminal 52.

FIG. 3 is a time chart of FIG. 1, and the operation of FIG. 1 will be explained with reference to this diagram.

In FIG. 3 (A> operation), first, in the initial state period 1, the first control signal S
1 is the ``L'' level, and the oscillation operation of the oscillation section 60 is stopped. At this time, the external connection terminal 54 is "H'"
level, and the capacitor 64 of the external connection terminal 53 is also charged up by the feedback resistor 62, so the level is 11H.
It becomes l+ level. Therefore, EX-OR, gate 7
Since the output terminal 71-3 of 1 is at L level and the reset signal R is also at 71L II level, the latch circuit 72 is reset and the second control signal at L level is output from output terminal q. Tri-state buffer 80
The first output law is a high impedance state (disconnected state). Furthermore, P-MO390 is in the on state.
Therefore, the output terminal 52 is pulled up to the ゛to■'° level.

Here, in the oscillation growth period T2 in which the first control signal S1 reaches the 'H°° level, the oscillation operation of the oscillation section 60 is started. At this time, the P-MO 390 is turned off, but since there is no discharge path in the output terminal 52, it remains at the "H" level. Also, the reset signal R of the latch circuit 72 is turned inactive. On the other hand, the voltage levels V53 and V54 at the external terminals 53 and 54 at both ends of the crystal oscillator 63 initially drop to the "Lll" level, but the phase gradually begins to shift and the amplitude increases, causing the oscillation to grow. .

The operation of FIG. 3(B) At this time, the output terminal 71 of the 'EX-OR gate 71
-3 voltage level V71 is the voltage level V53. When the voltage level difference of V54 increases, it increases, and when it decreases, it decreases. And overall it will rise.

During the subsequent oscillation stabilization period T3, the oscillation is stabilized and the voltage level of external connection terminals 53 and 54 is V53. When the voltage level difference of V54 increases sufficiently, V71 rises higher than the threshold voltage Vt of latch circuit #I72 and becomes "H" level, and both V71 and VS2 become "H" level. The voltage V72 at the output terminal 72a-3 becomes L'' level, and the latch circuit 72 is set.

Operations in FIGS. 3(C) and (D) Then, the second control signal S2 at the H° level is sent from the output terminal q, so the control terminal 80a of the tri-state buffer 80 becomes at the H level. As a result, the tristate buffer 80 enters a through state (passing through), and an oscillation signal out is obtained from the output terminal 52.

This embodiment has the following advantages.

(1-) Since the oscillation signal out is output when the phases at both ends of the crystal oscillator 63 become opposite, stable and good oscillation can be achieved even if the power supply voltage VCC and the oscillation frequency constants are different. A signal out is obtained.

(2) Unlike in the past, a CR delay circuit is not used to overcome the unstable period of the oscillation output OUT when oscillation is restarted, so an external connection terminal for externally connecting a time constant capacitor is provided.・No need.

This allows effective use of limited external connection terminals.

(3) There is a possibility that the output voltage V7 of 71 to EX-OR gate 1 may momentarily drop to "1-" level immediately after reaching +1 HI+ level, but by providing a latch circuit 72, during the oscillation period, Since the H" level is maintained, such hazards can be prevented.

(4) The initial state of the oscillation signal ou t is 11 HI+
level. On the other hand, since the terminal 72a2 of the latch circuit 72 is active at H''', the condition for setting the latch circuit 72 is that VS2 is at the II HI+ level. When the voltage with the terminal 80b is at the same level, the high impedance state becomes through.Therefore, there is no risk that the initial waveform of the oscillation signal OUT will be too short or cause a hazard, and a stable oscillation signal OUT can be generated. Obtainable.

FIG. 4 is a block diagram of an oscillation circuit showing a second embodiment of the present invention.

This oscillation circuit is EX-〇R in the oscillation circuit shown in Figure 1.
The circuit configuration of the gate 71 is simpler than the known one and the latch circuit 72 is omitted, and elements common to those in FIG. 1 are given the same reference numerals.

EX-C)R for phase detection of this oscillation circuit, gate 71a
has input terminals 71a-1 and 71a-2 connected to external connection terminals 53 and 54, respectively, and an input terminal 71a-3 connected to external connection terminal 51 for first control signal S1.

Furthermore, the input terminal 71a-1 is connected to the gate 1 of the P-MOS 71a-5, and the input terminal 71a-2 is connected to the inverter 71a-
The input terminal 71a-3 is connected to the gate of the P-MOS 71a-7 through the inverter 71a-8.
Each is connected to the gate of S71a-9. P
-MOS 71 a, -5 have their sources connected to the power supply voltage VCC, their drains connected to the sources of P-MOS 71 a, -7, respectively, and the (7) P-MOS 71 a -7 no train connected to the drain of N-MOS 71 a-9. It is connected to the. On the other hand, P-MOS 71 a-7 and N-M
One of the capacitors 71a-b is connected between the drains of the OS 71a9, and output terminals 71a and -4 are also connected, and the control terminal 80a of the tri-state buffer 80 is connected to the output terminal 71a-4. . Moreover, the source of the N-MOS 71a-9 and the other of the capacitors are grounded.

Next, the operation will be explained.

First, when the control signal S1 is at the II I, TI level,
The N-MOS 71a-9 is turned on, the capacitors 71a-b are discharged, and the output terminal 71a-4 becomes 11L".
Becomes Rubel. At this time, the potentials of the external connection terminals 5354 are both at "H" level, so the P-MOS 71 a
-5 and P-MO371a7 are in the off state.

Here, when the control signal S1 becomes "H" level, N-M
The OS 71a-"9 is turned off and the oscillation grows. During this time, each time the external connection terminal 53 becomes II L II level and the external connection terminal 54 becomes 'H'° level, the P-MO
S71a-5 and P-MOS71a-7 are turned on, and the potentials of output terminals 71a and -4 rise.

The operation differs from the first embodiment in that the potential of the output terminal 71a-4 rises without changing, and thereafter the operation is almost the same as that of the first embodiment.

In this oscillation circuit, the potential of the output terminal 71a-4 does not rise or fall, so there is no risk of hazard. Therefore, the latch circuit 72 for hazard prevention shown in FIG. 1 can be omitted, and the circuit formation area can be reduced accordingly. Further, since the potential of the output terminal 71a-4 rises with a sufficient delay from the start of oscillation, a stable oscillation output can be obtained.

FIG. 5 is a block diagram of an oscillation circuit showing a third embodiment of the present invention.

This oscillation circuit combines the phase detection means 70 and buffer means 80 shown in FIG. 1 and further simplifies the circuit configuration, and elements common to those in FIG. 1 are given the same reference numerals. ing.

Similar to the first and second embodiments, this oscillation circuit has external connection terminals 51.5B, 54 and an output terminal 52 in the integrated circuit 50, and a gate circuit 61 is connected between the external connection terminals 51.53. has been done.

Furthermore, an inverter 170°17 is connected to the external connection terminal 53.
1 are connected in series, and the external connection terminal 54 has an inverter 1 connected in series.
72 is connected. Output terminal 1 of inverter 171
71a is commonly connected to the gates of P=MO3182 and N-MOS18B of the buffer means 180. The buffer means 180 is connected between the power supply voltage VCC and the ground GPD.
184, its P-MOS181 and N-MOS
Output terminal 17 of inverter 172 is connected to gate 1 of 184.
2a is connected. Also, the drain of P-MOS181 is connected to the source of P-MOS182, and PlVIO818
2 drain is connected to the N-MOS18B train, N-M
The sources of the OS 183 are connected to the drains of the N-MOS 184, respectively.

Furthermore, the drain of P-MOS182 and NIV10
The drain of s18B is commonly connected to the drain of P-MOS 90 and output terminal 52, and the gate of P-MOS 90 is connected to external connection terminal 51.

6(a) to 6(d) are time charts of FIG. 5, and the operation of FIG. 5 will be explained with reference to these figures.

In the period T1 immediately after the start of operation oscillation in FIG. 6 (a>), the external connection terminal 53
．． 54 voltage levels V5B and V54 are both at "H" level. After that, the oscillation growth period T2 begins, and as the oscillation grows, VS2. VB2 gradually increases in amplitude and changes in phase to mutually opposite phases, and the oscillation stabilization period T
3.

The operations V5B and VB2 in FIGS. 6(b) and (c) are performed by inverters 170, 171°
During the oscillation stabilization period T3, each output voltage level V170. V171, V172
has a steep waveform.

Operation Vl in FIG. 6(d), 71. When both Vl and 72 are at “H” level,
N-MOS 183 and 184 are turned on, and buffer means 80
The output becomes 111-I+ level. On the contrary,
V171. When both V172 are at “L” level, P
- Since MOS181 and 182 are turned on, the output is l H
1" level.Furthermore, when 171 and V172 are in a combination other than the above, the output of the buffer means 80 is in a high impedance state. Therefore, V
When 171 and ■172 are in phase, that is, 'V5
When B and VB2 are in opposite phase to C, the output of the buffer means 80 becomes valid and an oscillation signal out is obtained.

This embodiment has the following advantages.

(1) In this embodiment, the initial pulse width may become somewhat shorter or longer or fluctuate.

However, if the oscillation frequency is around IMHz, there is no problem, and the waveform is much improved compared to the unstable waveform at the start of oscillation.

(2) For example, if the time it takes for oscillation to stabilize due to fluctuations in the power supply voltage VCC increases, the oscillation output
The time it takes for the UT to become valid is also longer, compared to the conventional method that uses a CR delay circuit that is unrelated to the oscillation circuit.
Oscillation signal with excellent stability against fluctuations in circuit constants
You can get ut.

Note that the present invention is not limited to the illustrated embodiment, and various modifications are possible. Examples of such modifications include the following.

(I> The latch circuit 72 in FIG. 1 is replaced by another gate circuit,
For example, it may be configured using a NOR gate.

(n) Set the initial value of the output terminal 52 of the first embodiment to II
When setting L 11 level, set P-MOS90 to NM
Replaced with a pull-down circuit by the OS, this N-MOS
The inverted logic of the first control signal S1 is applied to the gate of the latch circuit 72, and the input terminal 72a of the latch circuit 72
It is sufficient to invert the logic of -2 (1) The capacitor 712tb of the second embodiment may be connected to the inputs of several dummy inverters, or may be a parasitic capacitance of the circuit itself.

(IV) In the first to third embodiments, a crystal oscillator was used as the oscillator, but a piezoelectric ceramic oscillator, for example, may be used instead.

(Effects of the Invention) As explained in detail below, according to the present invention, it is possible to detect whether the phases at both ends of the vibrator are in-phase or anti-phase, and to obtain an oscillation output only when the phases are anti-phase. Therefore, the unstable oscillation during the oscillation start period of the oscillation section can be reliably overcome, and a highly stable oscillation output can be obtained.

Further, there is no need to provide an external connection terminal for a low power consumption mode signal in order to realize low power consumption of an integrated circuit as in the conventional case, and the circuit formation area is reduced accordingly.

Therefore, if the oscillator of the present invention is used as an oscillator for clock signals of a microcomputer, for example,
A highly stable and excellent clock signal can be obtained.

[Brief explanation of drawings]

Fig. 1 is a block diagram of an oscillation circuit showing the embodiment of the present invention, Fig. 2 is a block diagram of a conventional oscillation circuit, Fig. 3 is a time chart of Fig. 1, and Fig. 4 is a block diagram of a conventional oscillation circuit. A configuration diagram of an oscillation circuit showing a second embodiment, FIG. 5 is a configuration diagram of an oscillation circuit showing a third embodiment of the present invention, and FIG. 6 is a time chart 1 of FIG.
・. 50...Integrated circuit, 5], 53.54...External connection terminal, 52.
...output terminal, 60...oscillation section, 61...
・・Gate circuit, 63・・Crystal resonator, 70・
... Phase detection means, 7] ... EX-OR gate, 72 ... Lana circuit, 80 ... Tri-state buffer, 180 ...
. . . Buffer means, Sl, S2 . . . 1-1 second control signal. OUT...Oscillation output, out...Oscillation signal. 2...1

Claims (1)

[Scope of Claims] 1. An oscillation circuit comprising an oscillation unit having a vibrator that vibrates at a predetermined frequency and a gate circuit that inputs a first control signal to oscillate or stop the vibrator, comprising: a phase detection means for detecting whether the phases at both ends of the vibrator are in-phase or anti-phase and outputting a second control signal accordingly; and an oscillation output output from the gate circuit based on the second control signal. An oscillation circuit characterized in that it is provided with buffer means for enabling or disabling the oscillation circuit. 2. In an oscillation circuit including an oscillation unit having a vibrator that vibrates at a predetermined frequency and a gate circuit that inputs a control signal to oscillate or stop the vibrator, the oscillation output output from the gate circuit is An oscillation circuit characterized in that the oscillation circuit is provided with a buffer means which is disabled when the phases at both ends of the vibrator are in the same phase and enabled when the phases are opposite to each other.